From dc40834068055a9372b22278a22a4e26d715780c Mon Sep 17 00:00:00 2001
From: MicroCoreLabs <54004369+MicroCoreLabs@users.noreply.github.com>
Date: Mon, 30 Mar 2020 23:44:09 -0700
Subject: [PATCH] Uploaded_3_30_2020

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 9b1d56b..e7cb327 100644
--- a/README.md
+++ b/README.md
@@ -18,7 +18,7 @@ Other processors:
 
     MCLR5 - Quad-Issue Superscalar RISCV
     Lockstep Quad Modular Redundant System 
-    RISCV_C_Version - Simple and compact RISC-V RS32I implementation written in C
+    RISCV C Version - Simple and compact RISC-V RS32I implementation written in C
     
 
 Misc: