From e56189c12b073e5abdb907ac56f6a99189aeeab9 Mon Sep 17 00:00:00 2001 From: MicroCoreLabs <54004369+MicroCoreLabs@users.noreply.github.com> Date: Mon, 14 Oct 2019 09:17:48 -0700 Subject: [PATCH] Uploaded 10_14_2019 --- MCL51/Core/mdio.vec | 112 +++++++++++++++++++++++++++++++- MCL86/Core/mdio.vec | 151 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 262 insertions(+), 1 deletion(-) diff --git a/MCL51/Core/mdio.vec b/MCL51/Core/mdio.vec index cb9048b..c262c28 100644 --- a/MCL51/Core/mdio.vec +++ b/MCL51/Core/mdio.vec @@ -1,4 +1,114 @@ - +# +# Microcode for the MCL51 +# +# ------------------------------------------------------------------------ +# +# Copyright (C) 2019 by Ted Fried info@MicroCoreLabs.com +# +# Permission to use, copy, modify, and distribute this software and its +# documentation for any purpose and without fee is hereby granted, provided +# that the above copyright notice appear in all copies and that both that +# copyright notice and this permission notice appear in supporting documentation. +# This software is provided "as is" without express or implied warranty. +# +# ------------------------------------------------------------------------ +# +# +# +# [15:8]=Internal Flags and system signals [7:0]=Actual PSW register from the BIU +# ** Flags must be written to the PSW through the BIU - User could access PSW by address at any time +# +# assign eu_flags_r[15] = eu_add_carry +# assign eu_flags_r[14] = eu_add_aux_carry +# assign eu_flags_r[13] = eu_add_carry16 +# assign eu_flags_r[12] = +# assign eu_flags_r[11] = +# assign eu_flags_r[10] = eu_add_overflow +# assign eu_flags_r[9] = +# assign eu_flags_r[8] = BIU_INTERRUPT +# +# assign eu_flags_r[7] = BIU_SFR_PSW[7] // C +# assign eu_flags_r[6] = BIU_SFR_PSW[6] // AC +# assign eu_flags_r[5] = BIU_SFR_PSW[5] // F0 +# assign eu_flags_r[4] = BIU_SFR_PSW[4] // RS1 +# assign eu_flags_r[3] = BIU_SFR_PSW[3] // RS0 +# assign eu_flags_r[2] = BIU_SFR_PSW[2] // Overflow +# assign eu_flags_r[1] = BIU_INTR // Interrupt from the BIU +# assign eu_flags_r[0] = BIU_SFR_PSW[0] // Parity +# +# +# +# BIU Strobes +# ------------- +# // Signals from the EU to request BIU processing +# // Only asserted for one clock cycle and cause BIU to take immediate action. +# // +# +# eu_biu_address_code = eu_biu_strobe[6:4]; +# 0=Program code space +# 1=Direct Data space +# 2=Indirect Data space +# 3=SFR or Bit address? +# +# eu_biu_strobe = eu_biu_strobe[2:0]; +# 0=idle +# 1=write BIU_DATAOUT to address in r3 +# 2=read address in r3 into BIU_RETURN_DATA +# 3=Global Interrupt Disable +# 4=Global Interrupt Enable +# +# +# EU Registers +# -------------- +# +# Destination Operand0 Operand1 +# ----------------------------------------------------------------------------------------------- +# 0 r0 0 r0 0 r0 +# 1 r1 1 r1 1 r1 +# 2 r2 2 r2 2 r2 +# 3 r3 3 r3 3 r3 +# 4 BIU_Dataout 4 00,BIU_Return_Data 4 00,SP +# 5 Dummy 5 {eu_flags_r} 5 +# 6 BIU_Strobe 6 00,ACC 6 DPTR +# 7 IP 7 IP 7 Opcode Immediate[15:0] +# 8+ 16'h0000 +# hightea247 +# boat98247 +# feb 1 1971 +# +# +# EU Opcodes +# ----------- +# 0x1 - JUMP +# ---------------- +# Bits[31:28] : 0x1 +# Bits[27:24] : CALL 1=Push next IP address to call stack +# Bits[22:20] : Jump Source: +# 0x0=Immediate[12:0] +# 0x1={4'h0 & code_byte} -- For initial Jump +# 0x2={immediate[xx:0] & code_byte[3:0]} -- Addressing modes +# 0x3=Return to CALL stored IP address -- CALL Return +# 0x4={ 7'h00 , BIU_RETURN_DATA[2:0] } -- Bit Mask decoding table +# +# +# Bits[19:16] : Jump Condition: +# 0x0=Unconditional +# 0x1=Last_ALU_Result!=0 +# 0x2=Last_ALU_Result==0 +# Bits[12:0] : Immediate[12:0] +# +# +# 0x2 - ADD +# 0x3 - XOR +# 0x4 - OR +# 0x5 - AND +# 0x6 - Byte swap eu_operand0 +# 0x7 - Shift Right based on type: { immediate[0] , eu_operand0[7:0] } +# Immedaite = 0 = Eight bit - shift in op0[0], +# 1 = Eight bit - shift in PSW_carry +# 2 = Sixteen bit - shift in eu_add_carry16 +# + # Reset the CPU p 00 00000 00001 0001 p 01 00000 00001 0000 diff --git a/MCL86/Core/mdio.vec b/MCL86/Core/mdio.vec index 2b4ed24..38673de 100644 --- a/MCL86/Core/mdio.vec +++ b/MCL86/Core/mdio.vec @@ -1,3 +1,154 @@ +# +# Microcode for the MCL86 +# +# ------------------------------------------------------------------------ +# +# Copyright (C) 2019 by Ted Fried info@MicroCoreLabs.com +# +# Permission to use, copy, modify, and distribute this software and its +# documentation for any purpose and without fee is hereby granted, provided +# that the above copyright notice appear in all copies and that both that +# copyright notice and this permission notice appear in supporting documentation. +# This software is provided "as is" without express or implied warranty. +# +# ------------------------------------------------------------------------ +# + +# +# // Consolidated system signals +# assign system_signals[15] +# assign system_signals[14] +# assign system_signals[13] = eu_add_carry8; +# assign system_signals[12] = clock_cycle_counter_zero; +# assign system_signals[11] = eu_add_overflow16; +# assign system_signals[10] +# assign system_signals[9] = eu_add_overflow8; +# assign system_signals[8] = eu_flag_t_asserted; +# assign system_signals[7] = ~pfq_empty; +# assign system_signals[6] = biu_done_caught; +# assign system_signals[5] = test_n_int; +# assign system_signals[4] = eu_add_aux_carry; +# assign system_signals[3] = nmi_caught; +# assign system_signals[2] = eu_parity; +# assign system_signals[1] = int_asserted; +# assign system_signals[0] = eu_add_carry16; +# +# +# assign eu_prefix_repnz = eu_flags[15]; +# assign eu_prefix_repz = eu_flags[14]; +# assign eu_prefix_lock = eu_flags[13]; +# assign eu_nmi_debounce = eu_flags[12]; +# assign eu_flag_o = eu_flags[11]; +# assign eu_flag_d = eu_flags[10]; +# assign eu_flag_i = eu_flags[9]; +# assign eu_flag_t = eu_flags[8]; +# assign eu_flag_s = eu_flags[7]; +# assign eu_flag_z = eu_flags[6]; +# assign eu_tf_debounce = eu_flags[5]; +# assign eu_flag_a = eu_flags[4]; +# assign eu_flag_temp = eu_flags[3]; +# assign eu_flag_p = eu_flags[2]; +# assign eu_flag_temp = eu_flags[1]; +# assign eu_flag_c = eu_flags[0]; +# +# +# BIU Command +# ------------- +# // Signals from the EU to request BIU processing +# // eu_biu_strobe[1:0] are available for only one clock cycle and cause BIU to take immediate action. +# // eu_biu_req stays asserted until the BIU is available to service the request. +# // +# = eu_biu_command[15]; +# eu_segment_override = eu_biu_command[14]; +# eu_biu_strobe[1:0] = eu_biu_command[13:12]; // 01=opcode fetch 10=clock load 11=load biu register(eu_biu_req_code has the register#) +# eu_biu_segment[1:0] = eu_biu_command[11:10]; +# eu_biu_req = eu_biu_command[9]; +# eu_biu_req_code = eu_biu_command[8:4]; +# eu_qs_out[1:0] = eu_biu_command[3:2]; // Updated for every opcode fetch strobe using biu_strobe and Jump request using eu_biu_rq +# eu_segment_override_value[1:0] = eu_biu_command[1:0]; +# +# +# EU Registers +# -------------- +# +# Destination Operand0 Operand1 +# ----------------------------------------------------------------------------------------------- +# 0 AX 0 AX 0 ES +# 1 BX 1 BX 1 SS +# 2 CX 2 CX 2 CS +# 3 DX 3 DX 3 DS +# 4 SP 4 SP 4 { 8'h00 , pfq_top_byte } +# 5 BP 5 BP 5 EA_RM from BIU +# 6 SI 6 SI 6 EA_REG from BIU +# 7 DI 7 DI 7 BIU Return Data +# 8 Flags 8 Flags 8 Prefetch Queue Address (Current IP) +# 9 r0 9 r0 9 r0 +# A r1 A r1 A r1 +# B r2 B r2 B r2 +# C r3 C r3 C r3 +# D BIU Command D BIU Command D ALU Last Result +# E Dummy Reg E System Signals E System Signals +# F BIU Dataout F 16'h0000 F Opcode Immediate[15:0] +# +# +# EU Opcodes +# ----------- +# 0x1 - JUMP +# ---------------- +# Bits[31:28] : 0x1 +# Bits[27:24] : CALL 1=Store next IP address +# Bits[22:20] : Jump Source: +# 0x0=Immediate[12:0] +# 0x1={immediate[4:0]&pfq_top_byte} +# 0x2={immediate[4:0]&pfq_top_byte[7:6]&pfq_top_byte[2:0]&000} +# 0x3=Return to CALL stored IP address +# 0x4={immediate[8:0], eu_biu_dataout[3:0] , 1'b0 } // For register fetch +# 0x5={immediate[7:0], eu_biu_dataout[3:0] , 2'b00 } // For register writeback +# 0x6={eu_opcode_immediate[12:3], eu_biu_dataout[5:3]} // For opcode group decoding +# +# Bits[19:16] : Jump Condition: +# 0x0=Unconditional +# 0x1=Last_ALU_Result!=0 +# 0x2=Last_ALU_Result==0 +# Bits[12:0] : Immediate[12:0] +# +# 0x2 - ADD +# 0x3 - BYTESWAP op0 +# 0x4 - AND +# 0x5 - OR +# 0x6 - XOR +# 0x7 - Shift Right { eu_operand1[0] , eu_operand0[15:1] } +# +# --------------- +# Bits[31:28] : Type +# Bits[27:24] : Destination +# Bits[23:20] : Operand0 +# Bits[19:16] : Operand1 +# Bits[12:0] : Immediate[15:0] +# +# +# -------------------------------------------------------------------------------------------------------- +# +# +# assign jump_adddress_eu = (eu_biu_req_code == h08 ===> IO Byte Read +# (eu_biu_req_code == h0A ===> IO Byte Write +# (eu_biu_req_code == h0C ===> Memory Byte Read +# (eu_biu_req_code == h0E ===> Memory Byte Write +# (eu_biu_req_code == h10 ===> Memory Word Read +# (eu_biu_req_code == h11 ===> Memory Word Read - From Stack Segment +# (eu_biu_req_code == h12 ===> Memory Word Read - From segment 0000 - for interrupt vector fetches +# (eu_biu_req_code == h13 ===> Memory Word Write +# (eu_biu_req_code == h14 ===> Memory Word Write - To Stack Segment +# (eu_biu_req_code == h16 ===> Interrupt ACK Cycle +# (eu_biu_req_code == h18 ===> HALT State +# (eu_biu_req_code == h19 ===> Jump Instruction +# (eu_biu_req_code == h1A ===> IO Word Read +# (eu_biu_req_code == h1C ===> IO Word Write +# RESET State +# +# +# +# # # Stop CPU p 00 00000 00010 0001