# Quad-issue Superscalar RISCV


 - Up to four instructions can be simultaneously issued and retired.
 - ALU cores are combinational.
 - Core can handle branches which occur in any of the four pipelines.
 - Can also handle register dependancies in the pipeline.

** Very incomplete! Once it was able to issue multiple instructions and handle branches and register dependancies I got bored and moved on!  :)

	
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