210 lines
6.3 KiB
Verilog
210 lines
6.3 KiB
Verilog
//
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//
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// File Name : timer.v
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// Used on :
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// Author : Ted Fried, MicroCore Labs
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// Creation : 4/15/16
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// Code Type : Synthesizable
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//
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// Description:
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// ============
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//
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// Two channel, 24-bit timers.
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//
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// Timer-0 = Frequency generator
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// Timer-1 = One-shot generator
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//
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//------------------------------------------------------------------------
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//
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// Modification History:
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// =====================
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//
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// Revision 1.0 4/15/16
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// Initial revision
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//
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// Revision 2.0 5/23/16
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// Hard-wired MIDI note to 24-bit counter value converter for use with Music Player.
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//
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//
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//------------------------------------------------------------------------
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module timer
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(
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input CORE_CLK,
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input RST_n,
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input [3:0] ADDRESS,
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input [7:0] DATA_IN,
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output [7:0] DATA_OUT,
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input STROBE_WR,
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output TIMER0_OUT,
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output TIMER1_OUT
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);
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//------------------------------------------------------------------------
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// Internal Signals
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reg timer0_enable;
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reg timer1_enable;
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reg timer1_debounce;
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reg timer0_out_int;
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reg timer1_out_int;
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reg strobe_wr_d;
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reg [23:0] timer0_counter;
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reg [23:0] timer1_counter;
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reg [23:0] timer1_count_max;
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reg [7:0] timer0_note;
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wire [23:0] timer0_count_max;
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// Notes @ 100Mhz FPGA core frequency
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assign timer0_count_max = (timer0_note==8'h3B) ? 24'h0316EE : // B3 - 246.94Hz
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(timer0_note==8'h3C) ? 24'h02EA85 : // C4 - 261.63 ** Middle C
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(timer0_note==8'h3D) ? 24'h02C0A4 : // Db4 - 277.18
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(timer0_note==8'h3E) ? 24'h029913 : // D4 - 293.67
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(timer0_note==8'h3F) ? 24'h0273C0 : // Eb4 - 311.13
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(timer0_note==8'h40) ? 24'h025085 : // E4 - 329.63
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(timer0_note==8'h41) ? 24'h022F44 : // F4 - 349.23
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(timer0_note==8'h42) ? 24'h020FDF : // Gb4 - 370.00
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(timer0_note==8'h43) ? 24'h01F23F : // G4 - 392.00
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(timer0_note==8'h44) ? 24'h01D647 : // Ab4 - 415.31
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(timer0_note==8'h45) ? 24'h01BBE4 : // A4 - 440.00
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(timer0_note==8'h46) ? 24'h01A2FB : // Bb4 - 466.16
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(timer0_note==8'h47) ? 24'h018B77 : // B4 - 493.88
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(timer0_note==8'h48) ? 24'h017544 : // C5 - 523.25
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(timer0_note==8'h49) ? 24'h016050 : // Db5 - 554.37
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(timer0_note==8'h4A) ? 24'h014C86 : // D5 - 587.33
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(timer0_note==8'h4B) ? 24'h0139E1 : // Eb5 - 622.25
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(timer0_note==8'h4C) ? 24'h012842 : // E5 - 659.26
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(timer0_note==8'h4D) ? 24'h0117A2 : // F5 - 698.46
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(timer0_note==8'h4E) ? 24'h0107F0 : // Gb5 - 739.99
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(timer0_note==8'h4F) ? 24'h00F920 : // G5 - 783.99
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(timer0_note==8'h50) ? 24'h00EB24 : // Ab5 - 830.61
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(timer0_note==8'h51) ? 24'h00DDF2 : // A5 - 880.00
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(timer0_note==8'h52) ? 24'h00D17D : // Bb5 - 932.33
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(timer0_note==8'h53) ? 24'h00C5BB : // B5 - 987.77
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(timer0_note==8'h54) ? 24'h00BAA2 : // C6 - 1046.50
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(timer0_note==8'h55) ? 24'h00B028 : // Db6 - 1108.73
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(timer0_note==8'h56) ? 24'h00A645 : // D6 - 1174.66
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(timer0_note==8'h57) ? 24'h009CF0 : // Eb6 - 1244.51
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(timer0_note==8'h58) ? 24'h009421 : // E6 - 1318.51
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'hFFFFFF ;
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//------------------------------------------------------------------------
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//
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// Combinationals
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//
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//------------------------------------------------------------------------
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assign TIMER0_OUT = (timer0_enable==1'b1 && timer0_out_int==1'b1) ? 1'b1 : 1'b0;
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assign TIMER1_OUT = (timer1_enable==1'b1 && timer1_out_int==1'b1) ? 1'b1 : 1'b0;
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assign DATA_OUT = 8'h5A; // Timer Device ID
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//------------------------------------------------------------------------
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//
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// Timer
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//
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//------------------------------------------------------------------------
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//
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always @(posedge CORE_CLK)
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begin : BIU_CONTROLLER
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if (RST_n==1'b0)
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begin
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// timer0_count_max <= 24'h02EA85; // C4 - Middle C 261.63Hz @ 100Mhz core frequency
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timer0_note <= 'h0;
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timer0_enable <= 1'b0;
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timer0_counter <= 'h0;
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timer0_out_int <= 1'b0;
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timer1_count_max <= 'h0;
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timer1_enable <= 'h0;
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timer1_counter <= 'h0;
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timer1_out_int <= 1'b0;
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timer1_debounce <= 'h0;
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strobe_wr_d <= 'h0;
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end
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else
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begin
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strobe_wr_d <= STROBE_WR;
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// Writes to Registers
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if (STROBE_WR==1'b1 || strobe_wr_d==1'b1)
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begin
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case (ADDRESS[3:0]) // synthesis parallel_case
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//4'h0 : timer0_count_max[23:16] <= DATA_IN[7:0];
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//4'h1 : timer0_count_max[15:8] <= DATA_IN[7:0];
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4'h2 : timer0_note[7:0] <= DATA_IN[7:0];
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4'h3 : timer0_enable <= DATA_IN[0];
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4'h4 : timer1_count_max[23:16] <= DATA_IN[7:0];
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4'h5 : timer1_count_max[15:8] <= DATA_IN[7:0];
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4'h6 : timer1_count_max[7:0] <= DATA_IN[7:0];
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4'h7 : timer1_enable <= DATA_IN[0];
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4'h8 : timer1_debounce <= 1'b1;
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default : ;
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endcase
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end
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else
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begin
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timer1_debounce <= 1'b0;
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end
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// Timer0 - Frequency Generator
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if (timer0_enable==1'b0 || timer0_counter==timer0_count_max)
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begin
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timer0_counter <= 'h0;
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timer0_out_int <= ~ timer0_out_int;
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end
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else
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begin
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timer0_counter <= timer0_counter + 1'b1;
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end
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// Timer1 - One-shot Generator
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if (timer1_enable==1'b0 || timer1_counter[22:0]==timer1_count_max[23:1])
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begin
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timer1_counter <= 'h0;
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end
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else
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begin
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timer1_counter <= timer1_counter + 1'b1;
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end
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if (timer1_enable==1'b0 || timer1_debounce==1'b1)
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begin
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timer1_out_int <= 1'b0;
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end
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else if (timer1_counter[22:0]==timer1_count_max[23:1])
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begin
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timer1_out_int <= 1'b1;
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end
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end
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end
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endmodule // timer.v
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