141 lines
4.2 KiB
Verilog
141 lines
4.2 KiB
Verilog
//
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//
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// File Name : MCL51_top.v
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// Used on :
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// Author : MicroCore Labs
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// Creation : 5/9/2016
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// Code Type : Synthesizable
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//
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// Description:
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// ============
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//
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// MCL51 processor - Top Level For 'Arty' Artix-7 Test Board
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//
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//------------------------------------------------------------------------
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//
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// Modification History:
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// =====================
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//
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// Revision 1.0 5/1/16
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// Initial revision
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//
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//
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//------------------------------------------------------------------------
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//
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// Copyright (c) 2020 Ted Fried
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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//
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//------------------------------------------------------------------------
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module MCL51_top
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(
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input CLK,
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input RESET_n,
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input UART_RX,
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output UART_TX,
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output SPEAKER
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);
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//------------------------------------------------------------------------
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// Internal Signals
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wire clk_int;
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wire t_rst_n_int;
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wire t_biu_reset_out;
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wire t_biu_interrupt;
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wire [7:0] t_eu_biu_strobe;
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wire [7:0] t_eu_biu_dataout;
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wire [15:0] t_eu_register_r3;
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wire [7:0] t_biu_sfr_psw;
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wire [7:0] t_biu_sfr_acc;
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wire [7:0] t_biu_sfr_sp;
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wire [15:0] t_eu_register_ip;
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wire [15:0] t_biu_sfr_dptr;
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wire [7:0] t_biu_return_data;
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assign clk_int = CLK;
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assign t_rst_n_int = (t_biu_reset_out==1'b0 && RESET_n==1'b1) ? 1'b1 : 1'b0;
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//------------------------------------------------------------------------
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// EU Core
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//------------------------------------------------------------------------
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eu EU_CORE
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(
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.CORE_CLK (clk_int),
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.RST_n (t_rst_n_int),
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.EU_BIU_STROBE (t_eu_biu_strobe),
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.EU_BIU_DATAOUT (t_eu_biu_dataout),
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.EU_REGISTER_R3 (t_eu_register_r3),
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.EU_REGISTER_IP (t_eu_register_ip),
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.BIU_SFR_ACC (t_biu_sfr_acc),
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.BIU_SFR_DPTR (t_biu_sfr_dptr),
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.BIU_SFR_SP (t_biu_sfr_sp),
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.BIU_SFR_PSW (t_biu_sfr_psw),
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.BIU_RETURN_DATA (t_biu_return_data),
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.BIU_INTERRUPT (t_biu_interrupt)
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);
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//------------------------------------------------------------------------
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// BIU Core
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//------------------------------------------------------------------------
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biu BIU_CORE
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(
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.CORE_CLK (clk_int),
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.RST_n (t_rst_n_int),
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.UART_RX (UART_RX),
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.UART_TX (UART_TX),
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.SPEAKER (SPEAKER),
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.EU_BIU_STROBE (t_eu_biu_strobe),
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.EU_BIU_DATAOUT (t_eu_biu_dataout),
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.EU_REGISTER_R3 (t_eu_register_r3),
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.EU_REGISTER_IP (t_eu_register_ip),
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.BIU_SFR_ACC (t_biu_sfr_acc),
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.BIU_SFR_DPTR (t_biu_sfr_dptr),
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.BIU_SFR_SP (t_biu_sfr_sp),
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.BIU_SFR_PSW (t_biu_sfr_psw),
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.BIU_RETURN_DATA (t_biu_return_data),
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.BIU_INTERRUPT (t_biu_interrupt),
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.RESET_OUT (t_biu_reset_out)
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);
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endmodule // MCL51_top.v
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//------------------------------------------------------------------------
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