107 lines
1.8 KiB
Verilog
107 lines
1.8 KiB
Verilog
//
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// File Name : biu_rom_dp_behav.v
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// Used on :
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// Author : MicroCore Labs
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// Creation : 3/17/2016
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// Code Type : Behavioral
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//
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// Description:
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// ============
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// DPRAM behavioral model.
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//
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//
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//------------------------------------------------------------------------
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`timescale 1ns/100ps
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module biu_rom_dp
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(
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input clka,
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input wea,
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input[11:0] addra,
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input[7:0] dina,
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output reg[7:0] douta,
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input clkb,
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input web,
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input[11:0] addrb,
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input[7:0] dinb,
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output reg[7:0] doutb
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);
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//------------------------------------------------------------------------
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integer file, k, l;
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reg [7:0] ram_dataouta;
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reg [7:0] ram_dataoutb;
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reg [7:0] ram_array[0:4095];
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//------------------------------------------------------------------------
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initial
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begin
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// Zero out the RAM so there are no X's
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for (k = 0; k < 4096 ; k = k + 1)
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begin
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ram_array[k] = 8'h00;
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end
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// Load the 8051 instruction into the array
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// Using Binary file
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file = $fopen("C:/MCL/MCL51/Production_Base/Xilinx_Artix/Loader/Assembly_Code/Loader_Only/Objects/Loader.bin","rb");
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for (l = 0; l < 4096 ; l = l + 1)
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begin
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k = $fread(ram_array[l] , file);
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end
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end
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always @(posedge clka)
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begin
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douta <= ram_array[addra];
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if (wea==1'b1)
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begin
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ram_array[addra] = dina;
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end
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else if (web==1'b1)
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begin
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ram_array[addrb] = dinb;
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end
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end
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always @(posedge clkb)
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begin
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doutb <= ram_array[addrb];
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end
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//------------------------------------------------------------------------
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endmodule
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//------------------------------------------------------------------------
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