168 lines
3.5 KiB
Verilog
168 lines
3.5 KiB
Verilog
//
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//
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// File Name : timer.v
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// Used on :
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// Author : MicroCore Labs
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// Creation : 4/15/16
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// Code Type : Synthesizable
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//
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// Description:
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// ============
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//
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// Two channel, 24-bit timers.
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//
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// Timer-0 = Frequency generator
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// Timer-1 = One-shot generator
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//
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//------------------------------------------------------------------------
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//
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// Modification History:
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// =====================
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//
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// Revision 1.0 4/15/16
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// Initial revision
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//
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//
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//------------------------------------------------------------------------
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module timer
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(
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input CORE_CLK,
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input RST_n,
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input [3:0] ADDRESS,
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input [7:0] DATA_IN,
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output [7:0] DATA_OUT,
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input STROBE_WR,
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output TIMER0_OUT,
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output TIMER1_OUT
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);
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//------------------------------------------------------------------------
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// Internal Signals
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reg timer0_enable;
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reg timer1_enable;
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reg timer1_debounce;
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reg timer0_out_int;
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reg timer1_out_int;
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reg [23:0] timer0_counter;
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reg [23:0] timer1_counter;
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reg [23:0] timer0_count_max;
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reg [23:0] timer1_count_max;
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//------------------------------------------------------------------------
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//
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// Combinationals
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//
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//------------------------------------------------------------------------
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assign TIMER0_OUT = (timer0_enable==1'b1 && timer0_out_int==1'b1) ? 1'b1 : 1'b0;
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assign TIMER1_OUT = (timer1_enable==1'b1 && timer1_out_int==1'b1) ? 1'b1 : 1'b0;
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assign DATA_OUT = 8'h5A; // Timer Device ID
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//------------------------------------------------------------------------
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//
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// Timer
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//
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//------------------------------------------------------------------------
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//
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always @(posedge CORE_CLK)
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begin : BIU_CONTROLLER
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if (RST_n==1'b0)
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begin
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timer0_count_max <= 24'h02EA85; // C4 - Middle C 261.63Hz @ 100Mhz core frequency
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timer0_enable <= 1'b1;
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timer0_counter <= 'h0;
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timer0_out_int <= 1'b0;
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timer1_count_max <= 'h0;
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timer1_enable <= 'h0;
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timer1_counter <= 'h0;
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timer1_out_int <= 1'b0;
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timer1_debounce <= 'h0;
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end
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else
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begin
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// Writes to Registers
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if (STROBE_WR==1'b1)
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begin
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case (ADDRESS[3:0]) // synthesis parallel_case
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4'h0 : timer0_count_max[23:16] <= DATA_IN[7:0];
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4'h1 : timer0_count_max[15:8] <= DATA_IN[7:0];
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4'h2 : timer0_count_max[7:0] <= DATA_IN[7:0];
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4'h3 : timer0_enable <= DATA_IN[0];
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4'h4 : timer1_count_max[23:16] <= DATA_IN[7:0];
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4'h5 : timer1_count_max[15:8] <= DATA_IN[7:0];
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4'h6 : timer1_count_max[7:0] <= DATA_IN[7:0];
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4'h7 : timer1_enable <= DATA_IN[0];
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4'h8 : timer1_debounce <= 1'b1;
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default : ;
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endcase
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end
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else
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begin
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timer1_debounce <= 1'b0;
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end
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// Timer0 - Frequency Generator
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if (timer0_enable==1'b0 || timer0_counter==timer0_count_max)
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begin
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timer0_counter <= 'h0;
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timer0_out_int <= ~ timer0_out_int;
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end
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else
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begin
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timer0_counter <= timer0_counter + 1'b1;
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end
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// Timer1 - One-shot Generator
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if (timer1_enable==1'b0 || timer1_counter==timer1_count_max)
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begin
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timer1_counter <= 'h0;
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end
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else
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begin
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timer1_counter <= timer1_counter + 1'b1;
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end
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if (timer1_enable==1'b0 || timer1_debounce==1'b1)
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begin
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timer1_out_int <= 1'b0;
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end
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else if (timer1_counter==timer1_count_max)
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begin
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timer1_out_int <= 1'b1;
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end
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end
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end
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endmodule // timer.v
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