493 lines
17 KiB
Verilog
493 lines
17 KiB
Verilog
//
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//
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// File Name : mcl86_eu_core.v
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// Used on :
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// Author : Ted Fried, MicroCore Labs
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// Creation : 10/8/2015
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// Code Type : Synthesizable
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//
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// Description:
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// ============
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//
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// Execution Unit of the i8088 processor - Microsequencer
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//
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//------------------------------------------------------------------------
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//
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// Modification History:
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// =====================
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//
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// Revision 1.0 10/8/15
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// Initial revision
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//
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//
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//------------------------------------------------------------------------
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//
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// Copyright (c) 2020 Ted Fried
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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//
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//------------------------------------------------------------------------
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module mcl86_eu_core
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(
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input CORE_CLK_INT, // Core Clock
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input RESET_INT, // Pipelined 8088 RESET pin
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input TEST_N_INT, // Pipelined 8088 TEST_n pin
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output [15:0] EU_BIU_COMMAND, // EU to BIU Signals
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output [15:0] EU_BIU_DATAOUT,
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output [15:0] EU_REGISTER_R3,
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output EU_PREFIX_LOCK,
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output EU_FLAG_I,
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input BIU_DONE, // BIU to EU Signals
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input BIU_CLK_COUNTER_ZERO,
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input BIU_NMI_CAUGHT,
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output BIU_NMI_DEBOUNCE,
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input BIU_INTR,
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input [7:0] PFQ_TOP_BYTE,
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input PFQ_EMPTY,
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input[15:0] PFQ_ADDR_OUT,
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input [15:0] BIU_REGISTER_ES,
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input [15:0] BIU_REGISTER_SS,
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input [15:0] BIU_REGISTER_CS,
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input [15:0] BIU_REGISTER_DS,
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input [15:0] BIU_REGISTER_RM,
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input [15:0] BIU_REGISTER_REG,
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input [15:0] BIU_RETURN_DATA
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);
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//------------------------------------------------------------------------
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// Internal Signals
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reg eu_add_carry;
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reg eu_add_carry8;
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reg eu_add_aux_carry;
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reg eu_add_overflow16;
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reg eu_add_overflow8;
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reg eu_stall_pipeline;
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reg eu_flag_t_d;
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reg biu_done_d1;
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reg biu_done_d2;
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reg eu_tr_latched;
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reg biu_done_caught;
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reg eu_biu_req_d1;
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reg intr_enable_delayed;
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wire eu_prefix_rep;
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wire eu_prefix_repnz;
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wire eu_tf_debounce;
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wire eu_prefix_lock ;
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wire eu_biu_req;
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wire eu_parity;
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wire eu_flag_o;
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wire eu_flag_d;
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wire eu_flag_i;
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wire eu_flag_t;
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wire eu_flag_s;
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wire eu_flag_z;
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wire eu_flag_a;
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wire eu_flag_p;
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wire eu_flag_c;
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wire eu_opcode_jump_call;
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wire intr_asserted;
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wire eu_jump_boolean;
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reg [12:0] eu_rom_address;
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reg [51:0] eu_calling_address;
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reg [15:0] eu_register_ax;
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reg [15:0] eu_register_bx;
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reg [15:0] eu_register_cx;
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reg [15:0] eu_register_dx;
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reg [15:0] eu_register_sp;
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reg [15:0] eu_register_bp;
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reg [15:0] eu_register_si;
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reg [15:0] eu_register_di;
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reg [15:0] eu_flags;
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reg [15:0] eu_register_r0;
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reg [15:0] eu_register_r1;
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reg [15:0] eu_register_r2;
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reg [15:0] eu_register_r3;
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reg [15:0] eu_biu_command;
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reg [15:0] eu_biu_dataout;
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reg [15:0] eu_alu_last_result;
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wire [15:0] adder_out;
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wire [16:0] carry;
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wire [2:0] eu_opcode_type;
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wire [3:0] eu_opcode_dst_sel;
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wire [3:0] eu_opcode_op0_sel;
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wire [3:0] eu_opcode_op1_sel;
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wire [15:0] eu_opcode_immediate;
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wire [2:0] eu_opcode_jump_src;
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wire [3:0] eu_opcode_jump_cond;
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wire [15:0] system_signals;
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wire [15:0] eu_alu2;
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wire [15:0] eu_alu3;
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wire [15:0] eu_alu4;
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wire [15:0] eu_alu5;
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wire [15:0] eu_alu6;
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wire [15:0] eu_alu7;
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wire [15:0] eu_alu_out;
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wire [15:0] eu_operand0;
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wire [15:0] eu_operand1;
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wire [31:0] eu_rom_data;
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//------------------------------------------------------------------------
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//
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// EU Microcode RAM. 4Kx32 DPRAM
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//
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//------------------------------------------------------------------------
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eu_rom EU_4Kx32 (
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.clka (CORE_CLK_INT),
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.addra (eu_rom_address[11:0]),
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.douta (eu_rom_data)
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);
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//------------------------------------------------------------------------
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//
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// Combinationals
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//
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//------------------------------------------------------------------------
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assign EU_BIU_COMMAND = eu_biu_command;
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assign EU_BIU_DATAOUT = eu_biu_dataout;
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assign EU_REGISTER_R3 = eu_register_r3;
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assign EU_FLAG_I = intr_enable_delayed;
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assign EU_PREFIX_LOCK = eu_prefix_lock;
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// EU ROM opcode decoder
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assign eu_opcode_type = eu_rom_data[30:28];
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assign eu_opcode_dst_sel = eu_rom_data[27:24];
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assign eu_opcode_op0_sel = eu_rom_data[23:20];
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assign eu_opcode_op1_sel = eu_rom_data[19:16];
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assign eu_opcode_immediate = eu_rom_data[15:0];
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assign eu_opcode_jump_call = eu_rom_data[24];
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assign eu_opcode_jump_src = eu_rom_data[22:20];
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assign eu_opcode_jump_cond = eu_rom_data[19:16];
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assign eu_operand0 = (eu_opcode_op0_sel==4'h0) ? eu_register_ax :
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(eu_opcode_op0_sel==4'h1) ? eu_register_bx :
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(eu_opcode_op0_sel==4'h2) ? eu_register_cx :
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(eu_opcode_op0_sel==4'h3) ? eu_register_dx :
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(eu_opcode_op0_sel==4'h4) ? eu_register_sp :
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(eu_opcode_op0_sel==4'h5) ? eu_register_bp :
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(eu_opcode_op0_sel==4'h6) ? eu_register_si :
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(eu_opcode_op0_sel==4'h7) ? eu_register_di :
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(eu_opcode_op0_sel==4'h8) ? eu_flags :
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(eu_opcode_op0_sel==4'h9) ? eu_register_r0 :
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(eu_opcode_op0_sel==4'hA) ? eu_register_r1 :
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(eu_opcode_op0_sel==4'hB) ? eu_register_r2 :
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(eu_opcode_op0_sel==4'hC) ? eu_register_r3 :
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(eu_opcode_op0_sel==4'hD) ? eu_biu_command :
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(eu_opcode_op0_sel==4'hE) ? system_signals :
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16'h0 ;
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assign eu_operand1 = (eu_opcode_op1_sel==4'h0) ? BIU_REGISTER_ES :
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(eu_opcode_op1_sel==4'h1) ? BIU_REGISTER_SS :
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(eu_opcode_op1_sel==4'h2) ? BIU_REGISTER_CS :
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(eu_opcode_op1_sel==4'h3) ? BIU_REGISTER_DS :
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(eu_opcode_op1_sel==4'h4) ? { 8'h00 , PFQ_TOP_BYTE } :
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(eu_opcode_op1_sel==4'h5) ? BIU_REGISTER_RM :
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(eu_opcode_op1_sel==4'h6) ? BIU_REGISTER_REG :
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(eu_opcode_op1_sel==4'h7) ? BIU_RETURN_DATA :
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(eu_opcode_op1_sel==4'h8) ? PFQ_ADDR_OUT :
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(eu_opcode_op1_sel==4'h9) ? eu_register_r0 :
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(eu_opcode_op1_sel==4'hA) ? eu_register_r1 :
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(eu_opcode_op1_sel==4'hB) ? eu_register_r2 :
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(eu_opcode_op1_sel==4'hC) ? eu_register_r3 :
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(eu_opcode_op1_sel==4'hD) ? eu_alu_last_result :
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(eu_opcode_op1_sel==4'hE) ? system_signals :
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eu_opcode_immediate ;
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// JUMP condition codes
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assign eu_jump_boolean = (eu_opcode_jump_cond==4'h0) ? 1'b1 : // unconditional jump
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(eu_opcode_jump_cond==4'h1 && eu_alu_last_result!=16'h0) ? 1'b1 :
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(eu_opcode_jump_cond==4'h2 && eu_alu_last_result==16'h0) ? 1'b1 :
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1'b0 ;
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// Consolidated system signals
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assign system_signals[13] = eu_add_carry8;
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assign system_signals[12] = BIU_CLK_COUNTER_ZERO;
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assign system_signals[11] = eu_add_overflow16;
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assign system_signals[9] = eu_add_overflow8;
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assign system_signals[8] = eu_tr_latched;
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assign system_signals[7] = ~PFQ_EMPTY;
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assign system_signals[6] = biu_done_caught;
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assign system_signals[5] = TEST_N_INT;
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assign system_signals[4] = eu_add_aux_carry;
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assign system_signals[3] = BIU_NMI_CAUGHT;
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assign system_signals[2] = eu_parity;
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assign system_signals[1] = intr_asserted;
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assign system_signals[0] = eu_add_carry;
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assign eu_prefix_repnz = eu_flags[15];
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assign eu_prefix_rep = eu_flags[14];
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assign eu_prefix_lock = eu_flags[13];
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assign BIU_NMI_DEBOUNCE = eu_flags[12];
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assign eu_flag_o = eu_flags[11];
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assign eu_flag_d = eu_flags[10];
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assign eu_flag_i = eu_flags[9];
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assign eu_flag_t = eu_flags[8];
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assign eu_flag_s = eu_flags[7];
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assign eu_flag_z = eu_flags[6];
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assign eu_tf_debounce = eu_flags[5];
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assign eu_flag_a = eu_flags[4];
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assign eu_nmi_pending = eu_flags[3];
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assign eu_flag_p = eu_flags[2];
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assign eu_flag_temp = eu_flags[1];
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assign eu_flag_c = eu_flags[0];
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// EU ALU Operations
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// ------------------------------------------
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// eu_alu0 = NOP
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// eu_alu1 = JUMP
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assign eu_alu2 = adder_out; // ADD
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assign eu_alu3 = { eu_operand0[7:0] , eu_operand0[15:8] }; // BYTESWAP
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assign eu_alu4 = eu_operand0 & eu_operand1; // AND
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assign eu_alu5 = eu_operand0 | eu_operand1; // OR
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assign eu_alu6 = eu_operand0 ^ eu_operand1; // XOR
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assign eu_alu7 = { 1'b0 , eu_operand0[15:1] }; // SHR
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// Mux the ALU operations
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assign eu_alu_out = (eu_opcode_type==3'h2) ? eu_alu2 :
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(eu_opcode_type==3'h3) ? eu_alu3 :
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(eu_opcode_type==3'h4) ? eu_alu4 :
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(eu_opcode_type==3'h5) ? eu_alu5 :
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(eu_opcode_type==3'h6) ? eu_alu6 :
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(eu_opcode_type==3'h7) ? eu_alu7 :
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20'hEEEEE;
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// Generate 16-bit full adder for the EU
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assign carry[0] = 1'b0;
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genvar i;
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generate
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for (i=0; i < 16; i=i+1)
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begin : GEN_ADDER
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assign adder_out[i] = eu_operand0[i] ^ eu_operand1[i] ^ carry[i];
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assign carry[i+1] = (eu_operand0[i] & eu_operand1[i]) | (eu_operand0[i] & carry[i]) | (eu_operand1[i] & carry[i]);
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end
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endgenerate
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assign eu_parity = ~(eu_alu_last_result[0]^eu_alu_last_result[1]^eu_alu_last_result[2]^eu_alu_last_result[3]^eu_alu_last_result[4]^eu_alu_last_result[5]^eu_alu_last_result[6]^eu_alu_last_result[7]);
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assign eu_biu_req = eu_biu_command[9];
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assign intr_asserted = BIU_INTR & intr_enable_delayed;
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assign new_instruction = (eu_rom_address[12:8]==5'h01) ? 1'b1 : 1'b0;
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//------------------------------------------------------------------------------------------
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//
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// EU Microsequencer
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//
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//------------------------------------------------------------------------------------------
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always @(posedge CORE_CLK_INT)
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begin : EU_MICROSEQUENCER
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if (RESET_INT==1'b1)
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begin
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biu_done_d1 <= 'h0;
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biu_done_d2 <= 'h0;
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eu_biu_req_d1 <= 'h0;
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biu_done_caught <= 'h0;
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eu_flag_t_d <= 'h0;
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eu_tr_latched <= 'h0;
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eu_add_carry <= 'h0;
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eu_add_carry8 <= 'h0;
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eu_add_aux_carry <= 'h0;
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eu_add_overflow16 <= 'h0;
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eu_add_overflow8 <= 'h0;
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eu_alu_last_result <= 'h0;
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eu_register_ax <= 'h0;
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eu_register_bx <= 'h0;
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eu_register_cx <= 'h0;
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eu_register_dx <= 'h0;
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eu_register_sp <= 'h0;
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eu_register_bp <= 'h0;
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eu_register_si <= 'h0;
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eu_register_di <= 'h0;
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eu_flags <= 'h0;
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eu_register_r0 <= 'h0;
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eu_register_r1 <= 'h0;
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eu_register_r2 <= 'h0;
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eu_register_r3 <= 'h0;
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eu_biu_command <= 'h0;
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eu_biu_dataout <= 'h0;
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eu_stall_pipeline <= 'h0;
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eu_rom_address <= 13'h0020;
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eu_calling_address <= 'h0;
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intr_enable_delayed <= 1'b0;
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end
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else
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begin
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// Delay the INTR enable flag until after the next instruction begins.
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// No delay when it is disabled.
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if (eu_flag_i==1'b0)
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begin
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intr_enable_delayed <= 1'b0;
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end
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else
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if (new_instruction==1'b1)
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begin
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intr_enable_delayed <= eu_flag_i;
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end
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// Latch the TF flag on its rising edge.
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eu_flag_t_d <= eu_flag_t;
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if (eu_flag_t_d==1'b0 && eu_flag_t==1'b1)
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begin
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eu_tr_latched <= 1'b1;
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end
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else if (eu_tf_debounce==1'b1)
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begin
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eu_tr_latched <= 1'b0;
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end
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// Latch the done bit from the biu.
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// Debounce it when the request is released.
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biu_done_d1 <= BIU_DONE;
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biu_done_d2 <= biu_done_d1;
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eu_biu_req_d1 <= eu_biu_req;
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if (biu_done_d2==1'b0 && biu_done_d1==1'b1)
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biu_done_caught <= 1'b1;
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else if (eu_biu_req_d1==1'b1 && eu_biu_req==1'b0)
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biu_done_caught <= 1'b0;
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// Generate and store flags for addition
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if (eu_stall_pipeline==1'b0 && eu_opcode_type==3'h2)
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begin
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eu_add_carry <= carry[16];
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eu_add_carry8 <= carry[8];
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eu_add_aux_carry <= carry[4];
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eu_add_overflow16 <= carry[16] ^ carry[15];
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eu_add_overflow8 <= carry[8] ^ carry[7];
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end
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// Register writeback
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if (eu_stall_pipeline==1'b0 && eu_opcode_type!=3'h0 && eu_opcode_type!=3'h1)
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begin
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eu_alu_last_result <= eu_alu_out[15:0];
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case (eu_opcode_dst_sel) // synthesis parallel_case
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4'h0 : eu_register_ax <= eu_alu_out[15:0];
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4'h1 : eu_register_bx <= eu_alu_out[15:0];
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4'h2 : eu_register_cx <= eu_alu_out[15:0];
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4'h3 : eu_register_dx <= eu_alu_out[15:0];
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4'h4 : eu_register_sp <= eu_alu_out[15:0];
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4'h5 : eu_register_bp <= eu_alu_out[15:0];
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4'h6 : eu_register_si <= eu_alu_out[15:0];
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4'h7 : eu_register_di <= eu_alu_out[15:0];
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4'h8 : eu_flags <= eu_alu_out[15:0];
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4'h9 : eu_register_r0 <= eu_alu_out[15:0];
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4'hA : eu_register_r1 <= eu_alu_out[15:0];
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4'hB : eu_register_r2 <= eu_alu_out[15:0];
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4'hC : eu_register_r3 <= eu_alu_out[15:0];
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4'hD : eu_biu_command <= eu_alu_out[15:0];
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//4'hE : ;
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4'hF : eu_biu_dataout <= eu_alu_out[15:0];
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default : ;
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endcase
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end
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// JUMP Opcode
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if (eu_stall_pipeline==1'b0 && eu_opcode_type==3'h1 && eu_jump_boolean==1'b1)
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begin
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eu_stall_pipeline <= 1'b1;
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// For subroutine CALLs, store next opcode address
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if (eu_opcode_jump_call==1'b1)
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begin
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eu_calling_address[51:0] <= {eu_calling_address[38:0] , eu_rom_address[12:0] }; // 4 deep calling addresses
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end
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case (eu_opcode_jump_src) // synthesis parallel_case
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3'h0 : eu_rom_address <= eu_opcode_immediate[12:0];
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3'h1 : eu_rom_address <= { 4'b0 , 1'b1 , PFQ_TOP_BYTE }; // If only used for primary opcode jump, maybe make fixed prepend rather than immediate value prepend?
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3'h2 : eu_rom_address <= { eu_opcode_immediate[4:0], PFQ_TOP_BYTE[7:6] , PFQ_TOP_BYTE[2:0] , 3'b000 }; // Rearranged mod_reg_rm byte - imm,MOD,RM,000
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3'h3 : begin
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eu_rom_address <= eu_calling_address[12:0];
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eu_calling_address[38:0] <= eu_calling_address[51:13];
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end
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3'h4 : eu_rom_address <= { eu_opcode_immediate[7:0], eu_biu_dataout[3:0] , 1'b0 }; // Jump table for EA register fetch decoding. Jump Addresses decoded from biu_dataout.
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3'h5 : eu_rom_address <= { eu_opcode_immediate[6:0], eu_biu_dataout[3:0] , 2'b00 }; // Jump table for EA register writeback decoding. Jump Addresses decoded from biu_dataout.
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3'h6 : eu_rom_address <= { eu_opcode_immediate[12:3], eu_biu_dataout[5:3] }; // Jump table for instructions that share same opcode and decode using the REG field.
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default : ;
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endcase
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end
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else
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begin
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eu_stall_pipeline <= 1'b0; // Debounce the pipeline stall
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eu_rom_address <= eu_rom_address + 1'b1;
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end
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end
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end // EU Microsequencer
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endmodule // eu.v
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