355 lines
11 KiB
Verilog
355 lines
11 KiB
Verilog
//
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//
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// File Name : MCL86jr.v
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// Used on : MCL86jr Board
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// Author : Ted Fried, MicroCore Labs
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// Creation : 10/8/2015
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// Code Type : Synthesizable
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//
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// Description:
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// ============
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//
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// Top level for the MCL86 8088 CPU core running with minimum mode BIU
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//
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//------------------------------------------------------------------------
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//
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// Modification History:
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// =====================
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//
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// Revision 1.0 10/8/15
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// Initial revision
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//
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//
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//------------------------------------------------------------------------
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//
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// Copyright (c) 2020 Ted Fried
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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//
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//------------------------------------------------------------------------
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module MCL86jr
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(
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input CORE_CLK,
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input CLK,
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input RESET,
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input READY,
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input INTR,
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input NMI,
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output A19,
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output A18,
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output A17,
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output A16,
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output A15,
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output A14,
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output A13,
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output A12,
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output A11,
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output A10,
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output A9,
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output A8,
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inout AD7,
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inout AD6,
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inout AD5,
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inout AD4,
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inout AD3,
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inout AD2,
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inout AD1,
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inout AD0,
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output ALE,
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output INTA_n,
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output RD_n,
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output WR_n,
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output IOM,
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output DTR,
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output DEN,
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output SSO_n,
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output [18:0] SRAM_A,
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inout [7:0] SRAM_D,
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output SRAM_CE_n,
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output SRAM_OE_n,
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output SRAM_WE_n,
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output [7:0] LED,
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output BUF1_OE_n,
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output BUF2_OE_n,
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output BUF2_DIR
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);
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//------------------------------------------------------------------------
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// Internal Signals
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reg t_reset_d1='h0;
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reg t_reset_d2='h0;
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reg t_reset_d3='h0;
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reg t_reset_d4='h0;
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reg t_eu_flag_i_d;
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reg t_biu_ad_oe_d1;
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reg t_biu_ad_oe_d2;
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reg t_biu_lock_n_d;
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reg prescaler_d;
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reg led_go_left;
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reg fpga_config_done;
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wire core_clk_int;
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wire t_eu_prefix_lock;
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wire t_eu_flag_i;
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wire t_biu_lock_n;
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wire t_pfq_empty;
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wire t_biu_done;
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wire t_biu_clk_counter_zero;
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wire t_biu_ad_oe;
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wire t_biu_nmi_caught;
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wire t_biu_nmi_debounce;
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wire t_sram_d_oe;
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wire t_biu_intr;
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reg [26:0] prescaler;
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reg [7:0] led_int;
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reg [19:0] trigger_address;
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reg [19:0] t_biu_ad_out_d;
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wire [19:0] t_biu_ad_out;
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wire [7:0] t_biu_ad_in;
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wire [2:0] t_s2_s0_out;
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wire [15:0] t_eu_biu_command;
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wire [15:0] t_eu_biu_dataout;
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wire [15:0] t_eu_register_r3;
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wire [7:0] t_pfq_top_byte;
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wire [15:0] t_pfq_addr_out;
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wire [15:0] t_biu_register_es;
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wire [15:0] t_biu_register_ss;
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wire [15:0] t_biu_register_cs;
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wire [15:0] t_biu_register_ds;
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wire [15:0] t_biu_register_rm;
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wire [15:0] t_biu_register_reg;
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wire [15:0] t_biu_return_data;
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wire [7:0] t_sram_d_out;
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spartan6_pll SPARTAN6PLL
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(
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.CLK_IN1 (CORE_CLK),
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.CLK_OUT1 (core_clk_int)
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);
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//------------------------------------------------------------------------
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//
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// CPU Bus Combinationals
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//
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//------------------------------------------------------------------------
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assign A19 = t_biu_ad_out_d[19];
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assign A18 = t_biu_ad_out_d[18];
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assign A17 = t_biu_ad_out_d[17];
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assign A16 = t_biu_ad_out_d[16];
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assign A15 = t_biu_ad_out_d[15];
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assign A14 = t_biu_ad_out_d[14];
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assign A13 = t_biu_ad_out_d[13];
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assign A12 = t_biu_ad_out_d[12];
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assign A11 = t_biu_ad_out_d[11];
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assign A10 = t_biu_ad_out_d[10];
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assign A9 = t_biu_ad_out_d[9];
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assign A8 = t_biu_ad_out_d[8];
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assign AD7 = (t_biu_ad_oe_d2==1'b1) ? t_biu_ad_out_d[7] : 'hZ;
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assign AD6 = (t_biu_ad_oe_d2==1'b1) ? t_biu_ad_out_d[6] : 'hZ;
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assign AD5 = (t_biu_ad_oe_d2==1'b1) ? t_biu_ad_out_d[5] : 'hZ;
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assign AD4 = (t_biu_ad_oe_d2==1'b1) ? t_biu_ad_out_d[4] : 'hZ;
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assign AD3 = (t_biu_ad_oe_d2==1'b1) ? t_biu_ad_out_d[3] : 'hZ;
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assign AD2 = (t_biu_ad_oe_d2==1'b1) ? t_biu_ad_out_d[2] : 'hZ;
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assign AD1 = (t_biu_ad_oe_d2==1'b1) ? t_biu_ad_out_d[1] : 'hZ;
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assign AD0 = (t_biu_ad_oe_d2==1'b1) ? t_biu_ad_out_d[0] : 'hZ;
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assign t_biu_ad_in[7:0] = { AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0 };
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assign BUF1_OE_n = 1'b0; // Always enabled for now, but fix when HLD/HLDA is added
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assign BUF2_OE_n = 1'b0; // ~ t_biu_ad_oe_d2;
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assign BUF2_DIR = ~ t_biu_ad_oe_d2;
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assign SRAM_CE_n = 1'b0;
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assign SRAM_D = (t_sram_d_oe==1'b1) ? t_sram_d_out : 8'hZ;
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assign LED[7] = ~led_int[7];
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assign LED[6] = ~led_int[6];
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assign LED[5] = ~led_int[5];
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assign LED[4] = ~led_int[4];
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assign LED[3] = ~led_int[3];
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assign LED[2] = ~led_int[2];
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assign LED[1] = ~led_int[1];
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assign LED[0] = ~led_int[0];
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//------------------------------------------------------------------------
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always @(posedge core_clk_int)
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begin : REGISTER_IOS
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t_biu_ad_oe_d1 <= t_biu_ad_oe;
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t_biu_ad_oe_d2 <= t_biu_ad_oe_d1;
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t_biu_ad_out_d <= t_biu_ad_out;
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t_eu_flag_i_d <= t_eu_flag_i;
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t_biu_lock_n_d <= t_biu_lock_n;
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t_reset_d1 <= RESET;
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t_reset_d2 <= t_reset_d1;
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t_reset_d3 <= t_reset_d2;
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// Use either the PCjr board reset or an internal timer for a reset
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if ( (t_reset_d3==1'b1 && t_reset_d2==1'b1) || (fpga_config_done==1'b0) )
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begin
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t_reset_d4 <= 1'b1;
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led_int <= 8'b10000000;
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end
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else
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begin
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t_reset_d4 <= t_reset_d3;
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end
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prescaler <= prescaler + 1'b1;
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prescaler_d <= prescaler[21];
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if (prescaler[26]==1'b1) fpga_config_done <= 1'b1;
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// Blink the sweeping LEDs
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if (prescaler_d==1'b0 && prescaler[21]==1'b1)
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begin
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if (led_go_left==1'b0)
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led_int[7:0] <= {led_int[0] , led_int[7:1] };
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else
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led_int[7:0] <= {led_int[6:0] , led_int[7] };
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if (led_int[6]==1'b1) led_go_left <= 1'b0;
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if (led_int[1]==1'b1) led_go_left <= 1'b1;
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end
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end
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//------------------------------------------------------------------------
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// BIU Core
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//------------------------------------------------------------------------
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biu_min BIU_CORE
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(
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.CORE_CLK_INT (core_clk_int),
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.RESET_INT (t_reset_d4),
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.CLK (CLK),
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.READY_IN (READY),
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.NMI (NMI),
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.INTR (INTR),
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.INTA_n (INTA_n),
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.ALE (ALE),
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.RD_n (RD_n),
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.WR_n (WR_n),
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.SSO_n (SSO_n),
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.IOM (IOM),
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.DTR (DTR),
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.DEN (DEN),
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.AD_OE (t_biu_ad_oe),
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.AD_OUT (t_biu_ad_out),
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.AD_IN (t_biu_ad_in),
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.EU_BIU_COMMAND (t_eu_biu_command),
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.EU_BIU_DATAOUT (t_eu_biu_dataout),
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.EU_REGISTER_R3 (t_eu_register_r3),
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.EU_PREFIX_LOCK (t_eu_prefix_lock),
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.BIU_DONE (t_biu_done),
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.BIU_CLK_COUNTER_ZERO (t_biu_clk_counter_zero),
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.BIU_SEGMENT ( ),
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.BIU_NMI_CAUGHT (t_biu_nmi_caught),
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.BIU_NMI_DEBOUNCE (t_biu_nmi_debounce),
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.BIU_INTR (t_biu_intr),
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.PFQ_TOP_BYTE (t_pfq_top_byte),
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.PFQ_EMPTY (t_pfq_empty),
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.PFQ_ADDR_OUT (t_pfq_addr_out),
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.BIU_REGISTER_ES (t_biu_register_es),
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.BIU_REGISTER_SS (t_biu_register_ss),
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.BIU_REGISTER_CS (t_biu_register_cs),
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.BIU_REGISTER_DS (t_biu_register_ds),
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.BIU_REGISTER_RM (t_biu_register_rm),
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.BIU_REGISTER_REG (t_biu_register_reg),
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.BIU_RETURN_DATA (t_biu_return_data),
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.SRAM_A (SRAM_A),
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.SRAM_D_OE (t_sram_d_oe),
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.SRAM_D_OUT (t_sram_d_out),
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.SRAM_D_IN (SRAM_D),
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.SRAM_OE_n (SRAM_OE_n),
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.SRAM_WE_n (SRAM_WE_n)
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);
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//------------------------------------------------------------------------
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// EU Core
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//------------------------------------------------------------------------
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mcl86_eu_core EU_CORE
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(
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.CORE_CLK_INT (core_clk_int),
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.RESET_INT (t_reset_d4),
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.TEST_N_INT (1'b1),
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.EU_BIU_COMMAND (t_eu_biu_command),
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.EU_BIU_DATAOUT (t_eu_biu_dataout),
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.EU_REGISTER_R3 (t_eu_register_r3),
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.EU_PREFIX_LOCK (t_eu_prefix_lock),
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.EU_FLAG_I (t_eu_flag_i),
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.BIU_DONE (t_biu_done),
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.BIU_CLK_COUNTER_ZERO (t_biu_clk_counter_zero),
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.BIU_NMI_CAUGHT (t_biu_nmi_caught),
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.BIU_NMI_DEBOUNCE (t_biu_nmi_debounce),
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.BIU_INTR (t_biu_intr),
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.PFQ_TOP_BYTE (t_pfq_top_byte),
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.PFQ_EMPTY (t_pfq_empty),
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.PFQ_ADDR_OUT (t_pfq_addr_out),
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.BIU_REGISTER_ES (t_biu_register_es),
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.BIU_REGISTER_SS (t_biu_register_ss),
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.BIU_REGISTER_CS (t_biu_register_cs),
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.BIU_REGISTER_DS (t_biu_register_ds),
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.BIU_REGISTER_RM (t_biu_register_rm),
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.BIU_REGISTER_REG (t_biu_register_reg),
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.BIU_RETURN_DATA (t_biu_return_data)
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);
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endmodule
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//------------------------------------------------------------------------
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