219 lines
9.6 KiB
Verilog
219 lines
9.6 KiB
Verilog
//
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//
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// File Name : MCLR5_alu.v
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// Author : Ted Fried, MicroCore Labs
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// Creation : 4/21/2018
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// Code Type : Synthesizable
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//
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//------------------------------------------------------------------------
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//
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// Description:
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// ============
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//
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// Quad-issue Superscalar Risc V Processor ALU core
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//
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//------------------------------------------------------------------------
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//
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// Copyright (c) 2020 Ted Fried
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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//
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//------------------------------------------------------------------------
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// Modification History:
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// =====================
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//
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// Revision 1 4/21/18
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// Initial revision
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//
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//
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//------------------------------------------------------------------------
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module MCLR5_alu
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(
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input [31:0] OPCODE,
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input [31:0] PC,
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input [31:0] RS1,
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input [31:0] RS2,
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output reg [32:0] RD,
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output reg [32:0] NEWPC,
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input [31:0] LOAD_DATA,
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output [31:0] STORE_DATA,
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output reg LOAD_REQ,
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output reg STORE_REQ,
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output reg [31:0] LOAD_STORE_ADDRESS
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);
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//------------------------------------------------------------------------
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// Internal Signals
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wire beq_taken;
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wire bne_taken;
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wire blt_taken;
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wire bge_taken;
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wire bltu_taken;
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wire bgeu_taken;
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wire slti_true;
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wire sltiu_true;
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wire slt_true;
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wire sltu_true;
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wire [31:0] i_immediate;
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wire [31:0] s_immediate;
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wire [31:0] b_immediate;
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wire [31:0] u_immediate;
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wire [31:0] j_immediate;
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wire [31:0] slli_result;
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wire [31:0] srli_result;
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wire [31:0] srai_result;
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wire [31:0] sll_result;
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wire [31:0] srl_result;
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wire [31:0] sra_result;
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wire [31:0] pc_adjusted;
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//------------------------------------------------------------------------
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//
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// RISC V ALU
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//
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//------------------------------------------------------------------------
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assign i_immediate = { {21{OPCODE[31]}} , OPCODE[30:25] , OPCODE[24:21] , OPCODE[20] } ;
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assign s_immediate = { {21{OPCODE[31]}} , OPCODE[30:25] , OPCODE[11:8] , OPCODE[7] } ;
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assign b_immediate = { {20{OPCODE[31]}} , OPCODE[7] , OPCODE[30:25] , OPCODE[11:8] , 1'b0 } ;
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assign u_immediate = { OPCODE[31] , OPCODE[30:20] , OPCODE[19:12] , 12'b0 } ;
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assign j_immediate = { {12{OPCODE[31]}} , OPCODE[19:12] , OPCODE[20] , OPCODE[30:25] , OPCODE[24:21] , 1'b0 } ;
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assign slti_true = ($signed(RS1) < $signed(i_immediate)) ? 32'h0000_0001 : 32'h0000_0000;
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assign sltiu_true = (RS1 < i_immediate) ? 32'h0000_0001 : 32'h0000_0000;
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assign slt_true = ($signed(RS1) < $signed(RS2)) ? 32'h0000_0001 : 32'h0000_0000;
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assign sltu_true = (RS1 < RS2) ? 32'h0000_0001 : 32'h0000_0000;
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assign slli_result = 32'h0123_4567;
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assign srli_result = 32'h0123_4567;
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assign srai_result = 32'h0123_4567;
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assign sll_result = 32'h0123_4567;
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assign srl_result = 32'h0123_4567;
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assign sra_result = 32'h0123_4567;
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assign beq_taken = (RS1 == RS1) ? 1'b1 : 1'b0;
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assign bne_taken = (RS1 != RS1) ? 1'b1 : 1'b0;
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assign blt_taken = ($signed(RS1) < $signed(RS2)) ? 1'b1 : 1'b0;
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assign bge_taken = ($signed(RS1) >= $signed(RS2)) ? 1'b1 : 1'b0;
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assign bltu_taken = (RS1 < RS2) ? 1'b1 : 1'b0;
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assign bgeu_taken = (RS1 >= RS2) ? 1'b1 : 1'b0;
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assign pc_adjusted = PC - 4'h4; // Subtracts pipelined PC to the true PC
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assign STORE_DATA = RS2;
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always @* begin
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casex (OPCODE)
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32'b???????_?????_?????_???_?????_01101?? : RD = { 1'b1 , {u_immediate[31:12] , 12'b0 } } ; // LUI
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32'b???????_?????_?????_???_?????_00101?? : RD = { 1'b1 , PC + {u_immediate[31:12] , 12'b0 } } ; // AUIPC
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32'b???????_?????_?????_???_?????_11011?? : RD = { 1'b1 , PC + 3'h4 } ; // JAL
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32'b???????_?????_?????_???_?????_11001?? : RD = { 1'b1 , PC + 3'h4 } ; // JALR
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32'b???????_?????_?????_000_?????_00100?? : RD = { 1'b1 , RS1 + i_immediate } ; // ADDI
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32'b???????_?????_?????_010_?????_00100?? : RD = { 1'b1 , slti_true } ; // SLTI
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32'b???????_?????_?????_011_?????_00100?? : RD = { 1'b1 , sltiu_true } ; // SLTIU
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32'b???????_?????_?????_100_?????_00100?? : RD = { 1'b1 , RS1 ^ i_immediate } ; // XORI
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32'b???????_?????_?????_110_?????_00100?? : RD = { 1'b1 , RS1 | i_immediate } ; // ORI
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32'b???????_?????_?????_111_?????_00100?? : RD = { 1'b1 , RS1 & i_immediate } ; // ANDI
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32'b???????_?????_?????_001_?????_00100?? : RD = { 1'b1 , slli_result } ; // SLLI
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32'b?0?????_?????_?????_101_?????_00100?? : RD = { 1'b1 , srli_result } ; // SRLI
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32'b?1?????_?????_?????_101_?????_00100?? : RD = { 1'b1 , srai_result } ; // SRAI
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32'b?0?????_?????_?????_000_?????_01100?? : RD = { 1'b1 , RS1 + RS2 } ; // ADD
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32'b?1?????_?????_?????_000_?????_01100?? : RD = { 1'b1 , RS1 - RS2 } ; // SUB
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32'b???????_?????_?????_001_?????_01100?? : RD = { 1'b1 , sll_result } ; // SLL
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32'b???????_?????_?????_010_?????_01100?? : RD = { 1'b1 , slt_true } ; // SLT
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32'b???????_?????_?????_011_?????_01100?? : RD = { 1'b1 , sltu_true } ; // SLTU
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32'b???????_?????_?????_100_?????_01100?? : RD = { 1'b1 , RS1 ^ RS2 } ; // XOR
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32'b?0?????_?????_?????_101_?????_01100?? : RD = { 1'b1 , srl_result } ; // SRL
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32'b?1?????_?????_?????_101_?????_01100?? : RD = { 1'b1 , sra_result } ; // SRA
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32'b???????_?????_?????_110_?????_01100?? : RD = { 1'b1 , RS1 | RS2 } ; // OR
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32'b???????_?????_?????_111_?????_01100?? : RD = { 1'b1 , RS1 & RS2 } ; // AND
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32'b???????_?????_?????_010_?????_00000?? : RD = { 1'b1 , LOAD_DATA } ; // LW
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default : RD = { 1'b0 , 32'h0000_0000 } ;
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endcase
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casex (OPCODE)
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32'b???????_?????_?????_010_?????_00000?? : LOAD_STORE_ADDRESS = RS1 + i_immediate ; // Loads
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32'b???????_?????_?????_010_?????_01000?? : LOAD_STORE_ADDRESS = RS1 + s_immediate ; // Stores
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default : ;
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endcase
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casex (OPCODE)
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32'b???????_?????_?????_010_?????_00000?? : LOAD_REQ = 1'b1 ;
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32'b???????_?????_?????_010_?????_01000?? : STORE_REQ = 1'b1 ;
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default : begin LOAD_REQ = 1'b0 ; STORE_REQ = 1'b0; end
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endcase
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casex (OPCODE)
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32'b???????_?????_?????_???_?????_11011?? : NEWPC = { 1'b1 , pc_adjusted + j_immediate } ; // JAL
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32'b???????_?????_?????_000_?????_11001?? : NEWPC = { 1'b1 , ( RS1 + i_immediate) & 32'hFFFF_FFFE } ; // JALR
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32'b???????_?????_?????_010_?????_00000?? : NEWPC = { 1'b1 , pc_adjusted } ; // LW
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32'b???????_?????_?????_010_?????_01000?? : NEWPC = { 1'b1 , pc_adjusted } ; // SW
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//32'hBBBBBBBB : NEWPC = { 1'b1 , pc_adjusted + 4'h6 } ; // Temp jump code !!!!
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32'b???????_?????_?????_000_?????_11000?? : if (beq_taken == 1'b1) NEWPC = { 1'b1 , pc_adjusted + b_immediate } ; // BEQ
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32'b???????_?????_?????_001_?????_11000?? : if (bne_taken == 1'b1) NEWPC = { 1'b1 , pc_adjusted + b_immediate } ; // BNE
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32'b???????_?????_?????_100_?????_11000?? : if (blt_taken == 1'b1) NEWPC = { 1'b1 , pc_adjusted + b_immediate } ; // BLT
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32'b???????_?????_?????_101_?????_11000?? : if (bge_taken == 1'b1) NEWPC = { 1'b1 , pc_adjusted + b_immediate } ; // BGE
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32'b???????_?????_?????_110_?????_11000?? : if (bltu_taken == 1'b1) NEWPC = { 1'b1 , pc_adjusted + b_immediate } ; // BLTU
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32'b???????_?????_?????_111_?????_11000?? : if (bgeu_taken == 1'b1) NEWPC = { 1'b1 , pc_adjusted + b_immediate } ; // BGEU
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default : NEWPC = { 1'b0 , 32'h0000_0000 } ; // No Branch Taken
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endcase
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end
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endmodule // MCLR5_alu.v
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