73 lines
3.0 KiB
C
73 lines
3.0 KiB
C
#include STM32_HAL_H
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#include "pendsv.h"
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#include "rng.h"
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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uint32_t SystemCoreClock = 168000000;
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void SystemInit(void)
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{
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// set flash wait states for an increasing HCLK frequency -- reference RM0090 section 3.5.1
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FLASH->ACR = FLASH_ACR_LATENCY_5WS;
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// configure main PLL; assumes HSE is 8 MHz; this should evaluate to 0x27402a04 -- reference RM0090 section 7.3.2
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RCC->PLLCFGR = (RCC_PLLCFGR_RST_VALUE & ~RCC_PLLCFGR_PLLQ & ~RCC_PLLCFGR_PLLSRC & ~RCC_PLLCFGR_PLLP & ~RCC_PLLCFGR_PLLN & ~RCC_PLLCFGR_PLLM)
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| (7 << RCC_PLLCFGR_PLLQ_Pos) // Q = 7
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| RCC_PLLCFGR_PLLSRC_HSE // PLLSRC = HSE
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| (0 << RCC_PLLCFGR_PLLP_Pos) // P = 2 (two bits, 00 means PLLP = 2)
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| (168 << RCC_PLLCFGR_PLLN_Pos) // N = 168
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| (4 << RCC_PLLCFGR_PLLM_Pos); // M = 4
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// enable clock security system, HSE clock, and main PLL
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RCC->CR |= RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_PLLON;
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// wait until PLL and HSE ready
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while((RCC->CR & (RCC_CR_PLLRDY | RCC_CR_HSERDY)) != (RCC_CR_PLLRDY | RCC_CR_HSERDY));
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// APB2=2, APB1=4, AHB=1, system clock = main PLL
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RCC->CFGR = RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
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// wait until PLL is system clock
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while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
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// turn off the HSI as it is now unused (it will be turned on again automatically if a clock security failure occurs)
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RCC->CR &= ~RCC_CR_HSION;
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// init the TRNG peripheral
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rng_init();
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// enable full access to the fpu coprocessor
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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}
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void PendSV_Handler(void) {
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pendsv_isr_handler();
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}
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void SysTick_Handler(void) {
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// Instead of calling HAL_IncTick we do the increment here of the counter.
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// This is purely for efficiency, since SysTick is called 1000 times per
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// second at the highest interrupt priority.
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// Note: we don't need uwTick to be declared volatile here because this is
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// the only place where it can be modified, and the code is more efficient
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// without the volatile specifier.
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extern uint32_t uwTick;
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uwTick += 1;
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// Read the systick control regster. This has the side effect of clearing
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// the COUNTFLAG bit, which makes the logic in sys_tick_get_microseconds
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// work properly.
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SysTick->CTRL;
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// Right now we have the storage and DMA controllers to process during
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// this interrupt and we use custom dispatch handlers. If this needs to
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// be generalised in the future then a dispatch table can be used as
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// follows: ((void(*)(void))(systick_dispatch[uwTick & 0xf]))();
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// if (STORAGE_IDLE_TICK(uwTick)) {
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// NVIC->STIR = FLASH_IRQn;
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// }
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// if (DMA_IDLE_ENABLED() && DMA_IDLE_TICK(uwTick)) {
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// dma_idle_handler(uwTick);
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// }
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}
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