2021-01-20 06:46:46 -08:00
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/**
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*
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* \section COPYRIGHT
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*
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2021-03-19 03:45:56 -07:00
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* Copyright 2013-2021 Software Radio Systems Limited
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2021-01-20 06:46:46 -08:00
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*
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* By using this file, you agree to the terms and conditions set
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* forth in the LICENSE file which can be found at the top level of
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* the distribution.
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*
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*/
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2021-03-19 03:45:56 -07:00
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#include "srsran/phy/phch/ra_dl_nr.h"
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2021-02-03 02:05:18 -08:00
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#include "ra_helper.h"
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2021-03-19 03:45:56 -07:00
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#include "srsran/phy/utils/debug.h"
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2021-01-20 06:46:46 -08:00
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// Validate S and L combination for TypeA time domain resource allocation
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static bool check_time_ra_typeA(uint32_t* S, uint32_t* L)
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{
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// Check values using Table 5.1.2.1-1
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if (*S > 3) {
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2021-02-10 04:46:25 -08:00
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ERROR("S (%d) is out-of-range {0,1,2,3}", *S);
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2021-01-20 06:46:46 -08:00
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return false;
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}
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if (*L < 3 || *L > 14) {
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2021-02-10 04:46:25 -08:00
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ERROR("L (%d) is out-of-range {3,...,14}", *L);
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2021-01-20 06:46:46 -08:00
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return false;
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}
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uint32_t sum = *S + *L;
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if (sum < 3) {
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ERROR("The sum of S (%d) and L (%d) is lower than 3", *S, *L);
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2021-01-20 06:46:46 -08:00
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return false;
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}
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if (sum > 14) {
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2021-02-10 04:46:25 -08:00
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ERROR("The sum of S (%d) and L (%d) is greater than 14", *S, *L);
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2021-01-20 06:46:46 -08:00
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return false;
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}
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return true;
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}
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static bool check_time_ra_typeB(uint32_t* S, uint32_t* L)
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{
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ERROR("Not implemented");
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2021-01-20 06:46:46 -08:00
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return false;
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}
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2021-03-19 03:45:56 -07:00
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bool srsran_ra_dl_nr_time_validate(srsran_sch_grant_nr_t* grant)
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{
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2021-03-19 03:45:56 -07:00
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if (grant->mapping == srsran_sch_mapping_type_A) {
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2021-01-20 06:46:46 -08:00
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return check_time_ra_typeA(&grant->S, &grant->L);
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} else {
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return check_time_ra_typeB(&grant->S, &grant->L);
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}
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}
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2021-03-19 03:45:56 -07:00
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int srsran_ra_dl_nr_time_default_A(uint32_t m, srsran_dmrs_sch_typeA_pos_t dmrs_typeA_pos, srsran_sch_grant_nr_t* grant)
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2021-01-20 06:46:46 -08:00
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{
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if (grant == NULL) {
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2021-03-19 03:45:56 -07:00
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return SRSRAN_ERROR_INVALID_INPUTS;
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2021-01-20 06:46:46 -08:00
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}
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2021-03-29 09:10:43 -07:00
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if (m >= SRSRAN_MAX_NOF_TIME_RA) {
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2021-02-10 04:46:25 -08:00
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ERROR("m (%d) is out-of-range", m);
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2021-03-19 03:45:56 -07:00
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return SRSRAN_ERROR_INVALID_INPUTS;
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2021-01-20 06:46:46 -08:00
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}
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// Select k0
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2021-02-04 09:33:52 -08:00
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grant->k = 0;
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2021-01-20 06:46:46 -08:00
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// Select PDSCH mapping
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2021-03-19 03:45:56 -07:00
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static srsran_sch_mapping_type_t pdsch_mapping_lut[16] = {srsran_sch_mapping_type_A,
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srsran_sch_mapping_type_A,
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srsran_sch_mapping_type_A,
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srsran_sch_mapping_type_A,
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srsran_sch_mapping_type_A,
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srsran_sch_mapping_type_B,
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srsran_sch_mapping_type_B,
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srsran_sch_mapping_type_B,
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srsran_sch_mapping_type_B,
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srsran_sch_mapping_type_B,
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srsran_sch_mapping_type_B,
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srsran_sch_mapping_type_A,
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srsran_sch_mapping_type_A,
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srsran_sch_mapping_type_A,
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srsran_sch_mapping_type_B,
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srsran_sch_mapping_type_B};
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2021-01-20 06:46:46 -08:00
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grant->mapping = pdsch_mapping_lut[m];
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2021-03-29 09:10:43 -07:00
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static uint32_t S_pos2[SRSRAN_MAX_NOF_TIME_RA] = {2, 2, 2, 2, 2, 9, 4, 5, 5, 9, 12, 1, 1, 2, 4, 8};
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static uint32_t L_pos2[SRSRAN_MAX_NOF_TIME_RA] = {12, 10, 9, 7, 5, 4, 4, 7, 2, 2, 2, 13, 6, 4, 7, 4};
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static uint32_t S_pos3[SRSRAN_MAX_NOF_TIME_RA] = {3, 3, 3, 3, 3, 10, 6, 5, 5, 9, 12, 1, 1, 2, 4, 8};
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static uint32_t L_pos3[SRSRAN_MAX_NOF_TIME_RA] = {11, 9, 8, 6, 4, 4, 4, 7, 2, 2, 2, 13, 6, 4, 7, 4};
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// Select start symbol (S) and length (L)
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switch (dmrs_typeA_pos) {
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2021-03-19 03:45:56 -07:00
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case srsran_dmrs_sch_typeA_pos_2:
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2021-01-20 06:46:46 -08:00
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grant->S = S_pos2[m];
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grant->L = L_pos2[m];
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break;
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2021-03-19 03:45:56 -07:00
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case srsran_dmrs_sch_typeA_pos_3:
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2021-01-20 06:46:46 -08:00
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grant->S = S_pos3[m];
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grant->L = L_pos3[m];
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break;
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default:
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2021-02-10 04:46:25 -08:00
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ERROR("Undefined case (%d)", dmrs_typeA_pos);
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2021-03-19 03:45:56 -07:00
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return SRSRAN_ERROR;
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2021-01-20 06:46:46 -08:00
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}
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2021-03-19 03:45:56 -07:00
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return SRSRAN_SUCCESS;
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2021-01-20 06:46:46 -08:00
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}
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2021-03-19 03:45:56 -07:00
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static void ra_dl_nr_time_hl(const srsran_sch_time_ra_t* hl_ra_cfg, srsran_sch_grant_nr_t* grant)
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{
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// Compute S and L from SLIV from higher layers
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2021-08-16 00:08:30 -07:00
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srsran_sliv_to_s_and_l(SRSRAN_NSYMB_PER_SLOT_NR, hl_ra_cfg->sliv, &grant->S, &grant->L);
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2021-01-29 07:43:40 -08:00
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2021-02-04 09:33:52 -08:00
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grant->k = hl_ra_cfg->k;
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2021-01-20 06:46:46 -08:00
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grant->mapping = hl_ra_cfg->mapping_type;
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}
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2021-03-19 03:45:56 -07:00
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int srsran_ra_dl_nr_time(const srsran_sch_hl_cfg_nr_t* cfg,
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const srsran_rnti_type_t rnti_type,
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const srsran_search_space_type_t ss_type,
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const uint32_t coreset_id,
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const uint8_t m,
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srsran_sch_grant_nr_t* grant)
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{
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if (cfg == NULL || grant == NULL) {
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2021-03-19 03:45:56 -07:00
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return SRSRAN_ERROR_INVALID_INPUTS;
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2021-01-20 06:46:46 -08:00
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}
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2021-03-29 09:10:43 -07:00
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if (m >= SRSRAN_MAX_NOF_TIME_RA) {
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2021-02-10 04:46:25 -08:00
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ERROR("m (%d) is out-of-range", m);
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2021-03-19 03:45:56 -07:00
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return SRSRAN_ERROR_INVALID_INPUTS;
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2021-01-20 06:46:46 -08:00
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}
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2021-01-29 07:43:40 -08:00
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// Determine which PDSCH Time domain RA configuration to apply (TS 38.214 Table 5.1.2.1.1-1)
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2021-03-19 03:45:56 -07:00
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if (rnti_type == srsran_rnti_type_si && ss_type == srsran_search_space_type_common_0) {
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2021-01-29 07:43:40 -08:00
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// Row 1
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ERROR("Row not implemented");
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2021-03-19 03:45:56 -07:00
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} else if (rnti_type == srsran_rnti_type_si && ss_type == srsran_search_space_type_common_0A) {
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2021-01-29 07:43:40 -08:00
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// Row 2
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ERROR("Row not implemented");
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2021-03-19 03:45:56 -07:00
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} else if ((rnti_type == srsran_rnti_type_ra || rnti_type == srsran_rnti_type_tc) &&
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ss_type == srsran_search_space_type_common_1) {
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2021-01-29 07:43:40 -08:00
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// Row 3
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2021-02-03 02:05:18 -08:00
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if (cfg->nof_common_time_ra > 0) {
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ra_dl_nr_time_hl(&cfg->common_time_ra[m], grant);
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2021-01-29 07:43:40 -08:00
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} else {
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// Note: Only Default A is supported, which corresponds SS/PBCH block and coreset mux pattern 1
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2021-03-19 03:45:56 -07:00
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srsran_ra_dl_nr_time_default_A(m, cfg->typeA_pos, grant);
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2021-01-29 07:43:40 -08:00
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}
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2021-03-19 03:45:56 -07:00
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} else if (rnti_type == srsran_rnti_type_p && ss_type == srsran_search_space_type_common_2) {
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2021-01-29 07:43:40 -08:00
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// Row 4
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ERROR("Row not implemented");
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2021-03-19 03:45:56 -07:00
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} else if ((rnti_type == srsran_rnti_type_c || rnti_type == srsran_rnti_type_mcs_c ||
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rnti_type == srsran_rnti_type_cs) &&
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SRSRAN_SEARCH_SPACE_IS_COMMON(ss_type) && coreset_id == 0) {
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2021-01-29 07:43:40 -08:00
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// Row 5
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2021-02-03 02:05:18 -08:00
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if (cfg->nof_common_time_ra > 0) {
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ra_dl_nr_time_hl(&cfg->common_time_ra[m], grant);
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2021-01-29 07:43:40 -08:00
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} else {
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2021-03-19 03:45:56 -07:00
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srsran_ra_dl_nr_time_default_A(m, cfg->typeA_pos, grant);
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2021-01-29 07:43:40 -08:00
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}
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2021-03-19 03:45:56 -07:00
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} else if ((rnti_type == srsran_rnti_type_c || rnti_type == srsran_rnti_type_mcs_c ||
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rnti_type == srsran_rnti_type_cs) &&
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((SRSRAN_SEARCH_SPACE_IS_COMMON(ss_type) && coreset_id != 0) || ss_type == srsran_search_space_type_ue)) {
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2021-01-29 07:43:40 -08:00
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// Row 6
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2021-02-03 02:05:18 -08:00
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if (cfg->nof_dedicated_time_ra > 0) {
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ra_dl_nr_time_hl(&cfg->dedicated_time_ra[m], grant);
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} else if (cfg->nof_common_time_ra > 0) {
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ra_dl_nr_time_hl(&cfg->common_time_ra[m], grant);
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2021-01-29 07:43:40 -08:00
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} else {
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2021-03-19 03:45:56 -07:00
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srsran_ra_dl_nr_time_default_A(m, cfg->typeA_pos, grant);
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2021-01-29 07:43:40 -08:00
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}
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2021-01-20 06:46:46 -08:00
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} else {
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2021-03-29 09:10:43 -07:00
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ERROR("Unhandled case %s, ss_type=%d", srsran_rnti_type_str(rnti_type), ss_type);
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2021-01-20 06:46:46 -08:00
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}
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// Validate S and L parameters
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2021-03-19 03:45:56 -07:00
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if (!srsran_ra_dl_nr_time_validate(grant)) {
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2021-02-10 04:46:25 -08:00
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ERROR("Invalid Time RA S=%d; L=%d; m=%d", grant->S, grant->L, m);
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2021-03-19 03:45:56 -07:00
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return SRSRAN_ERROR;
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2021-01-20 06:46:46 -08:00
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}
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2021-03-19 03:45:56 -07:00
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return SRSRAN_SUCCESS;
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2021-01-20 06:46:46 -08:00
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}
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2021-04-22 09:22:56 -07:00
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int srsran_ra_dl_nr_nof_front_load_symbols(const srsran_sch_hl_cfg_nr_t* cfg,
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const srsran_dci_dl_nr_t* dci,
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srsran_dmrs_sch_len_t* dmrs_duration)
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2021-01-20 06:46:46 -08:00
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{
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2021-04-22 09:22:56 -07:00
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// Table 7.3.1.2.2-1: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=1
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// Table 7.3.1.2.2-3: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=1
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if (cfg->dmrs_max_length == srsran_dmrs_sch_len_1) {
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*dmrs_duration = srsran_dmrs_sch_len_1;
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return SRSRAN_SUCCESS;
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2021-01-20 06:46:46 -08:00
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}
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2021-04-22 09:22:56 -07:00
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// Table 7.3.1.2.2-2: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=2
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if (cfg->dmrs_type == srsran_dmrs_sch_type_1 && cfg->dmrs_max_length == srsran_dmrs_sch_len_2) {
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// Only one codeword supported!
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if (dci->ports < 12) {
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*dmrs_duration = srsran_dmrs_sch_len_1;
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return SRSRAN_SUCCESS;
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}
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if (dci->ports < 31) {
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*dmrs_duration = srsran_dmrs_sch_len_2;
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return SRSRAN_SUCCESS;
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}
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ERROR("reserved value for ports (%d)", dci->ports);
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return SRSRAN_ERROR;
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2021-01-20 06:46:46 -08:00
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}
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2021-04-22 09:22:56 -07:00
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// Table 7.3.1.2.2-4: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=2
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if (cfg->dmrs_type == srsran_dmrs_sch_type_2 && cfg->dmrs_max_length == srsran_dmrs_sch_len_2) {
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// Only one codeword supported!
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if (dci->ports < 3) {
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*dmrs_duration = srsran_dmrs_sch_len_1;
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return SRSRAN_SUCCESS;
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}
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2021-01-20 06:46:46 -08:00
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2021-04-22 09:22:56 -07:00
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if (dci->ports < 24) {
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*dmrs_duration = srsran_dmrs_sch_len_2;
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return SRSRAN_SUCCESS;
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}
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ERROR("reserved value for ports (%d)", dci->ports);
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return SRSRAN_ERROR;
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2021-01-20 06:46:46 -08:00
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}
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2021-04-22 09:22:56 -07:00
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ERROR("Unhandled case");
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return SRSRAN_ERROR;
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2021-01-20 06:46:46 -08:00
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}
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2021-04-22 09:22:56 -07:00
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int srsran_ra_dl_nr_nof_dmrs_cdm_groups_without_data(const srsran_sch_hl_cfg_nr_t* cfg,
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const srsran_dci_dl_nr_t* dci,
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uint32_t L)
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2021-01-20 06:46:46 -08:00
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{
|
2021-04-22 09:22:56 -07:00
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// According to TS 38.214 5.1.6.2 DM-RS reception procedure
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switch (dci->ctx.format) {
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case srsran_dci_format_nr_1_0:
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// When receiving PDSCH scheduled by DCI format 1_0, the UE shall assume the number of DM-RS CDM groups
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// without data is 1 which corresponds to CDM group 0 for the case of PDSCH with allocation duration of 2 symbols,
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// and the UE shall assume that the number of DM-RS CDM groups without data is 2 which corresponds to CDM group
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// {0,1} for all other cases.
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if (L == 2) {
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return 1;
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} else {
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return 2;
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}
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return SRSRAN_SUCCESS;
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2021-04-23 07:47:29 -07:00
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case srsran_dci_format_nr_1_1:
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2021-04-22 09:22:56 -07:00
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// When receiving PDSCH scheduled by DCI format 1_1, the UE shall assume that the CDM groups indicated in the
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// configured index from Tables 7.3.1.2.2-1, 7.3.1.2.2-2, 7.3.1.2.2-3, 7.3.1.2.2-4 of [5, TS. 38.212] contain
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// potential co- scheduled downlink DM-RS and are not used for data transmission, where "1", "2" and "3" for the
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// number of DM-RS CDM group(s) in Tables 7.3.1.2.2-1, 7.3.1.2.2-2, 7.3.1.2.2-3, 7.3.1.2.2-4 of [5, TS. 38.212]
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// correspond to CDM group 0, {0,1}, {0,1,2}, respectively.
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// Table 7.3.1.2.2-1: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=1
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if (cfg->dmrs_type == srsran_dmrs_sch_type_1 && cfg->dmrs_max_length == srsran_dmrs_sch_len_1) {
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if (dci->ports < 3) {
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return 1;
|
2021-01-20 06:46:46 -08:00
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}
|
2021-04-22 09:22:56 -07:00
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if (dci->ports < 12) {
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return 2;
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}
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ERROR("Invalid ports=%d;", dci->ports);
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return SRSRAN_ERROR;
|
2021-01-20 06:46:46 -08:00
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|
|
}
|
2021-04-22 09:22:56 -07:00
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ERROR("Unhandled case (%d, %d)", cfg->dmrs_type, cfg->dmrs_max_length);
|
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return SRSRAN_ERROR;
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|
default:
|
2021-06-28 06:18:13 -07:00
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|
ERROR("Invalid DL DCI format %s", srsran_dci_format_nr_string(dci->ctx.format));
|
2021-01-20 06:46:46 -08:00
|
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|
}
|
2021-04-22 09:22:56 -07:00
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|
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|
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return SRSRAN_ERROR;
|
2021-01-20 06:46:46 -08:00
|
|
|
}
|
|
|
|
|
2021-03-19 03:45:56 -07:00
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|
|
int srsran_ra_dl_nr_freq(const srsran_carrier_nr_t* carrier,
|
|
|
|
const srsran_sch_hl_cfg_nr_t* cfg,
|
|
|
|
const srsran_dci_dl_nr_t* dci_dl,
|
|
|
|
srsran_sch_grant_nr_t* grant)
|
2021-01-20 06:46:46 -08:00
|
|
|
{
|
2021-04-23 07:47:29 -07:00
|
|
|
if (carrier == NULL || cfg == NULL || grant == NULL || dci_dl == NULL) {
|
2021-03-19 03:45:56 -07:00
|
|
|
return SRSRAN_ERROR_INVALID_INPUTS;
|
2021-01-20 06:46:46 -08:00
|
|
|
}
|
|
|
|
|
2021-08-19 07:04:29 -07:00
|
|
|
// For a PDSCH scheduled with a DCI format 1_0 in any type of PDCCH common search space, regardless of which
|
|
|
|
// bandwidth part is the active bandwidth part, RB numbering starts from the lowest RB of the CORESET in which the
|
|
|
|
// DCI was received; otherwise RB numbering starts from the lowest RB in the determined downlink bandwidth part.
|
|
|
|
uint32_t start_rb = 0;
|
|
|
|
if (dci_dl->ctx.format == srsran_dci_format_nr_1_0 && SRSRAN_SEARCH_SPACE_IS_COMMON(dci_dl->ctx.ss_type)) {
|
|
|
|
start_rb = dci_dl->ctx.coreset_start_rb;
|
|
|
|
}
|
|
|
|
|
|
|
|
// when DCI format 1_0 is decoded in any common search space in which case the size of CORESET 0 shall be used if
|
|
|
|
// CORESET 0 is configured for the cell and the size of initial DL bandwidth part shall be used if CORESET 0 is not
|
|
|
|
// configured for the cell.
|
|
|
|
uint32_t type1_bwp_sz = carrier->nof_prb;
|
|
|
|
if (SRSRAN_SEARCH_SPACE_IS_COMMON(dci_dl->ctx.ss_type) && dci_dl->coreset0_bw != 0) {
|
|
|
|
type1_bwp_sz = dci_dl->coreset0_bw;
|
|
|
|
}
|
|
|
|
|
2021-04-23 07:47:29 -07:00
|
|
|
// The UE shall assume that when the scheduling grant is received with DCI format 1_0 , then downlink resource
|
|
|
|
// allocation type 1 is used.
|
2021-03-29 09:10:43 -07:00
|
|
|
if (dci_dl->ctx.format == srsran_dci_format_nr_1_0) {
|
2021-08-19 07:04:29 -07:00
|
|
|
return ra_helper_freq_type1(type1_bwp_sz, start_rb, dci_dl->freq_domain_assigment, grant);
|
2021-01-20 06:46:46 -08:00
|
|
|
}
|
|
|
|
|
2021-04-23 07:47:29 -07:00
|
|
|
// If the scheduling DCI is configured to indicate the downlink resource allocation type as part of the Frequency
|
|
|
|
// domain resource assignment field by setting a higher layer parameter resourceAllocation in pdsch-Config to
|
|
|
|
// 'dynamicswitch', the UE shall use downlink resource allocation type 0 or type 1 as defined by this DCI field.
|
|
|
|
if (cfg->alloc == srsran_resource_alloc_dynamic) {
|
|
|
|
ERROR("Unsupported dynamic resource allocation");
|
|
|
|
return SRSRAN_ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise the UE shall use the downlink frequency resource allocation type as defined by the higher layer parameter
|
|
|
|
// resourceAllocation.
|
|
|
|
if (cfg->alloc == srsran_resource_alloc_type1) {
|
2021-08-19 07:04:29 -07:00
|
|
|
return ra_helper_freq_type1(type1_bwp_sz, start_rb, dci_dl->freq_domain_assigment, grant);
|
2021-04-23 07:47:29 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
if (cfg->alloc == srsran_resource_alloc_type0) {
|
|
|
|
return ra_helper_freq_type0(carrier, cfg, dci_dl->freq_domain_assigment, grant);
|
|
|
|
}
|
|
|
|
|
|
|
|
ERROR("Unhandled case");
|
2021-03-19 03:45:56 -07:00
|
|
|
return SRSRAN_ERROR;
|
2021-01-20 06:46:46 -08:00
|
|
|
}
|
2021-06-21 09:09:28 -07:00
|
|
|
|
|
|
|
uint32_t srsran_ra_nr_type1_riv(uint32_t N_prb, uint32_t start_rb, uint32_t length_rb)
|
|
|
|
{
|
2021-08-16 00:08:30 -07:00
|
|
|
return srsran_sliv_from_s_and_l(N_prb, start_rb, length_rb);
|
2021-08-25 09:13:26 -07:00
|
|
|
}
|
|
|
|
|