2020-11-26 01:25:22 -08:00
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/**
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2021-03-28 14:12:42 -07:00
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* Copyright 2013-2021 Software Radio Systems Limited
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2015-01-29 16:15:09 -08:00
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*
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2021-04-22 01:59:40 -07:00
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* This file is part of srsRAN.
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2015-01-29 16:15:09 -08:00
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*
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2021-04-22 01:59:40 -07:00
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* srsRAN is free software: you can redistribute it and/or modify
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2021-03-28 14:12:42 -07:00
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* it under the terms of the GNU Affero General Public License as
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* published by the Free Software Foundation, either version 3 of
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* the License, or (at your option) any later version.
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*
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2021-04-22 01:59:40 -07:00
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* srsRAN is distributed in the hope that it will be useful,
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2021-03-28 14:12:42 -07:00
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Affero General Public License for more details.
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2015-01-29 16:15:09 -08:00
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*
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2021-03-28 14:12:42 -07:00
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* A copy of the GNU Affero General Public License can be found in
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* the LICENSE file in the top-level directory of this distribution
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* and at http://www.gnu.org/licenses/.
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2015-01-29 16:15:09 -08:00
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*
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*/
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2019-12-16 07:04:22 -08:00
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#include <assert.h>
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#include <math.h>
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#include <stdbool.h>
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2015-01-29 16:15:09 -08:00
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#include <stdint.h>
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#include <stdio.h>
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2019-12-16 07:04:22 -08:00
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#include <stdlib.h>
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2015-01-29 16:15:09 -08:00
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#include <string.h>
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#include <strings.h>
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2021-03-19 03:45:56 -07:00
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#include "srsran/phy/common/phy_common.h"
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#include "srsran/phy/fec/block/block.h"
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#include "srsran/phy/fec/convolutional/convcoder.h"
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#include "srsran/phy/fec/convolutional/rm_conv.h"
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#include "srsran/phy/fec/crc.h"
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#include "srsran/phy/phch/uci.h"
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#include "srsran/phy/utils/bit.h"
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#include "srsran/phy/utils/debug.h"
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#include "srsran/phy/utils/vector.h"
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2016-04-27 08:23:36 -07:00
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2021-01-08 01:47:14 -08:00
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/* Table 5.2.3.3-1: Basis sequences for (20, A) code */
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2019-12-16 07:04:22 -08:00
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static uint8_t M_basis_seq_pucch[20][13] = {
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{1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0}, {1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0},
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{1, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1}, {1, 0, 1, 1, 0, 0, 0, 0, 1, 0, 1, 1, 1},
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{1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1}, {1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1},
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{1, 0, 1, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1}, {1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1},
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{1, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1}, {1, 0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1},
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{1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 1, 1}, {1, 1, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 1},
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{1, 0, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1}, {1, 1, 0, 1, 0, 1, 0, 1, 0, 1, 1, 1, 1},
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{1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1}, {1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1},
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{1, 1, 1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1}, {1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1},
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{1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0}, {1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0},
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};
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2021-03-19 03:45:56 -07:00
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void srsran_uci_cqi_pucch_init(srsran_uci_cqi_pucch_t* q)
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2019-12-16 07:04:22 -08:00
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{
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2017-10-16 08:33:30 -07:00
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uint8_t word[16];
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2021-03-19 03:45:56 -07:00
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uint32_t nwords = 1 << SRSRAN_UCI_MAX_CQI_LEN_PUCCH;
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q->cqi_table = srsran_vec_malloc(nwords * sizeof(int8_t*));
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q->cqi_table_s = srsran_vec_malloc(nwords * sizeof(int16_t*));
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2017-10-16 08:33:30 -07:00
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for (uint32_t w = 0; w < nwords; w++) {
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2021-03-19 03:45:56 -07:00
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q->cqi_table[w] = srsran_vec_malloc(SRSRAN_UCI_CQI_CODED_PUCCH_B * sizeof(int8_t));
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q->cqi_table_s[w] = srsran_vec_malloc(SRSRAN_UCI_CQI_CODED_PUCCH_B * sizeof(int16_t));
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2019-12-16 07:04:22 -08:00
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uint8_t* ptr = word;
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2021-03-19 03:45:56 -07:00
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srsran_bit_unpack(w, &ptr, SRSRAN_UCI_MAX_CQI_LEN_PUCCH);
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srsran_uci_encode_cqi_pucch(word, SRSRAN_UCI_MAX_CQI_LEN_PUCCH, q->cqi_table[w]);
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for (int j = 0; j < SRSRAN_UCI_CQI_CODED_PUCCH_B; j++) {
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2017-10-16 08:33:30 -07:00
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q->cqi_table_s[w][j] = (int16_t)(2 * q->cqi_table[w][j] - 1);
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2017-03-28 00:13:24 -07:00
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}
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}
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}
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2021-03-19 03:45:56 -07:00
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void srsran_uci_cqi_pucch_free(srsran_uci_cqi_pucch_t* q)
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2019-12-16 07:04:22 -08:00
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{
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2021-03-19 03:45:56 -07:00
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uint32_t nwords = 1 << SRSRAN_UCI_MAX_CQI_LEN_PUCCH;
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2019-12-16 07:04:22 -08:00
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for (uint32_t w = 0; w < nwords; w++) {
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2017-09-05 01:54:36 -07:00
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if (q->cqi_table[w]) {
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free(q->cqi_table[w]);
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}
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if (q->cqi_table_s[w]) {
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free(q->cqi_table_s[w]);
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}
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}
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2017-10-16 08:33:30 -07:00
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free(q->cqi_table);
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free(q->cqi_table_s);
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2017-09-05 01:54:36 -07:00
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}
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2019-12-16 07:04:22 -08:00
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/* Encode UCI CQI/PMI as described in 5.2.3.3 of 36.212
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2017-03-28 00:13:24 -07:00
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*/
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2021-03-19 03:45:56 -07:00
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int srsran_uci_encode_cqi_pucch(uint8_t* cqi_data, uint32_t cqi_len, uint8_t b_bits[SRSRAN_UCI_CQI_CODED_PUCCH_B])
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2017-03-28 00:13:24 -07:00
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{
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2021-03-19 03:45:56 -07:00
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if (cqi_len <= SRSRAN_UCI_MAX_CQI_LEN_PUCCH) {
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for (uint32_t i = 0; i < SRSRAN_UCI_CQI_CODED_PUCCH_B; i++) {
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2019-12-16 07:04:22 -08:00
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uint64_t x = 0;
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for (uint32_t n = 0; n < cqi_len; n++) {
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x += cqi_data[n] * M_basis_seq_pucch[i][n];
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2017-03-28 00:13:24 -07:00
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}
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2019-12-16 07:04:22 -08:00
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b_bits[i] = (uint8_t)(x % 2);
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2017-03-28 00:13:24 -07:00
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}
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2021-03-19 03:45:56 -07:00
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return SRSRAN_SUCCESS;
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2017-03-28 00:13:24 -07:00
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} else {
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2021-03-19 03:45:56 -07:00
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return SRSRAN_ERROR_INVALID_INPUTS;
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2017-03-28 00:13:24 -07:00
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}
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}
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2021-03-19 03:45:56 -07:00
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int srsran_uci_encode_cqi_pucch_from_table(srsran_uci_cqi_pucch_t* q,
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2019-12-16 07:04:22 -08:00
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uint8_t* cqi_data,
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uint32_t cqi_len,
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2021-03-19 03:45:56 -07:00
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uint8_t b_bits[SRSRAN_UCI_CQI_CODED_PUCCH_B])
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2017-10-16 08:33:30 -07:00
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{
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2021-03-19 03:45:56 -07:00
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if (cqi_len <= SRSRAN_UCI_MAX_CQI_LEN_PUCCH) {
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bzero(&cqi_data[cqi_len], SRSRAN_UCI_MAX_CQI_LEN_PUCCH - cqi_len);
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2019-12-16 07:04:22 -08:00
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uint8_t* ptr = cqi_data;
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2021-03-19 03:45:56 -07:00
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uint32_t packed = srsran_bit_pack(&ptr, SRSRAN_UCI_MAX_CQI_LEN_PUCCH);
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memcpy(b_bits, q->cqi_table[packed], SRSRAN_UCI_CQI_CODED_PUCCH_B);
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2017-10-16 08:33:30 -07:00
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2021-03-19 03:45:56 -07:00
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return SRSRAN_SUCCESS;
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2017-10-16 08:33:30 -07:00
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} else {
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2021-03-19 03:45:56 -07:00
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return SRSRAN_ERROR_INVALID_INPUTS;
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2017-10-16 08:33:30 -07:00
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}
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}
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2019-12-16 07:04:22 -08:00
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/* Decode UCI CQI/PMI over PUCCH
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2017-03-28 00:13:24 -07:00
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*/
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2021-03-19 03:45:56 -07:00
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int16_t srsran_uci_decode_cqi_pucch(srsran_uci_cqi_pucch_t* q,
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int16_t b_bits[SRSRAN_CQI_MAX_BITS],
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2019-04-23 01:53:11 -07:00
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uint8_t* cqi_data,
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uint32_t cqi_len)
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2017-03-28 00:13:24 -07:00
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{
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2021-05-25 02:56:30 -07:00
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if (q != NULL && cqi_len < SRSRAN_UCI_MAX_CQI_LEN_PUCCH && b_bits != NULL && cqi_data != NULL) {
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2019-12-16 07:04:22 -08:00
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uint32_t max_w = 0;
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int32_t max_corr = INT32_MIN;
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2021-03-19 03:45:56 -07:00
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uint32_t nwords = 1 << SRSRAN_UCI_MAX_CQI_LEN_PUCCH;
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for (uint32_t w = 0; w < nwords; w += 1 << (SRSRAN_UCI_MAX_CQI_LEN_PUCCH - cqi_len)) {
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2017-03-28 00:13:24 -07:00
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// Calculate correlation with pregenerated word and select maximum
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2021-03-19 03:45:56 -07:00
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int32_t corr = srsran_vec_dot_prod_sss(q->cqi_table_s[w], b_bits, SRSRAN_UCI_CQI_CODED_PUCCH_B);
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2017-03-28 00:13:24 -07:00
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if (corr > max_corr) {
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2019-04-23 01:53:11 -07:00
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max_corr = corr;
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max_w = w;
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2017-03-28 00:13:24 -07:00
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}
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}
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// Convert word to bits again
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2019-12-16 07:04:22 -08:00
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uint8_t* ptr = cqi_data;
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2021-03-19 03:45:56 -07:00
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srsran_bit_unpack(max_w, &ptr, SRSRAN_UCI_MAX_CQI_LEN_PUCCH);
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2019-12-16 07:04:22 -08:00
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2021-02-10 04:46:25 -08:00
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INFO("Decoded CQI: w=%d, corr=%d", max_w, max_corr);
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2017-03-28 00:13:24 -07:00
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return max_corr;
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} else {
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2021-03-19 03:45:56 -07:00
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return SRSRAN_ERROR_INVALID_INPUTS;
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2019-04-23 01:53:11 -07:00
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}
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2017-03-28 00:13:24 -07:00
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}
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2016-04-27 08:23:36 -07:00
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2021-03-19 03:45:56 -07:00
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int srsran_uci_cqi_init(srsran_uci_cqi_pusch_t* q)
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2019-12-16 07:04:22 -08:00
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{
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2021-03-19 03:45:56 -07:00
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if (srsran_crc_init(&q->crc, SRSRAN_LTE_CRC8, 8)) {
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return SRSRAN_ERROR;
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2015-02-09 02:32:47 -08:00
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}
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2019-12-16 07:04:22 -08:00
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int poly[3] = {0x6D, 0x4F, 0x57};
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2021-03-19 03:45:56 -07:00
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if (srsran_viterbi_init(&q->viterbi, SRSRAN_VITERBI_37, poly, SRSRAN_UCI_MAX_CQI_LEN_PUSCH, true)) {
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return SRSRAN_ERROR;
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2016-04-27 08:23:36 -07:00
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}
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2019-12-16 07:04:22 -08:00
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2021-03-19 03:45:56 -07:00
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return SRSRAN_SUCCESS;
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2015-02-09 02:32:47 -08:00
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}
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2021-03-19 03:45:56 -07:00
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void srsran_uci_cqi_free(srsran_uci_cqi_pusch_t* q)
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2016-04-27 08:23:36 -07:00
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{
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2021-03-19 03:45:56 -07:00
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srsran_viterbi_free(&q->viterbi);
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2015-02-09 02:32:47 -08:00
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}
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2021-03-19 03:45:56 -07:00
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static uint32_t Q_prime_cqi(srsran_pusch_cfg_t* cfg, uint32_t O, float beta, uint32_t Q_prime_ri)
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2015-04-27 09:14:28 -07:00
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{
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2019-04-23 01:53:11 -07:00
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uint32_t K = cfg->K_segm;
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2015-02-10 07:49:11 -08:00
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uint32_t Q_prime = 0;
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2019-04-23 01:53:11 -07:00
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uint32_t L = (O < 11) ? 0 : 8;
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2019-12-16 07:04:22 -08:00
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uint32_t x = 999999;
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2019-04-23 01:53:11 -07:00
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2015-02-10 07:49:11 -08:00
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if (K > 0) {
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2021-03-19 03:45:56 -07:00
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x = (uint32_t)ceilf((float)(O + L) * cfg->grant.L_prb * SRSRAN_NRE * cfg->grant.nof_symb * beta / K);
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2015-02-10 07:49:11 -08:00
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}
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2019-04-23 01:53:11 -07:00
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2021-03-19 03:45:56 -07:00
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Q_prime = SRSRAN_MIN(x, cfg->grant.L_prb * SRSRAN_NRE * cfg->grant.nof_symb - Q_prime_ri);
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2015-02-09 02:32:47 -08:00
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2019-12-16 07:04:22 -08:00
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return Q_prime;
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2015-02-09 02:32:47 -08:00
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}
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2021-03-19 03:45:56 -07:00
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uint32_t srsran_qprime_cqi_ext(uint32_t L_prb, uint32_t nof_symbols, uint32_t tbs, float beta)
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2020-08-25 13:30:35 -07:00
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{
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2021-03-19 03:45:56 -07:00
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srsran_pusch_cfg_t cfg = {};
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2020-08-25 13:30:35 -07:00
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cfg.grant.L_prb = L_prb;
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cfg.grant.nof_symb = nof_symbols;
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cfg.K_segm = tbs;
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// O is the number of CQI + CRC len (8). See 5.2.2.6
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2021-03-19 03:45:56 -07:00
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return Q_prime_cqi(&cfg, SRSRAN_UCI_CQI_CODED_PUCCH_B + 8, beta, 0);
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2020-08-25 13:30:35 -07:00
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}
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2015-02-09 02:32:47 -08:00
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/* Encode UCI CQI/PMI for payloads equal or lower to 11 bits (Sec 5.2.2.6.4)
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*/
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2021-03-19 03:45:56 -07:00
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int encode_cqi_short(srsran_uci_cqi_pusch_t* q, uint8_t* data, uint32_t nof_bits, uint8_t* q_bits, uint32_t Q)
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2015-01-29 16:15:09 -08:00
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{
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2021-03-19 03:45:56 -07:00
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if (nof_bits <= SRSRAN_FEC_BLOCK_MAX_NOF_BITS && nof_bits > 0 && q != NULL && data != NULL && q_bits != NULL) {
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srsran_block_encode(data, nof_bits, q_bits, Q);
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return SRSRAN_SUCCESS;
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2015-02-09 02:32:47 -08:00
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}
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2021-03-19 03:45:56 -07:00
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return SRSRAN_ERROR_INVALID_INPUTS;
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2015-01-29 16:15:09 -08:00
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}
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2016-04-27 08:23:36 -07:00
|
|
|
// For decoding the block-encoded CQI we use ML decoding
|
2021-03-19 03:45:56 -07:00
|
|
|
int decode_cqi_short(srsran_uci_cqi_pusch_t* q, int16_t* q_bits, uint32_t Q, uint8_t* data, uint32_t nof_bits)
|
2016-04-27 08:23:36 -07:00
|
|
|
{
|
2021-03-19 03:45:56 -07:00
|
|
|
if (nof_bits <= SRSRAN_FEC_BLOCK_MAX_NOF_BITS && nof_bits > 0 && q != NULL && data != NULL && q_bits != NULL) {
|
|
|
|
int32_t max_corr = srsran_block_decode_i16(q_bits, Q, data, nof_bits);
|
2021-02-10 04:46:25 -08:00
|
|
|
INFO("Decoded CQI: corr=%d", max_corr);
|
2021-03-19 03:45:56 -07:00
|
|
|
return SRSRAN_SUCCESS;
|
2016-04-27 08:23:36 -07:00
|
|
|
} else {
|
2021-03-19 03:45:56 -07:00
|
|
|
return SRSRAN_ERROR_INVALID_INPUTS;
|
2019-12-16 07:04:22 -08:00
|
|
|
}
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
|
|
|
|
2015-02-09 02:32:47 -08:00
|
|
|
/* Encode UCI CQI/PMI for payloads greater than 11 bits (go through CRC, conv coder and rate match)
|
|
|
|
*/
|
2021-03-19 03:45:56 -07:00
|
|
|
int encode_cqi_long(srsran_uci_cqi_pusch_t* q, uint8_t* data, uint32_t nof_bits, uint8_t* q_bits, uint32_t Q)
|
2015-02-09 02:32:47 -08:00
|
|
|
{
|
2021-03-19 03:45:56 -07:00
|
|
|
srsran_convcoder_t encoder;
|
2015-02-09 02:32:47 -08:00
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
if (nof_bits + 8 < SRSRAN_UCI_MAX_CQI_LEN_PUSCH && q != NULL && data != NULL && q_bits != NULL) {
|
2019-12-16 07:04:22 -08:00
|
|
|
int poly[3] = {0x6D, 0x4F, 0x57};
|
|
|
|
encoder.K = 7;
|
|
|
|
encoder.R = 3;
|
2015-02-09 02:32:47 -08:00
|
|
|
encoder.tail_biting = true;
|
|
|
|
memcpy(encoder.poly, poly, 3 * sizeof(int));
|
|
|
|
|
|
|
|
memcpy(q->tmp_cqi, data, sizeof(uint8_t) * nof_bits);
|
2021-03-19 03:45:56 -07:00
|
|
|
srsran_crc_attach(&q->crc, q->tmp_cqi, nof_bits);
|
2015-02-09 02:32:47 -08:00
|
|
|
|
2018-01-31 03:43:22 -08:00
|
|
|
DEBUG("cqi_crc_tx=");
|
2021-03-19 03:45:56 -07:00
|
|
|
if (SRSRAN_VERBOSE_ISDEBUG()) {
|
|
|
|
srsran_vec_fprint_b(stdout, q->tmp_cqi, nof_bits + 8);
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
2019-12-16 07:04:22 -08:00
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
srsran_convcoder_encode(&encoder, q->tmp_cqi, q->encoded_cqi, nof_bits + 8);
|
2015-02-09 02:32:47 -08:00
|
|
|
|
2018-01-31 03:43:22 -08:00
|
|
|
DEBUG("cconv_tx=");
|
2021-03-19 03:45:56 -07:00
|
|
|
if (SRSRAN_VERBOSE_ISDEBUG()) {
|
|
|
|
srsran_vec_fprint_b(stdout, q->encoded_cqi, 3 * (nof_bits + 8));
|
2015-02-09 02:32:47 -08:00
|
|
|
}
|
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
srsran_rm_conv_tx(q->encoded_cqi, 3 * (nof_bits + 8), q_bits, Q);
|
2019-12-16 07:04:22 -08:00
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
return SRSRAN_SUCCESS;
|
2015-02-09 02:32:47 -08:00
|
|
|
} else {
|
2021-03-19 03:45:56 -07:00
|
|
|
return SRSRAN_ERROR_INVALID_INPUTS;
|
2015-02-09 02:32:47 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
int decode_cqi_long(srsran_uci_cqi_pusch_t* q, int16_t* q_bits, uint32_t Q, uint8_t* data, uint32_t nof_bits)
|
2016-04-27 08:23:36 -07:00
|
|
|
{
|
2021-03-19 03:45:56 -07:00
|
|
|
int ret = SRSRAN_ERROR_INVALID_INPUTS;
|
|
|
|
if (nof_bits + 8 < SRSRAN_UCI_MAX_CQI_LEN_PUSCH && q != NULL && data != NULL && q_bits != NULL) {
|
|
|
|
srsran_rm_conv_rx_s(q_bits, Q, q->encoded_cqi_s, 3 * (nof_bits + 8));
|
2016-04-27 08:23:36 -07:00
|
|
|
|
2018-01-31 03:43:22 -08:00
|
|
|
DEBUG("cconv_rx=");
|
2021-03-19 03:45:56 -07:00
|
|
|
if (SRSRAN_VERBOSE_ISDEBUG()) {
|
|
|
|
srsran_vec_fprint_s(stdout, q->encoded_cqi_s, 3 * (nof_bits + 8));
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
srsran_viterbi_decode_s(&q->viterbi, q->encoded_cqi_s, q->tmp_cqi, nof_bits + 8);
|
2019-12-16 07:04:22 -08:00
|
|
|
|
2018-01-31 03:43:22 -08:00
|
|
|
DEBUG("cqi_crc_rx=");
|
2021-03-19 03:45:56 -07:00
|
|
|
if (SRSRAN_VERBOSE_ISDEBUG()) {
|
|
|
|
srsran_vec_fprint_b(stdout, q->tmp_cqi, nof_bits + 8);
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
2019-12-16 07:04:22 -08:00
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
ret = srsran_crc_checksum(&q->crc, q->tmp_cqi, nof_bits + 8);
|
2019-12-16 07:04:22 -08:00
|
|
|
if (ret == 0) {
|
|
|
|
memcpy(data, q->tmp_cqi, nof_bits * sizeof(uint8_t));
|
2017-08-22 06:06:51 -07:00
|
|
|
ret = 1;
|
2016-04-27 08:23:36 -07:00
|
|
|
} else {
|
2019-12-16 07:04:22 -08:00
|
|
|
ret = 0;
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
|
|
|
}
|
2019-12-16 07:04:22 -08:00
|
|
|
return ret;
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
|
|
|
|
2019-12-16 07:04:22 -08:00
|
|
|
/* Encode UCI CQI/PMI
|
2016-04-27 08:23:36 -07:00
|
|
|
*/
|
2021-03-19 03:45:56 -07:00
|
|
|
int srsran_uci_decode_cqi_pusch(srsran_uci_cqi_pusch_t* q,
|
|
|
|
srsran_pusch_cfg_t* cfg,
|
2019-04-23 01:53:11 -07:00
|
|
|
int16_t* q_bits,
|
|
|
|
float beta,
|
|
|
|
uint32_t Q_prime_ri,
|
|
|
|
uint32_t cqi_len,
|
|
|
|
uint8_t* cqi_data,
|
|
|
|
bool* cqi_ack)
|
2016-04-27 08:23:36 -07:00
|
|
|
{
|
|
|
|
if (beta < 0) {
|
2021-02-10 04:46:25 -08:00
|
|
|
ERROR("Error beta is reserved");
|
2019-12-16 07:04:22 -08:00
|
|
|
return -1;
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
|
|
|
uint32_t Q_prime = Q_prime_cqi(cfg, cqi_len, beta, Q_prime_ri);
|
2021-03-19 03:45:56 -07:00
|
|
|
uint32_t Qm = srsran_mod_bits_x_symbol(cfg->grant.tb.mod);
|
2016-04-27 08:23:36 -07:00
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
int ret = SRSRAN_ERROR;
|
2016-04-27 08:23:36 -07:00
|
|
|
if (cqi_len <= 11) {
|
2019-04-23 01:53:11 -07:00
|
|
|
ret = decode_cqi_short(q, q_bits, Q_prime * Qm, cqi_data, cqi_len);
|
|
|
|
if (cqi_ack) {
|
|
|
|
*cqi_ack = true;
|
|
|
|
}
|
2016-04-27 08:23:36 -07:00
|
|
|
} else {
|
2019-04-23 01:53:11 -07:00
|
|
|
ret = decode_cqi_long(q, q_bits, Q_prime * Qm, cqi_data, cqi_len);
|
2016-04-27 08:23:36 -07:00
|
|
|
if (ret == 1) {
|
|
|
|
if (cqi_ack) {
|
2019-12-16 07:04:22 -08:00
|
|
|
*cqi_ack = true;
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
2019-12-16 07:04:22 -08:00
|
|
|
ret = 0;
|
2016-04-27 08:23:36 -07:00
|
|
|
} else if (ret == 0) {
|
|
|
|
if (cqi_ack) {
|
2019-12-16 07:04:22 -08:00
|
|
|
*cqi_ack = false;
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
} else {
|
2019-12-16 07:04:22 -08:00
|
|
|
return (int)Q_prime;
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-12-16 07:04:22 -08:00
|
|
|
/* Encode UCI CQI/PMI as described in 5.2.2.6 of 36.212
|
2015-02-09 02:32:47 -08:00
|
|
|
*/
|
2021-03-19 03:45:56 -07:00
|
|
|
int srsran_uci_encode_cqi_pusch(srsran_uci_cqi_pusch_t* q,
|
|
|
|
srsran_pusch_cfg_t* cfg,
|
2019-04-23 01:53:11 -07:00
|
|
|
uint8_t* cqi_data,
|
|
|
|
uint32_t cqi_len,
|
|
|
|
float beta,
|
|
|
|
uint32_t Q_prime_ri,
|
|
|
|
uint8_t* q_bits)
|
2015-02-09 02:32:47 -08:00
|
|
|
{
|
2015-03-24 07:58:33 -07:00
|
|
|
if (beta < 0) {
|
2021-02-10 04:46:25 -08:00
|
|
|
ERROR("Error beta is reserved");
|
2019-04-23 01:53:11 -07:00
|
|
|
return -1;
|
2015-03-24 07:58:33 -07:00
|
|
|
}
|
2015-04-27 09:14:28 -07:00
|
|
|
|
|
|
|
uint32_t Q_prime = Q_prime_cqi(cfg, cqi_len, beta, Q_prime_ri);
|
2021-03-19 03:45:56 -07:00
|
|
|
uint32_t Qm = srsran_mod_bits_x_symbol(cfg->grant.tb.mod);
|
2019-04-23 01:53:11 -07:00
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
int ret = SRSRAN_ERROR;
|
2015-02-09 02:32:47 -08:00
|
|
|
if (cqi_len <= 11) {
|
2019-04-23 01:53:11 -07:00
|
|
|
ret = encode_cqi_short(q, cqi_data, cqi_len, q_bits, Q_prime * Qm);
|
2015-02-09 02:32:47 -08:00
|
|
|
} else {
|
2019-04-23 01:53:11 -07:00
|
|
|
ret = encode_cqi_long(q, cqi_data, cqi_len, q_bits, Q_prime * Qm);
|
2015-02-09 02:32:47 -08:00
|
|
|
}
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
} else {
|
2019-04-23 01:53:11 -07:00
|
|
|
return (int)Q_prime;
|
2015-02-09 02:32:47 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-09-18 06:46:27 -07:00
|
|
|
/* Generates UCI-ACK bits and computes position in q bits */
|
2019-12-16 07:04:22 -08:00
|
|
|
static int uci_ulsch_interleave_ack_gen(uint32_t ack_q_bit_idx,
|
|
|
|
uint32_t Qm,
|
|
|
|
uint32_t H_prime_total,
|
|
|
|
uint32_t N_pusch_symbs,
|
2021-03-19 03:45:56 -07:00
|
|
|
srsran_uci_bit_t* ack_bits)
|
2016-04-27 08:23:36 -07:00
|
|
|
{
|
2015-02-12 04:22:17 -08:00
|
|
|
const uint32_t ack_column_set_norm[4] = {2, 3, 8, 9};
|
2019-12-16 07:04:22 -08:00
|
|
|
const uint32_t ack_column_set_ext[4] = {1, 2, 6, 7};
|
2015-03-24 07:58:33 -07:00
|
|
|
|
2019-04-23 01:53:11 -07:00
|
|
|
if (H_prime_total / N_pusch_symbs >= 1 + ack_q_bit_idx / 4) {
|
2019-12-16 07:04:22 -08:00
|
|
|
uint32_t row = H_prime_total / N_pusch_symbs - 1 - ack_q_bit_idx / 4;
|
|
|
|
uint32_t colidx = (3 * ack_q_bit_idx) % 4;
|
2019-04-23 01:53:11 -07:00
|
|
|
uint32_t col = N_pusch_symbs > 10 ? ack_column_set_norm[colidx] : ack_column_set_ext[colidx];
|
2019-12-16 07:04:22 -08:00
|
|
|
for (uint32_t k = 0; k < Qm; k++) {
|
|
|
|
ack_bits[k].position = row * Qm + (H_prime_total / N_pusch_symbs) * col * Qm + k;
|
2019-04-23 01:53:11 -07:00
|
|
|
}
|
2021-03-19 03:45:56 -07:00
|
|
|
return SRSRAN_SUCCESS;
|
2015-02-12 04:22:17 -08:00
|
|
|
} else {
|
2021-02-10 04:46:25 -08:00
|
|
|
ERROR("Error interleaving UCI-ACK bit idx %d for H_prime_total=%d and N_pusch_symbs=%d",
|
2019-04-23 01:53:11 -07:00
|
|
|
ack_q_bit_idx,
|
|
|
|
H_prime_total,
|
|
|
|
N_pusch_symbs);
|
2021-03-19 03:45:56 -07:00
|
|
|
return SRSRAN_ERROR;
|
2015-02-12 04:22:17 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Inserts UCI-RI bits into the correct positions in the g buffer before interleaving */
|
2019-12-16 07:04:22 -08:00
|
|
|
static int uci_ulsch_interleave_ri_gen(uint32_t ri_q_bit_idx,
|
|
|
|
uint32_t Qm,
|
|
|
|
uint32_t H_prime_total,
|
|
|
|
uint32_t N_pusch_symbs,
|
2021-03-19 03:45:56 -07:00
|
|
|
srsran_uci_bit_t* ri_bits)
|
2016-04-27 08:23:36 -07:00
|
|
|
{
|
2019-12-16 07:04:22 -08:00
|
|
|
static uint32_t ri_column_set_norm[4] = {1, 4, 7, 10};
|
2015-02-12 04:22:17 -08:00
|
|
|
static uint32_t ri_column_set_ext[4] = {0, 3, 5, 8};
|
|
|
|
|
2019-12-16 07:04:22 -08:00
|
|
|
if (H_prime_total / N_pusch_symbs >= 1 + ri_q_bit_idx / 4) {
|
|
|
|
uint32_t row = H_prime_total / N_pusch_symbs - 1 - ri_q_bit_idx / 4;
|
|
|
|
uint32_t colidx = (3 * ri_q_bit_idx) % 4;
|
2019-04-23 01:53:11 -07:00
|
|
|
uint32_t col = N_pusch_symbs > 10 ? ri_column_set_norm[colidx] : ri_column_set_ext[colidx];
|
2015-09-05 02:51:19 -07:00
|
|
|
|
2019-12-16 07:04:22 -08:00
|
|
|
for (uint32_t k = 0; k < Qm; k++) {
|
2019-04-23 01:53:11 -07:00
|
|
|
ri_bits[k].position = row * Qm + (H_prime_total / N_pusch_symbs) * col * Qm + k;
|
2019-12-16 07:04:22 -08:00
|
|
|
}
|
2021-03-19 03:45:56 -07:00
|
|
|
return SRSRAN_SUCCESS;
|
2015-02-12 04:22:17 -08:00
|
|
|
} else {
|
2021-02-10 04:46:25 -08:00
|
|
|
ERROR("Error interleaving UCI-RI bit idx %d for H_prime_total=%d and N_pusch_symbs=%d",
|
2019-04-23 01:53:11 -07:00
|
|
|
ri_q_bit_idx,
|
|
|
|
H_prime_total,
|
|
|
|
N_pusch_symbs);
|
2021-03-19 03:45:56 -07:00
|
|
|
return SRSRAN_ERROR;
|
2015-02-12 04:22:17 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
static uint32_t Q_prime_ri_ack(srsran_pusch_cfg_t* cfg, uint32_t O, uint32_t O_cqi, float beta)
|
2019-12-16 07:04:22 -08:00
|
|
|
{
|
2015-03-24 07:58:33 -07:00
|
|
|
if (beta < 0) {
|
2021-02-10 04:46:25 -08:00
|
|
|
ERROR("Error beta is reserved");
|
2019-12-16 07:04:22 -08:00
|
|
|
return -1;
|
2015-03-24 07:58:33 -07:00
|
|
|
}
|
|
|
|
|
2019-04-23 01:53:11 -07:00
|
|
|
uint32_t K = cfg->K_segm;
|
|
|
|
|
2015-02-10 07:49:11 -08:00
|
|
|
// If not carrying UL-SCH, get Q_prime according to 5.2.4.1
|
|
|
|
if (K == 0) {
|
2015-02-10 08:09:50 -08:00
|
|
|
if (O_cqi <= 11) {
|
2019-04-23 01:53:11 -07:00
|
|
|
K = O_cqi;
|
2015-02-10 08:09:50 -08:00
|
|
|
} else {
|
2019-04-23 01:53:11 -07:00
|
|
|
K = O_cqi + 8;
|
2015-02-10 08:09:50 -08:00
|
|
|
}
|
2015-02-10 07:49:11 -08:00
|
|
|
}
|
2015-01-29 16:15:09 -08:00
|
|
|
|
2021-04-28 01:30:38 -07:00
|
|
|
if (K == 0) {
|
|
|
|
ERROR("K is zero!");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
uint32_t x = (uint32_t)ceilf((float)O * cfg->grant.L_prb * SRSRAN_NRE * cfg->grant.nof_symb * beta / K);
|
2015-01-29 16:15:09 -08:00
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
uint32_t Q_prime = SRSRAN_MIN(x, 4 * cfg->grant.L_prb * SRSRAN_NRE);
|
2019-04-23 01:53:11 -07:00
|
|
|
|
|
|
|
return Q_prime;
|
2015-01-29 16:15:09 -08:00
|
|
|
}
|
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
uint32_t srsran_qprime_ack_ext(uint32_t L_prb, uint32_t nof_symbols, uint32_t tbs, uint32_t nof_ack, float beta)
|
2020-08-25 13:30:35 -07:00
|
|
|
{
|
2021-03-19 03:45:56 -07:00
|
|
|
srsran_pusch_cfg_t cfg = {};
|
2020-08-25 13:30:35 -07:00
|
|
|
cfg.grant.L_prb = L_prb;
|
|
|
|
cfg.grant.nof_symb = nof_symbols;
|
|
|
|
cfg.K_segm = tbs;
|
|
|
|
return Q_prime_ri_ack(&cfg, nof_ack, 0, beta);
|
|
|
|
}
|
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
static uint32_t encode_ri_ack(const uint8_t data[2], uint32_t O_ack, uint8_t Qm, srsran_uci_bit_t* q_encoded_bits)
|
2016-04-27 08:23:36 -07:00
|
|
|
{
|
2017-09-07 07:30:15 -07:00
|
|
|
uint32_t i = 0;
|
|
|
|
|
2019-04-23 01:53:11 -07:00
|
|
|
if (O_ack == 1) {
|
|
|
|
q_encoded_bits[i++].type = data[0] ? UCI_BIT_1 : UCI_BIT_0;
|
|
|
|
q_encoded_bits[i++].type = UCI_BIT_REPETITION;
|
2019-12-16 07:04:22 -08:00
|
|
|
while (i < Qm) {
|
2019-04-23 01:53:11 -07:00
|
|
|
q_encoded_bits[i++].type = UCI_BIT_PLACEHOLDER;
|
2017-09-07 07:30:15 -07:00
|
|
|
}
|
2019-04-23 01:53:11 -07:00
|
|
|
} else if (O_ack == 2) {
|
|
|
|
q_encoded_bits[i++].type = data[0] ? UCI_BIT_1 : UCI_BIT_0;
|
|
|
|
q_encoded_bits[i++].type = data[1] ? UCI_BIT_1 : UCI_BIT_0;
|
|
|
|
while (i < Qm) {
|
|
|
|
q_encoded_bits[i++].type = UCI_BIT_PLACEHOLDER;
|
2017-09-07 07:30:15 -07:00
|
|
|
}
|
2019-04-23 01:53:11 -07:00
|
|
|
q_encoded_bits[i++].type = (data[0] ^ data[1]) ? UCI_BIT_1 : UCI_BIT_0;
|
|
|
|
q_encoded_bits[i++].type = data[0] ? UCI_BIT_1 : UCI_BIT_0;
|
|
|
|
while (i < Qm * 2) {
|
|
|
|
q_encoded_bits[i++].type = UCI_BIT_PLACEHOLDER;
|
2017-09-07 07:30:15 -07:00
|
|
|
}
|
2019-04-23 01:53:11 -07:00
|
|
|
q_encoded_bits[i++].type = data[1] ? UCI_BIT_1 : UCI_BIT_0;
|
|
|
|
q_encoded_bits[i++].type = (data[0] ^ data[1]) ? UCI_BIT_1 : UCI_BIT_0;
|
2019-12-16 07:04:22 -08:00
|
|
|
while (i < Qm * 3) {
|
2019-04-23 01:53:11 -07:00
|
|
|
q_encoded_bits[i++].type = UCI_BIT_PLACEHOLDER;
|
2017-09-07 07:30:15 -07:00
|
|
|
}
|
2015-02-12 04:22:17 -08:00
|
|
|
}
|
2017-09-07 07:30:15 -07:00
|
|
|
|
|
|
|
return i;
|
2015-02-12 04:22:17 -08:00
|
|
|
}
|
2017-09-26 04:08:05 -07:00
|
|
|
|
2019-04-23 01:53:11 -07:00
|
|
|
static uint32_t
|
2021-03-19 03:45:56 -07:00
|
|
|
encode_ack_long(const uint8_t* data, uint32_t O_ack, uint8_t Q_m, uint32_t Q_prime, srsran_uci_bit_t* q_encoded_bits)
|
2019-04-23 01:53:11 -07:00
|
|
|
{
|
|
|
|
uint32_t Q_ack = Q_m * Q_prime;
|
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
if (O_ack > SRSRAN_UCI_MAX_ACK_BITS) {
|
|
|
|
ERROR("Error encoding long ACK bits: O_ack can't be higher than %d", SRSRAN_UCI_MAX_ACK_BITS);
|
2019-04-23 01:53:11 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-01-08 01:47:14 -08:00
|
|
|
// Encoded bits
|
2021-03-19 03:45:56 -07:00
|
|
|
uint8_t q[SRSRAN_FEC_BLOCK_SIZE] = {};
|
2021-01-08 01:47:14 -08:00
|
|
|
|
|
|
|
// Encode
|
2021-03-19 03:45:56 -07:00
|
|
|
srsran_block_encode(data, O_ack, q, SRSRAN_FEC_BLOCK_SIZE);
|
2021-01-08 01:47:14 -08:00
|
|
|
|
|
|
|
// Convert to UCI bits
|
2019-04-23 01:53:11 -07:00
|
|
|
for (uint32_t i = 0; i < Q_ack; i++) {
|
2021-03-19 03:45:56 -07:00
|
|
|
q_encoded_bits[i].type = q[i % SRSRAN_FEC_BLOCK_SIZE] ? UCI_BIT_1 : UCI_BIT_0;
|
2019-04-23 01:53:11 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return Q_ack;
|
|
|
|
}
|
2017-09-26 04:08:05 -07:00
|
|
|
|
2020-07-27 06:44:57 -07:00
|
|
|
static int32_t decode_ri_ack_1bit(const int16_t* q_bits, const uint8_t* c_seq, uint8_t data[1])
|
2017-09-26 04:08:05 -07:00
|
|
|
{
|
2020-07-27 06:44:57 -07:00
|
|
|
int32_t sum = (int32_t)(q_bits[0] + q_bits[1]);
|
|
|
|
|
2020-03-04 05:53:41 -08:00
|
|
|
if (data) {
|
2020-07-27 06:44:57 -07:00
|
|
|
data[0] = (sum > 0) ? 1 : 0;
|
2020-03-04 05:53:41 -08:00
|
|
|
}
|
2020-07-27 06:44:57 -07:00
|
|
|
|
|
|
|
return abs(sum);
|
2017-09-26 04:08:05 -07:00
|
|
|
}
|
|
|
|
|
2020-07-27 06:44:57 -07:00
|
|
|
static int32_t decode_ri_ack_2bits(const int16_t* llr, uint32_t Qm, uint8_t data[2])
|
2016-04-27 08:23:36 -07:00
|
|
|
{
|
2020-03-04 05:53:41 -08:00
|
|
|
uint32_t p0 = Qm * 0 + 0;
|
|
|
|
uint32_t p1 = Qm * 0 + 1;
|
|
|
|
uint32_t p2 = Qm * 1 + 0;
|
|
|
|
uint32_t p3 = Qm * 1 + 1;
|
|
|
|
uint32_t p4 = Qm * 2 + 0;
|
|
|
|
uint32_t p5 = Qm * 2 + 1;
|
|
|
|
|
2020-07-27 06:44:57 -07:00
|
|
|
int16_t sum1 = llr[p0] + llr[p3];
|
|
|
|
int16_t sum2 = llr[p1] + llr[p4];
|
|
|
|
int16_t sum3 = llr[p2] + llr[p5];
|
|
|
|
|
|
|
|
data[0] = (sum1 > 0) ? 1 : 0;
|
|
|
|
data[1] = (sum2 > 0) ? 1 : 0;
|
2020-03-04 05:53:41 -08:00
|
|
|
|
2020-07-27 06:44:57 -07:00
|
|
|
bool parity_check = (sum3 > 0) == (data[0] ^ data[1]);
|
|
|
|
|
|
|
|
// Return 0 if parity check is not valid
|
|
|
|
return (parity_check ? (abs(sum1) + abs(sum2) + abs(sum3)) : 0);
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
|
|
|
|
2019-04-23 01:53:11 -07:00
|
|
|
// Table 5.2.2.6-A
|
|
|
|
const static uint8_t w_scram[4][4] = {{1, 1, 1, 1}, {1, 0, 1, 0}, {1, 1, 0, 0}, {1, 0, 0, 1}};
|
2018-01-10 07:29:17 -08:00
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
static void uci_ack_scramble_tdd(srsran_uci_bit_t* q, uint32_t O_ack, uint32_t Q_ack, uint32_t N_bundle)
|
2019-04-23 01:53:11 -07:00
|
|
|
{
|
|
|
|
if (N_bundle == 0) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t wi = (N_bundle - 1) % 4;
|
|
|
|
|
|
|
|
uint32_t m = O_ack == 1 ? 1 : 3;
|
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
srsran_uci_bit_type_t q_m1 = q[0].type;
|
2019-04-23 01:53:11 -07:00
|
|
|
uint32_t k = 0;
|
|
|
|
for (uint32_t i = 0; i < Q_ack; i++) {
|
|
|
|
switch (q[i].type) {
|
|
|
|
case UCI_BIT_REPETITION:
|
|
|
|
// A repetition bit always comes after a 1 or 0 so we can do i-1
|
|
|
|
if (i > 0) {
|
|
|
|
q[i].type = ((q_m1 == UCI_BIT_1 ? 1 : 0) + w_scram[wi][k / m]) % 2;
|
|
|
|
}
|
|
|
|
k = (k + 1) % (4 * m);
|
|
|
|
break;
|
|
|
|
case UCI_BIT_PLACEHOLDER:
|
|
|
|
// do not change
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
q_m1 = q[i].type;
|
|
|
|
q[i].type = ((q[i].type == UCI_BIT_1 ? 1 : 0) + w_scram[wi][k / m]) % 2;
|
|
|
|
k = (k + 1) % (4 * m);
|
|
|
|
break;
|
2018-01-31 07:48:50 -08:00
|
|
|
}
|
2018-01-10 07:29:17 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-04-23 01:53:11 -07:00
|
|
|
/* Encode UCI ACK/RI bits as described in 5.2.2.6 of 36.212
|
2018-01-10 07:29:17 -08:00
|
|
|
* Currently only supporting 1-bit RI
|
|
|
|
*/
|
2021-03-19 03:45:56 -07:00
|
|
|
int srsran_uci_encode_ack_ri(srsran_pusch_cfg_t* cfg,
|
2019-04-23 01:53:11 -07:00
|
|
|
uint8_t* data,
|
|
|
|
uint32_t O_ack,
|
|
|
|
uint32_t O_cqi,
|
|
|
|
float beta,
|
|
|
|
uint32_t H_prime_total,
|
|
|
|
bool input_is_ri,
|
|
|
|
uint32_t N_bundle,
|
2021-03-19 03:45:56 -07:00
|
|
|
srsran_uci_bit_t* bits)
|
2018-01-10 07:29:17 -08:00
|
|
|
{
|
|
|
|
if (beta < 0) {
|
2021-02-10 04:46:25 -08:00
|
|
|
ERROR("Error beta is reserved");
|
2018-01-10 07:29:17 -08:00
|
|
|
return -1;
|
|
|
|
}
|
2019-04-23 01:53:11 -07:00
|
|
|
uint32_t Q_prime = Q_prime_ri_ack(cfg, O_ack, O_cqi, beta);
|
2018-01-10 07:29:17 -08:00
|
|
|
|
2019-04-23 01:53:11 -07:00
|
|
|
uint32_t Q_ack = 0;
|
2021-03-19 03:45:56 -07:00
|
|
|
uint32_t Qm = srsran_mod_bits_x_symbol(cfg->grant.tb.mod);
|
2018-01-10 07:29:17 -08:00
|
|
|
|
2019-04-23 01:53:11 -07:00
|
|
|
if (O_ack < 3) {
|
|
|
|
uint32_t enc_len = encode_ri_ack(data, O_ack, Qm, bits);
|
|
|
|
// Repeat bits Q_prime times, remainder bits will be ignored later
|
|
|
|
while (Q_ack < Q_prime * Qm) {
|
|
|
|
for (uint32_t j = 0; j < enc_len; j++) {
|
|
|
|
bits[Q_ack++].type = bits[j].type;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
Q_ack = encode_ack_long(data, O_ack, Qm, Q_prime, bits);
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
|
|
|
|
2019-04-23 01:53:11 -07:00
|
|
|
// Generate interleaver positions
|
|
|
|
if (Q_ack > 0) {
|
|
|
|
for (uint32_t i = 0; i < Q_prime; i++) {
|
|
|
|
if (input_is_ri) {
|
|
|
|
uci_ulsch_interleave_ri_gen(i, Qm, H_prime_total, cfg->grant.nof_symb, &bits[Qm * i]);
|
2018-01-31 07:48:50 -08:00
|
|
|
} else {
|
2019-04-23 01:53:11 -07:00
|
|
|
uci_ulsch_interleave_ack_gen(i, Qm, H_prime_total, cfg->grant.nof_symb, &bits[Qm * i]);
|
2018-01-31 07:48:50 -08:00
|
|
|
}
|
2019-04-23 01:53:11 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
// TDD-bundling scrambling
|
|
|
|
if (!input_is_ri && N_bundle && O_ack > 0) {
|
|
|
|
uci_ack_scramble_tdd(bits, O_ack, Q_prime * Qm, N_bundle);
|
2017-09-08 01:41:52 -07:00
|
|
|
}
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
2017-09-07 08:46:30 -07:00
|
|
|
|
2019-04-23 01:53:11 -07:00
|
|
|
return (int)Q_prime;
|
2015-02-12 04:22:17 -08:00
|
|
|
}
|
|
|
|
|
2017-11-16 05:48:03 -08:00
|
|
|
/* Decode UCI ACK/RI bits as described in 5.2.2.6 of 36.212
|
2016-04-27 08:23:36 -07:00
|
|
|
* Currently only supporting 1-bit RI
|
|
|
|
*/
|
2021-03-19 03:45:56 -07:00
|
|
|
int srsran_uci_decode_ack_ri(srsran_pusch_cfg_t* cfg,
|
2019-04-23 01:53:11 -07:00
|
|
|
int16_t* q_bits,
|
|
|
|
uint8_t* c_seq,
|
|
|
|
float beta,
|
|
|
|
uint32_t H_prime_total,
|
|
|
|
uint32_t O_cqi,
|
2021-03-19 03:45:56 -07:00
|
|
|
srsran_uci_bit_t* ack_ri_bits,
|
2020-04-15 06:38:48 -07:00
|
|
|
uint8_t* data,
|
2020-07-27 06:44:57 -07:00
|
|
|
bool* valid,
|
2019-04-23 01:53:11 -07:00
|
|
|
uint32_t nof_bits,
|
|
|
|
bool is_ri)
|
2016-04-27 08:23:36 -07:00
|
|
|
{
|
|
|
|
if (beta < 0) {
|
2021-02-10 04:46:25 -08:00
|
|
|
ERROR("Error beta (%f) is reserved", beta);
|
2021-03-19 03:45:56 -07:00
|
|
|
return SRSRAN_ERROR;
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
|
|
|
|
2017-11-16 05:48:03 -08:00
|
|
|
uint32_t Qprime = Q_prime_ri_ack(cfg, nof_bits, O_cqi, beta);
|
2021-03-19 03:45:56 -07:00
|
|
|
uint32_t Qm = srsran_mod_bits_x_symbol(cfg->grant.tb.mod);
|
2016-04-27 08:23:36 -07:00
|
|
|
|
2020-03-04 05:53:41 -08:00
|
|
|
int16_t llr_acc[32] = {}; ///< LLR accumulator
|
2021-05-25 02:56:30 -07:00
|
|
|
uint32_t nof_acc = (nof_bits == 1) ? Qm
|
|
|
|
: (nof_bits == 2) ? Qm * 3
|
|
|
|
: SRSRAN_FEC_BLOCK_SIZE; ///< Number of required LLR
|
|
|
|
uint32_t count_acc = 0; ///< LLR counter
|
2020-03-04 05:53:41 -08:00
|
|
|
|
2017-11-16 05:48:03 -08:00
|
|
|
for (uint32_t i = 0; i < Qprime; i++) {
|
|
|
|
if (is_ri) {
|
2020-03-04 05:53:41 -08:00
|
|
|
uci_ulsch_interleave_ri_gen(i, Qm, H_prime_total, cfg->grant.nof_symb, &ack_ri_bits[count_acc]);
|
2017-11-16 05:48:03 -08:00
|
|
|
} else {
|
2020-03-04 05:53:41 -08:00
|
|
|
uci_ulsch_interleave_ack_gen(i, Qm, H_prime_total, cfg->grant.nof_symb, &ack_ri_bits[count_acc]);
|
2017-11-16 05:48:03 -08:00
|
|
|
}
|
2020-03-04 05:53:41 -08:00
|
|
|
|
|
|
|
/// Extract and accumulate LLR
|
|
|
|
for (uint32_t j = 0; j < Qm; j++, count_acc++) {
|
|
|
|
// Calculate circular LLR index
|
|
|
|
uint32_t acc_idx = count_acc % nof_acc;
|
2020-03-06 10:58:37 -08:00
|
|
|
uint32_t pos = ack_ri_bits[count_acc].position;
|
|
|
|
|
|
|
|
int16_t q = q_bits[pos];
|
|
|
|
|
|
|
|
// Remove scrambling of repeated bits
|
|
|
|
if (nof_bits == 1) {
|
|
|
|
if (acc_idx == 1 && pos > 0) {
|
|
|
|
q = (c_seq[pos] == c_seq[pos - 1]) ? +q : -q;
|
|
|
|
}
|
|
|
|
}
|
2020-03-04 05:53:41 -08:00
|
|
|
|
|
|
|
// Accumulate LLR
|
2020-03-06 10:58:37 -08:00
|
|
|
llr_acc[acc_idx] += q;
|
2020-03-04 05:53:41 -08:00
|
|
|
|
|
|
|
/// Limit accumulator boundaries
|
2021-03-19 03:45:56 -07:00
|
|
|
llr_acc[acc_idx] = SRSRAN_MIN(llr_acc[acc_idx], INT16_MAX / 2);
|
|
|
|
llr_acc[acc_idx] = SRSRAN_MAX(llr_acc[acc_idx], -INT16_MAX / 2);
|
2017-11-16 05:48:03 -08:00
|
|
|
}
|
2016-04-27 08:23:36 -07:00
|
|
|
}
|
|
|
|
|
2020-03-04 05:53:41 -08:00
|
|
|
/// Decode UCI HARQ/ACK bits as described in 5.2.2.6 of 36.212
|
2020-12-01 02:45:54 -08:00
|
|
|
int32_t thr = (count_acc * ((Qm < 4) ? 100 : (Qm < 6) ? 200 : (Qm < 8) ? 700 : 1000)) / Qm;
|
2020-07-27 06:44:57 -07:00
|
|
|
int32_t corr = 0;
|
2020-03-04 05:53:41 -08:00
|
|
|
switch (nof_bits) {
|
|
|
|
case 1:
|
2020-07-27 06:44:57 -07:00
|
|
|
corr = decode_ri_ack_1bit(llr_acc, c_seq, data);
|
2020-03-04 05:53:41 -08:00
|
|
|
break;
|
|
|
|
case 2:
|
2020-07-27 06:44:57 -07:00
|
|
|
corr = decode_ri_ack_2bits(llr_acc, Qm, data);
|
2020-03-04 05:53:41 -08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
// For more than 2 bits...
|
2021-03-19 03:45:56 -07:00
|
|
|
corr = srsran_block_decode_i16(llr_acc, SRSRAN_FEC_BLOCK_SIZE, data, nof_bits);
|
2020-07-27 06:44:57 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
if (valid) {
|
|
|
|
*valid = corr > thr;
|
2015-03-24 07:58:33 -07:00
|
|
|
}
|
2015-01-29 16:15:09 -08:00
|
|
|
|
2019-12-16 07:04:22 -08:00
|
|
|
return (int)Qprime;
|
2015-01-29 16:15:09 -08:00
|
|
|
}
|
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
uint32_t srsran_uci_cfg_total_ack(const srsran_uci_cfg_t* uci_cfg)
|
2019-10-01 07:05:44 -07:00
|
|
|
{
|
|
|
|
uint32_t nof_ack = 0;
|
2021-03-19 03:45:56 -07:00
|
|
|
for (uint32_t i = 0; i < SRSRAN_MAX_CARRIERS; i++) {
|
2019-10-01 07:05:44 -07:00
|
|
|
nof_ack += uci_cfg->ack[i].nof_acks;
|
|
|
|
}
|
|
|
|
return nof_ack;
|
|
|
|
}
|
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
void srsran_uci_data_reset(srsran_uci_data_t* uci_data)
|
2019-10-01 07:05:44 -07:00
|
|
|
{
|
2021-03-19 03:45:56 -07:00
|
|
|
bzero(uci_data, sizeof(srsran_uci_data_t));
|
2019-10-01 07:05:44 -07:00
|
|
|
|
|
|
|
/* Set all ACKs to DTX */
|
2021-03-19 03:45:56 -07:00
|
|
|
memset(uci_data->value.ack.ack_value, 2, SRSRAN_UCI_MAX_ACK_BITS);
|
2019-10-01 07:05:44 -07:00
|
|
|
}
|
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
int srsran_uci_data_info(srsran_uci_cfg_t* uci_cfg, srsran_uci_value_t* uci_data, char* str, uint32_t str_len)
|
2019-04-23 01:53:11 -07:00
|
|
|
{
|
|
|
|
int n = 0;
|
|
|
|
|
|
|
|
if (uci_cfg->is_scheduling_request_tti) {
|
2021-03-19 03:45:56 -07:00
|
|
|
n = srsran_print_check(str, str_len, n, ", sr=%s", uci_data->scheduling_request ? "yes" : "no");
|
2019-04-23 01:53:11 -07:00
|
|
|
}
|
|
|
|
|
2021-03-19 03:45:56 -07:00
|
|
|
uint32_t nof_acks = srsran_uci_cfg_total_ack(uci_cfg);
|
2020-01-31 10:42:56 -08:00
|
|
|
if (nof_acks) {
|
2021-03-19 03:45:56 -07:00
|
|
|
n = srsran_print_check(str, str_len, n, ", ack=");
|
2020-07-03 03:58:49 -07:00
|
|
|
if (uci_data->ack.valid) {
|
|
|
|
for (uint32_t i = 0; i < nof_acks; i++) {
|
2021-03-19 03:45:56 -07:00
|
|
|
n = srsran_print_check(str, str_len, n, "%d", uci_data->ack.ack_value[i]);
|
2020-07-03 03:58:49 -07:00
|
|
|
}
|
|
|
|
if (uci_cfg->ack[0].N_bundle) {
|
2021-03-19 03:45:56 -07:00
|
|
|
n = srsran_print_check(str, str_len, n, ", n_bundle=%d", uci_cfg->ack[0].N_bundle);
|
2020-07-03 03:58:49 -07:00
|
|
|
}
|
|
|
|
} else {
|
2021-03-19 03:45:56 -07:00
|
|
|
n = srsran_print_check(str, str_len, n, "invalid");
|
2019-04-23 01:53:11 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (uci_cfg->cqi.ri_len) {
|
2021-03-19 03:45:56 -07:00
|
|
|
n = srsran_print_check(str, str_len, n, ", ri=%d", uci_data->ri);
|
2019-04-23 01:53:11 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
if (uci_cfg->cqi.data_enable) {
|
2021-03-19 03:45:56 -07:00
|
|
|
char cqi_str[SRSRAN_CQI_STR_MAX_CHAR] = "";
|
|
|
|
srsran_cqi_value_tostring(&uci_cfg->cqi, &uci_data->cqi, cqi_str, SRSRAN_CQI_STR_MAX_CHAR);
|
|
|
|
n = srsran_print_check(str, str_len, n, "%s (cc=%d)", cqi_str, uci_cfg->cqi.scell_index);
|
2019-04-23 01:53:11 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return n;
|
|
|
|
}
|