sched,nr: update nr scheduler to use new mac nr interface types

This commit is contained in:
Francisco Paisana 2021-07-14 22:29:06 +01:00
parent 8a34a3c41a
commit 09c7000201
8 changed files with 24 additions and 16 deletions

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@ -214,9 +214,8 @@ public:
};
struct pdsch_t {
srsran_sch_cfg_nr_t sch = {}; ///< PDSCH configuration
std::array<uint8_t*, SRSRAN_MAX_TB> data = {}; ///< Data pointer
std::array<srsran_softbuffer_tx_t, SRSRAN_MAX_TB> tx_softbuffer = {}; ///< HARQ-specific Softbuffer
srsran_sch_cfg_nr_t sch = {}; ///< PDSCH configuration
std::array<uint8_t*, SRSRAN_MAX_TB> data = {}; ///< Data pointer
};
struct ssb_t {

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@ -62,7 +62,6 @@ public:
size_t nof_allocs() const { return dfs_tree.size(); }
private:
const bwp_params* bwp_cfg;
const srsran_coreset_t* coreset_cfg;
uint32_t coreset_id;
uint32_t slot_idx;

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@ -191,7 +191,6 @@ public:
private:
prb_bitmap prbs_;
rbg_bitmap rbgs_;
uint32_t bwp_prb_start = 0;
uint32_t P_ = 0;
uint32_t Pnofbits = 0;
uint32_t first_rbg_size = 0;

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@ -21,7 +21,6 @@ coreset_region::coreset_region(const bwp_params& bwp_cfg_,
uint32_t slot_idx_,
pdcch_dl_list_t& dl_list_,
pdcch_ul_list_t& ul_list_) :
bwp_cfg(&bwp_cfg_),
coreset_cfg(&bwp_cfg_.cfg.pdcch.coreset[coreset_id_]),
coreset_id(coreset_id_),
slot_idx(slot_idx_),

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@ -55,7 +55,6 @@ uint32_t get_rbg_size(uint32_t bwp_nof_prb, uint32_t bwp_start, bool config1_or_
bwp_rb_bitmap::bwp_rb_bitmap(uint32_t bwp_nof_prbs, uint32_t bwp_prb_start_, bool config1_or_2) :
prbs_(bwp_nof_prbs),
rbgs_(get_nof_rbgs(bwp_nof_prbs, bwp_prb_start_, config1_or_2)),
bwp_prb_start(bwp_prb_start_),
P_(get_P(bwp_nof_prbs, config1_or_2)),
Pnofbits(log2(P_)),
first_rbg_size(get_rbg_size(bwp_nof_prbs, bwp_prb_start_, config1_or_2, 0))

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@ -196,7 +196,7 @@ alloc_result bwp_slot_allocator::alloc_pdsch(slot_ue& ue, const prb_grant& dl_gr
} else {
srsran_assert(pdsch.sch.grant.tb[0].tbs == (int)ue.h_dl->tbs(), "The TBS did not remain constant in retx");
}
pdsch.tx_softbuffer[0] = *ue.h_dl->get_softbuffer();
pdsch.sch.grant.tb[0].softbuffer.tx = ue.h_dl->get_softbuffer().get();
return alloc_result::success;
}

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@ -232,7 +232,7 @@ bool sched_worker_manager::save_sched_result(tti_point pdcch_tti, uint32_t cc, d
dl_res.pdsch = bwp_slot.pdschs;
ul_res.pusch = bwp_slot.puschs;
// Generate PUCCH
// Group pending HARQ ACKs
srsran_pdsch_ack_nr_t ack = {};
ack.nof_cc = not bwp_slot.pending_acks.empty();
const srsran::phy_cfg_nr_t* phy_cfg = nullptr;
@ -246,11 +246,23 @@ bool sched_worker_manager::save_sched_result(tti_point pdcch_tti, uint32_t cc, d
if (phy_cfg != nullptr) {
srsran_slot_cfg_t slot_cfg{};
slot_cfg.idx = pdcch_tti.sf_idx();
ul_res.pucch.emplace_back();
pucch_t& pucch = ul_res.pucch.back();
if (not phy_cfg->get_pucch(slot_cfg, ack, pucch.pucch_cfg, pucch.uci_cfg, pucch.resource)) {
logger.error("Error getting UCI CFG");
slot_cfg.idx = pdcch_tti.sf_idx();
srsran_uci_cfg_nr_t uci_cfg = {};
srsran_assert(phy_cfg->get_uci_cfg(slot_cfg, ack, uci_cfg), "Error getting UCI CFG");
if (uci_cfg.ack.count > 0 || uci_cfg.nof_csi > 0 || uci_cfg.o_sr > 0) {
if (not ul_res.pusch.empty()) {
// Put UCI configuration in PUSCH config
srsran_assert(phy_cfg->get_pusch_uci_cfg(slot_cfg, uci_cfg, ul_res.pusch[0].sch),
"Error setting UCI configuration in PUSCH");
} else {
// Put UCI configuration in PUCCH config
ul_res.pucch.emplace_back();
pucch_t& pucch = ul_res.pucch.back();
pucch.uci_cfg = uci_cfg;
srsran_assert(phy_cfg->get_pucch_uci_cfg(slot_cfg, pucch.uci_cfg, pucch.pucch_cfg, pucch.resource),
"Error getting PUCCH UCI cfg");
}
}
}

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@ -52,8 +52,9 @@ void test_dl_sched_result(const sim_nr_enb_ctxt_t& enb_ctxt, const sched_nr_cc_o
}
for (const pdsch_t& pdsch : pdschs) {
TESTASSERT(pdsch.tx_softbuffer[0].buffer_b != nullptr);
TESTASSERT(pdsch.tx_softbuffer[0].max_cb > 0);
TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx != nullptr);
TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx->buffer_b != nullptr);
TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx->max_cb > 0);
}
}