mirror of https://github.com/PentHertz/srsLTE.git
nr,gnb,sched: fix si softbuffer allocation. Add extra comments
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360f718a5e
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1807ba1e37
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@ -54,8 +54,6 @@ struct bwp_slot_grid {
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slot_coreset_list coresets;
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slot_coreset_list coresets;
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harq_ack_list_t pending_acks;
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harq_ack_list_t pending_acks;
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srsran::bounded_vector<uint32_t, MAX_GRANTS> sib_idxs;
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srsran::unique_pool_ptr<tx_harq_softbuffer> rar_softbuffer;
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srsran::unique_pool_ptr<tx_harq_softbuffer> rar_softbuffer;
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bwp_slot_grid() = default;
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bwp_slot_grid() = default;
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@ -92,7 +90,11 @@ class bwp_slot_allocator
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public:
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public:
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explicit bwp_slot_allocator(bwp_res_grid& bwp_grid_, slot_point pdcch_slot_, slot_ue_map_t& ues_);
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explicit bwp_slot_allocator(bwp_res_grid& bwp_grid_, slot_point pdcch_slot_, slot_ue_map_t& ues_);
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alloc_result alloc_si(uint32_t aggr_idx, uint32_t si_idx, uint32_t si_ntx, const prb_interval& prbs);
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alloc_result alloc_si(uint32_t aggr_idx,
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uint32_t si_idx,
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uint32_t si_ntx,
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const prb_interval& prbs,
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tx_harq_softbuffer& softbuffer);
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alloc_result alloc_rar_and_msg3(uint16_t ra_rnti,
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alloc_result alloc_rar_and_msg3(uint16_t ra_rnti,
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uint32_t aggr_idx,
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uint32_t aggr_idx,
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prb_interval interv,
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prb_interval interv,
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@ -25,7 +25,11 @@ struct bwp_res_grid;
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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bool fill_dci_sib(prb_interval interv, uint32_t sib_idx, const bwp_params_t& bwp_cfg, srsran_dci_dl_nr_t& dci);
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bool fill_dci_sib(prb_interval interv,
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uint32_t sib_idx,
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uint32_t si_ntx,
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const bwp_params_t& bwp_cfg,
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srsran_dci_dl_nr_t& dci);
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bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params_t& bwp_cfg, srsran_dci_dl_nr_t& dci);
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bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params_t& bwp_cfg, srsran_dci_dl_nr_t& dci);
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@ -13,6 +13,7 @@
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#ifndef SRSRAN_SCHED_NR_SIGNALLING_H
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#ifndef SRSRAN_SCHED_NR_SIGNALLING_H
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#define SRSRAN_SCHED_NR_SIGNALLING_H
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#define SRSRAN_SCHED_NR_SIGNALLING_H
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#include "harq_softbuffer.h"
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#include "sched_nr_cfg.h"
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#include "sched_nr_cfg.h"
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#include "sched_nr_interface.h"
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#include "sched_nr_interface.h"
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#include "srsenb/hdr/stack/mac/sched_common.h"
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#include "srsenb/hdr/stack/mac/sched_common.h"
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@ -63,13 +64,17 @@ private:
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srslog::basic_logger& logger;
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srslog::basic_logger& logger;
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struct si_msg_ctxt_t {
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struct si_msg_ctxt_t {
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uint32_t n = 0; /// 0 for SIB1, n/index in schedulingInfoList in si-SchedulingInfo in SIB1
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// args
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uint32_t len = 0;
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uint32_t n = 0; /// 0 for SIB1, n/index in schedulingInfoList in si-SchedulingInfo in SIB1
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uint32_t win_len = 0;
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uint32_t len = 0; /// length in bytes of SIB1 / SI message
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uint32_t period = 0;
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uint32_t win_len = 0; /// window length in slots
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uint32_t n_tx = 0;
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uint32_t period = 0; /// periodicity of SIB1/SI window
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alloc_result result = alloc_result::invalid_coderate; /// last attempt to schedule SI
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slot_point win_start; /// start of SI window, invalid if outside
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// state
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uint32_t n_tx = 0; /// nof transmissions of the same SIB1 / SI message
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alloc_result result = alloc_result::invalid_coderate; /// last attempt to schedule SI
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slot_point win_start; /// start of SI window, invalid if outside
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srsran::unique_pool_ptr<tx_harq_softbuffer> si_softbuffer;
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};
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};
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srsran::bounded_vector<si_msg_ctxt_t, 10> pending_sis; /// configured SIB1 and SI messages
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srsran::bounded_vector<si_msg_ctxt_t, 10> pending_sis; /// configured SIB1 and SI messages
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};
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};
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@ -66,7 +66,11 @@ bwp_slot_allocator::bwp_slot_allocator(bwp_res_grid& bwp_grid_, slot_point pdcch
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logger(bwp_grid_.cfg->logger), cfg(*bwp_grid_.cfg), bwp_grid(bwp_grid_), pdcch_slot(pdcch_slot_), slot_ues(ues_)
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logger(bwp_grid_.cfg->logger), cfg(*bwp_grid_.cfg), bwp_grid(bwp_grid_), pdcch_slot(pdcch_slot_), slot_ues(ues_)
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{}
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{}
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alloc_result bwp_slot_allocator::alloc_si(uint32_t aggr_idx, uint32_t si_idx, uint32_t si_ntx, const prb_interval& prbs)
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alloc_result bwp_slot_allocator::alloc_si(uint32_t aggr_idx,
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uint32_t si_idx,
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uint32_t si_ntx,
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const prb_interval& prbs,
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tx_harq_softbuffer& softbuffer)
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{
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{
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bwp_slot_grid& bwp_pdcch_slot = bwp_grid[pdcch_slot];
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bwp_slot_grid& bwp_pdcch_slot = bwp_grid[pdcch_slot];
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alloc_result ret = verify_pdsch_space(bwp_pdcch_slot, bwp_pdcch_slot);
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alloc_result ret = verify_pdsch_space(bwp_pdcch_slot, bwp_pdcch_slot);
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@ -88,7 +92,7 @@ alloc_result bwp_slot_allocator::alloc_si(uint32_t aggr_idx, uint32_t si_idx, ui
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bwp_pdcch_slot.dl_prbs |= prbs;
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bwp_pdcch_slot.dl_prbs |= prbs;
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// Generate DCI for RAR with given RA-RNTI
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// Generate DCI for RAR with given RA-RNTI
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pdcch_dl_t& pdcch = bwp_pdcch_slot.dl.phy.pdcch_dl.back();
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pdcch_dl_t& pdcch = bwp_pdcch_slot.dl.phy.pdcch_dl.back();
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if (not fill_dci_sib(prbs, si_idx, *bwp_grid.cfg, pdcch.dci)) {
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if (not fill_dci_sib(prbs, si_idx, si_ntx, *bwp_grid.cfg, pdcch.dci)) {
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// Cancel on-going PDCCH allocation
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// Cancel on-going PDCCH allocation
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bwp_pdcch_slot.coresets[coreset_id]->rem_last_dci();
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bwp_pdcch_slot.coresets[coreset_id]->rem_last_dci();
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return alloc_result::invalid_coderate;
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return alloc_result::invalid_coderate;
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@ -107,9 +111,10 @@ alloc_result bwp_slot_allocator::alloc_si(uint32_t aggr_idx, uint32_t si_idx, ui
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bwp_pdcch_slot.dl.phy.pdsch.pop_back();
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bwp_pdcch_slot.dl.phy.pdsch.pop_back();
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return alloc_result::other_cause;
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return alloc_result::other_cause;
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}
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}
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pdsch.sch.grant.tb[0].softbuffer.tx = softbuffer.get();
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// Store SI msg index
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// Store SI msg index
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bwp_pdcch_slot.sib_idxs.push_back(si_idx);
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bwp_pdcch_slot.dl.sib_idxs.push_back(si_idx);
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return alloc_result::success;
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return alloc_result::success;
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}
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}
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@ -103,7 +103,11 @@ void sched_dl_signalling(bwp_slot_allocator& bwp_alloc)
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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bool fill_dci_sib(prb_interval interv, uint32_t sib_id, const bwp_params_t& bwp_cfg, srsran_dci_dl_nr_t& dci)
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bool fill_dci_sib(prb_interval interv,
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uint32_t sib_id,
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uint32_t si_ntx,
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const bwp_params_t& bwp_cfg,
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srsran_dci_dl_nr_t& dci)
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{
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{
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dci.mcs = 5;
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dci.mcs = 5;
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dci.ctx.format = srsran_dci_format_nr_1_0;
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dci.ctx.format = srsran_dci_format_nr_1_0;
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@ -117,7 +121,7 @@ bool fill_dci_sib(prb_interval interv, uint32_t sib_id, const bwp_params_t& bwp_
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dci.bwp_id = bwp_cfg.bwp_id;
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dci.bwp_id = bwp_cfg.bwp_id;
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dci.cc_id = bwp_cfg.cc;
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dci.cc_id = bwp_cfg.cc;
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dci.rv = 0;
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dci.rv = 0;
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dci.sii = sib_id == 1 ? 0 : 1;
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dci.sii = sib_id == 0 ? 0 : 1;
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return true;
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return true;
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}
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}
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@ -127,10 +131,11 @@ si_sched::si_sched(const bwp_params_t& bwp_cfg_) :
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{
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{
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// TODO: Get SIB1 other SI msgs config from RRC
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// TODO: Get SIB1 other SI msgs config from RRC
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pending_sis.emplace_back();
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pending_sis.emplace_back();
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pending_sis[0].n = 0;
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pending_sis[0].n = 0;
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pending_sis[0].len = 77;
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pending_sis[0].len = 77;
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pending_sis[0].period = 160;
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pending_sis[0].period = 160;
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pending_sis[0].win_len = 160;
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pending_sis[0].win_len = 160;
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pending_sis[0].si_softbuffer = harq_softbuffer_pool::get_instance().get_tx(bwp_cfg->nof_prb());
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}
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}
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void si_sched::run_slot(bwp_slot_allocator& bwp_alloc)
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void si_sched::run_slot(bwp_slot_allocator& bwp_alloc)
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@ -152,10 +157,10 @@ void si_sched::run_slot(bwp_slot_allocator& bwp_alloc)
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if (not si.win_start.valid()) {
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if (not si.win_start.valid()) {
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bool start_window;
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bool start_window;
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if (si.n == 0) {
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if (si.n == 0) {
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// SIB1
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// SIB1 (slot index zero of even frames)
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start_window = sl_pdcch.slot_idx() == 0 and sl_pdcch.sfn() % 2 == 0;
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start_window = sl_pdcch.slot_idx() == 0 and sl_pdcch.sfn() % 2 == 0;
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} else {
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} else {
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// SI messages
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// 5.2.2.3.2 - Acquisition of SI message
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start_window = (sl_pdcch.sfn() % si.period == x / N) and sl_pdcch.slot_idx() == x % bwp_cfg->slots.size();
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start_window = (sl_pdcch.sfn() % si.period == x / N) and sl_pdcch.slot_idx() == x % bwp_cfg->slots.size();
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}
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}
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if (start_window) {
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if (start_window) {
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@ -194,7 +199,7 @@ void si_sched::run_slot(bwp_slot_allocator& bwp_alloc)
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si.result = alloc_result::no_sch_space;
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si.result = alloc_result::no_sch_space;
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break;
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break;
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}
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}
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si.result = bwp_alloc.alloc_si(si_aggr_level, si.n, si.n_tx, grant);
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si.result = bwp_alloc.alloc_si(si_aggr_level, si.n, si.n_tx, grant, *si.si_softbuffer.get());
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if (si.result == alloc_result::success) {
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if (si.result == alloc_result::success) {
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// SIB scheduled successfully
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// SIB scheduled successfully
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si.win_start.clear();
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si.win_start.clear();
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