From 2fbd172888c0e46c7ef2ba13db639f22d3a6618b Mon Sep 17 00:00:00 2001 From: Xavier Arteaga Date: Wed, 30 Jun 2021 17:12:17 +0200 Subject: [PATCH] Initial PHY NR configuration generator --- lib/include/srsran/common/phy_cfg_nr.h | 19 -- .../srsran/common/phy_cfg_nr_default.h | 146 ++++++++++++ lib/src/common/CMakeLists.txt | 1 + lib/src/common/phy_cfg_nr_default.cc | 221 ++++++++++++++++++ test/phy/nr_dl_flood.cc | 197 +--------------- 5 files changed, 372 insertions(+), 212 deletions(-) create mode 100644 lib/include/srsran/common/phy_cfg_nr_default.h create mode 100644 lib/src/common/phy_cfg_nr_default.cc diff --git a/lib/include/srsran/common/phy_cfg_nr.h b/lib/include/srsran/common/phy_cfg_nr.h index 644614ed5..b37e6291d 100644 --- a/lib/include/srsran/common/phy_cfg_nr.h +++ b/lib/include/srsran/common/phy_cfg_nr.h @@ -134,25 +134,6 @@ struct phy_cfg_nr_t { srsran_pucch_nr_resource_t& resource) const; }; -struct phy_cfg_nr_default_t : public phy_cfg_nr_t { - /** - * @brief DL reference configurations defined in TS 38.101-4 User Equipment (UE) radio transmission and reception; - * Part 4: Performance requirements - */ - typedef enum { - R_PDSCH_2_1_1 = 0, // R.PDSCH.2-1.1 TDD - } dl_reference_t; - - /** - * @brief UL reference configurations defined in TS 38.104 Base Station (BS) radio transmission and reception - */ - typedef enum { - G_FR1_A3_8 = 0, // G-FR1-A3-8 - } ul_reference_t; - - phy_cfg_nr_default_t(const dl_reference_t& dl_reference, const ul_reference_t& ul_reference); -}; - } // namespace srsran #endif // SRSRAN_PHY_CFG_NR_H diff --git a/lib/include/srsran/common/phy_cfg_nr_default.h b/lib/include/srsran/common/phy_cfg_nr_default.h new file mode 100644 index 000000000..ee781f79a --- /dev/null +++ b/lib/include/srsran/common/phy_cfg_nr_default.h @@ -0,0 +1,146 @@ +/** + * + * \section COPYRIGHT + * + * Copyright 2013-2021 Software Radio Systems Limited + * + * By using this file, you agree to the terms and conditions set + * forth in the LICENSE file which can be found at the top level of + * the distribution. + * + */ + +#ifndef SRSRAN_PHY_CFG_NR_DEFAULT_H +#define SRSRAN_PHY_CFG_NR_DEFAULT_H + +#include "phy_cfg_nr.h" + +namespace srsran { + +class phy_cfg_nr_default_t : public phy_cfg_nr_t +{ +public: + struct reference_cfg_t { + enum { + /** + * @brief Carrier reference configuration for 10MHz serving cell bandwidth + * - BW: 10 MHZ (52 PRB) + * - PCI: 500 + * - SCS: 15 kHz + * - SSB: 5ms + */ + R_CARRIER_CUSTOM_10MHZ = 0, + } carrier = R_CARRIER_CUSTOM_10MHZ; + + enum { + /** + * @brief TDD custom reference 5 slot DL and 5 slot UL + */ + R_TDD_CUSTOM_6_4 = 0, + } tdd = R_TDD_CUSTOM_6_4; + + enum { + /** + * @brief Carrier reference configuration for 10MHz serving cell bandwidth + * - CORESET: all channel, 1 symbol + * - Single common Search Space + */ + R_PDCCH_CUSTOM_COMMON_SS = 0, + } pdcch = R_PDCCH_CUSTOM_COMMON_SS; + + enum { + /** + * @brief Custom fallback baseline configuration, designed for component testing + * - Defined single common PDSCH time allocation starting at symbol index 1 and length 13 + * - No DMRS dedicated configuration + */ + R_PDSCH_DEFAULT = 0, + } pdsch = R_PDSCH_DEFAULT; + + enum { + /** + * @brief Custom fallback baseline configuration, designed for component testing + * - Single Time resource allocation + * - transmission starts at symbol index 0 for 14 symbols + * - k is 4 slots + * - No DMRS dedicated configuration + */ + R_PUSCH_DEFAULT = 0, + } pusch = R_PUSCH_DEFAULT; + + enum { + /** + * @brief Custom single PUCCH resource per set + * - Format 1 for 1 or 2 bits + * - Format 2 for more than 2 bits + */ + R_PUCCH_CUSTOM_ONE = 0, + } pucch = R_PUCCH_CUSTOM_ONE; + + enum { + /** + * @brief Sets the delay between PDSCH and HARQ feedback timing automatically + * - Dynamic HARQ ACK codebook + * - Guarantees a minimum delay of 4ms + */ + R_HARQ_AUTO = 0, + } harq = R_HARQ_AUTO; + + enum { + /** + * @brief Sets the PRACH configuration to an LTE compatible configuration + * - Configuration index 0 + * - Frequency offset 2 PRB + * - Root sequence 2 + */ + R_PRACH_DEFAULT_LTE, + } prach = R_PRACH_DEFAULT_LTE; + }; + + phy_cfg_nr_default_t(const reference_cfg_t& reference_cfg); + +private: + /** + * Carrier make helper methods + */ + static void make_carrier_custom_10MHz(srsran_carrier_nr_t& carrier); + + /** + * TDD make helper methods + */ + static void make_tdd_custom_6_4(srsran_tdd_config_nr_t& tdd); + + /** + * PDCCH make helper methods + */ + static void make_pdcch_custom_common_ss(srsran_pdcch_cfg_nr_t& pdcch, const srsran_carrier_nr_t& carrier); + + /** + * PDSCH make helper methods + */ + static void make_pdsch_default(srsran_sch_hl_cfg_nr_t& pdsch); + + /** + * PUSCH make helper methods + */ + static void make_pusch_default(srsran_sch_hl_cfg_nr_t& pusch); + + /** + * PUCCH make helper methods + */ + static void make_pucch_custom_one(srsran_pucch_nr_hl_cfg_t& pucch); + + /** + * HARQ make helper methods + */ + static void make_harq_auto(srsran_harq_ack_cfg_hl_t& harq, const srsran_tdd_config_nr_t& tdd_cfg); + + /** + * PRACH make helper methods + */ + static void make_prach_default_lte(srsran_prach_cfg_t& prach); +}; + +} // namespace srsran + +#endif // SRSRAN_PHY_CFG_NR_DEFAULT_H diff --git a/lib/src/common/CMakeLists.txt b/lib/src/common/CMakeLists.txt index 498d7d504..8c0f15aa0 100644 --- a/lib/src/common/CMakeLists.txt +++ b/lib/src/common/CMakeLists.txt @@ -23,6 +23,7 @@ set(SOURCES arch_select.cc mac_pcap_net.cc pcap.c phy_cfg_nr.cc + phy_cfg_nr_default.cc rlc_pcap.cc s1ap_pcap.cc security.cc diff --git a/lib/src/common/phy_cfg_nr_default.cc b/lib/src/common/phy_cfg_nr_default.cc new file mode 100644 index 000000000..4acf90b9c --- /dev/null +++ b/lib/src/common/phy_cfg_nr_default.cc @@ -0,0 +1,221 @@ +/** + * + * \section COPYRIGHT + * + * Copyright 2013-2021 Software Radio Systems Limited + * + * By using this file, you agree to the terms and conditions set + * forth in the LICENSE file which can be found at the top level of + * the distribution. + * + */ + +#include "srsran/common/phy_cfg_nr_default.h" +#include "srsran/srsran.h" + +namespace srsran { + +void phy_cfg_nr_default_t::make_carrier_custom_10MHz(srsran_carrier_nr_t& carrier) +{ + carrier.nof_prb = 52; + carrier.max_mimo_layers = 1; + carrier.pci = 500; + carrier.absolute_frequency_point_a = 633928; + carrier.absolute_frequency_ssb = 634176; + carrier.offset_to_carrier = 0; + carrier.scs = srsran_subcarrier_spacing_15kHz; +} + +void phy_cfg_nr_default_t::make_tdd_custom_6_4(srsran_tdd_config_nr_t& tdd) +{ + tdd.pattern1.period_ms = 10; + tdd.pattern1.nof_dl_slots = 6; + tdd.pattern1.nof_dl_symbols = 0; + tdd.pattern1.nof_ul_slots = 4; + tdd.pattern1.nof_ul_symbols = 0; + + // Disable pattern 2 + tdd.pattern2.period_ms = 0; +} + +void phy_cfg_nr_default_t::make_pdcch_custom_common_ss(srsran_pdcch_cfg_nr_t& pdcch, const srsran_carrier_nr_t& carrier) +{ + pdcch.coreset_present[1] = true; + pdcch.coreset[1].id = 1; + for (uint32_t i = 0; i < SRSRAN_CORESET_FREQ_DOMAIN_RES_SIZE; i++) { + pdcch.coreset[1].freq_resources[0] = i < SRSRAN_FLOOR(carrier.nof_prb, 6); + } + pdcch.coreset[1].duration = 1; + pdcch.coreset[1].mapping_type = srsran_coreset_mapping_type_non_interleaved; + pdcch.coreset[1].precoder_granularity = srsran_coreset_precoder_granularity_reg_bundle; + + pdcch.search_space_present[1] = true; + pdcch.search_space[1].id = 1; + pdcch.search_space[1].coreset_id = 1; + pdcch.search_space[1].duration = 1; + pdcch.search_space[1].nof_candidates[0] = 0; + pdcch.search_space[1].nof_candidates[1] = 0; + pdcch.search_space[1].nof_candidates[2] = 0; + pdcch.search_space[1].nof_candidates[3] = 1; + pdcch.search_space[1].nof_candidates[4] = 0; + pdcch.search_space[1].formats[0] = srsran_dci_format_nr_0_0; // DCI format for PUSCH + pdcch.search_space[1].formats[1] = srsran_dci_format_nr_1_0; // DCI format for PDSCH + pdcch.search_space[1].nof_formats = 2; + pdcch.search_space[1].type = srsran_search_space_type_common_3; +} + +void phy_cfg_nr_default_t::make_pdsch_default(srsran_sch_hl_cfg_nr_t& pdsch) +{ + // Select PDSCH time resource allocation + pdsch.common_time_ra[0].k = 0; + pdsch.common_time_ra[0].mapping_type = srsran_sch_mapping_type_A; + pdsch.common_time_ra[0].sliv = srsran_ra_type2_to_riv(SRSRAN_NSYMB_PER_SLOT_NR - 1, 1, SRSRAN_NSYMB_PER_SLOT_NR); + pdsch.nof_common_time_ra = 1; + + // Setup PDSCH DMRS type A position + pdsch.typeA_pos = srsran_dmrs_sch_typeA_pos_2; +} + +void phy_cfg_nr_default_t::make_pusch_default(srsran_sch_hl_cfg_nr_t& pusch) +{ + // Select PUSCH time resource allocation + pusch.common_time_ra[0].k = 4; + pusch.common_time_ra[0].mapping_type = srsran_sch_mapping_type_A; + pusch.common_time_ra[0].sliv = srsran_ra_type2_to_riv(SRSRAN_NSYMB_PER_SLOT_NR, 0, SRSRAN_NSYMB_PER_SLOT_NR); + pusch.nof_common_time_ra = 1; + + // Setup PUSCH DMRS type A position + pusch.typeA_pos = srsran_dmrs_sch_typeA_pos_2; +} + +void phy_cfg_nr_default_t::make_pucch_custom_one(srsran_pucch_nr_hl_cfg_t& pucch) +{ + // PUCCH Resource for format 1 + srsran_pucch_nr_resource_t resource_small = {}; + resource_small.starting_prb = 0; + resource_small.format = SRSRAN_PUCCH_NR_FORMAT_1; + resource_small.initial_cyclic_shift = 0; + resource_small.nof_symbols = 14; + resource_small.start_symbol_idx = 0; + resource_small.time_domain_occ = 0; + + // PUCCH Resource for format 2 + srsran_pucch_nr_resource_t resource_big = {}; + resource_big.starting_prb = 51; + resource_big.format = SRSRAN_PUCCH_NR_FORMAT_2; + resource_big.nof_prb = 1; + resource_big.nof_symbols = 2; + resource_big.start_symbol_idx = 0; + + // Resource for SR + srsran_pucch_nr_resource_t resource_sr = {}; + resource_sr.starting_prb = 51; + resource_sr.format = SRSRAN_PUCCH_NR_FORMAT_1; + resource_sr.initial_cyclic_shift = 0; + resource_sr.nof_symbols = 14; + resource_sr.start_symbol_idx = 0; + resource_sr.time_domain_occ = 0; + + pucch.enabled = true; + + // Set format 1 for 1-2 bits + pucch.sets[0].resources[0] = resource_small; + pucch.sets[0].resources[1] = resource_small; + pucch.sets[0].resources[2] = resource_small; + pucch.sets[0].resources[3] = resource_small; + pucch.sets[0].resources[4] = resource_small; + pucch.sets[0].resources[5] = resource_small; + pucch.sets[0].resources[6] = resource_small; + pucch.sets[0].resources[7] = resource_small; + pucch.sets[0].nof_resources = 8; + + // Set format 2 for more bits + pucch.sets[1].resources[0] = resource_big; + pucch.sets[1].resources[1] = resource_big; + pucch.sets[1].resources[2] = resource_big; + pucch.sets[1].resources[3] = resource_big; + pucch.sets[1].resources[4] = resource_big; + pucch.sets[1].resources[5] = resource_big; + pucch.sets[1].resources[6] = resource_big; + pucch.sets[1].resources[7] = resource_big; + pucch.sets[1].nof_resources = 8; + + // Configure scheduling request + pucch.sr_resources[1].configured = true; + pucch.sr_resources[1].sr_id = 0; + pucch.sr_resources[1].period = 40; + pucch.sr_resources[1].offset = 8; + pucch.sr_resources[1].resource = resource_sr; +} + +void phy_cfg_nr_default_t::make_harq_auto(srsran_harq_ack_cfg_hl_t& harq, const srsran_tdd_config_nr_t& tdd_cfg) +{ + harq.nof_dl_data_to_ul_ack = SRSRAN_MAX(tdd_cfg.pattern1.nof_dl_slots, SRSRAN_MAX_NOF_DL_DATA_TO_UL); + for (uint32_t i = 0; i < harq.nof_dl_data_to_ul_ack; i++) { + harq.dl_data_to_ul_ack[i] = ((harq.nof_dl_data_to_ul_ack - 4) > i) ? (harq.nof_dl_data_to_ul_ack - i) : 4; + } + + for (uint32_t i = harq.nof_dl_data_to_ul_ack; i < SRSRAN_MAX_NOF_DL_DATA_TO_UL; i++) { + harq.dl_data_to_ul_ack[i] = 0; + } +} + +void phy_cfg_nr_default_t::make_prach_default_lte(srsran_prach_cfg_t& prach) +{ + prach.config_idx = 0; + prach.freq_offset = 2; + prach.root_seq_idx = 0; +} + +phy_cfg_nr_default_t::phy_cfg_nr_default_t(const reference_cfg_t& reference_cfg) +{ + switch (reference_cfg.carrier) { + case reference_cfg_t::R_CARRIER_CUSTOM_10MHZ: + make_carrier_custom_10MHz(carrier); + break; + } + + switch (reference_cfg.tdd) { + case reference_cfg_t::R_TDD_CUSTOM_6_4: + make_tdd_custom_6_4(tdd); + break; + } + + switch (reference_cfg.pdcch) { + case reference_cfg_t::R_PDCCH_CUSTOM_COMMON_SS: + make_pdcch_custom_common_ss(pdcch, carrier); + break; + } + + switch (reference_cfg.pdsch) { + case reference_cfg_t::R_PDSCH_DEFAULT: + make_pdsch_default(pdsch); + break; + } + + switch (reference_cfg.pusch) { + case reference_cfg_t::R_PUSCH_DEFAULT: + make_pusch_default(pusch); + break; + } + + switch (reference_cfg.pucch) { + case reference_cfg_t::R_PUCCH_CUSTOM_ONE: + make_pusch_default(pusch); + break; + } + + switch (reference_cfg.harq) { + case reference_cfg_t::R_HARQ_AUTO: + make_harq_auto(harq_ack, tdd); + break; + } + + switch (reference_cfg.prach) { + case reference_cfg_t::R_PRACH_DEFAULT_LTE: + make_prach_default_lte(prach); + break; + } +} + +} // namespace srsran \ No newline at end of file diff --git a/test/phy/nr_dl_flood.cc b/test/phy/nr_dl_flood.cc index 56bb8e87f..5476c93d0 100644 --- a/test/phy/nr_dl_flood.cc +++ b/test/phy/nr_dl_flood.cc @@ -11,6 +11,7 @@ */ #include "dummy_gnb_stack.h" +#include "srsran/common/phy_cfg_nr_default.h" #include "srsran/common/test_common.h" #include "test_bench.h" @@ -19,199 +20,9 @@ test_bench::args_t::args_t(int argc, char** argv) // Flag configuration as valid valid = true; - phy_cfg.carrier.nof_prb = 52; - phy_cfg.carrier.max_mimo_layers = 1; - phy_cfg.carrier.pci = 500; - phy_cfg.carrier.absolute_frequency_point_a = 633928; - phy_cfg.carrier.absolute_frequency_ssb = 634176; - phy_cfg.carrier.offset_to_carrier = 0; - phy_cfg.carrier.scs = srsran_subcarrier_spacing_15kHz; - - phy_cfg.ssb.periodicity_ms = 5; - phy_cfg.ssb.position_in_burst[0] = true; - phy_cfg.ssb.scs = srsran_subcarrier_spacing_30kHz; - - phy_cfg.pdcch.coreset_present[1] = true; - phy_cfg.pdcch.coreset[1].id = 1; - phy_cfg.pdcch.coreset[1].freq_resources[0] = true; - phy_cfg.pdcch.coreset[1].freq_resources[1] = true; - phy_cfg.pdcch.coreset[1].freq_resources[2] = true; - phy_cfg.pdcch.coreset[1].freq_resources[3] = true; - phy_cfg.pdcch.coreset[1].freq_resources[4] = true; - phy_cfg.pdcch.coreset[1].freq_resources[5] = true; - phy_cfg.pdcch.coreset[1].freq_resources[6] = true; - phy_cfg.pdcch.coreset[1].freq_resources[7] = true; - phy_cfg.pdcch.coreset[1].duration = 1; - phy_cfg.pdcch.coreset[1].mapping_type = srsran_coreset_mapping_type_non_interleaved; - phy_cfg.pdcch.coreset[1].precoder_granularity = srsran_coreset_precoder_granularity_reg_bundle; - phy_cfg.pdcch.coreset_present[2] = true; - phy_cfg.pdcch.coreset[2].id = 2; - phy_cfg.pdcch.coreset[2].freq_resources[0] = true; - phy_cfg.pdcch.coreset[2].freq_resources[1] = true; - phy_cfg.pdcch.coreset[2].freq_resources[2] = true; - phy_cfg.pdcch.coreset[2].freq_resources[3] = true; - phy_cfg.pdcch.coreset[2].freq_resources[4] = true; - phy_cfg.pdcch.coreset[2].freq_resources[5] = true; - phy_cfg.pdcch.coreset[2].freq_resources[6] = true; - phy_cfg.pdcch.coreset[2].freq_resources[7] = true; - phy_cfg.pdcch.coreset[2].duration = 1; - phy_cfg.pdcch.coreset[2].mapping_type = srsran_coreset_mapping_type_non_interleaved; - phy_cfg.pdcch.coreset[2].precoder_granularity = srsran_coreset_precoder_granularity_reg_bundle; - - phy_cfg.pdcch.search_space_present[1] = true; - phy_cfg.pdcch.search_space[1].id = 1; - phy_cfg.pdcch.search_space[1].coreset_id = 1; - phy_cfg.pdcch.search_space[1].duration = 1; - phy_cfg.pdcch.search_space[1].nof_candidates[0] = 1; - phy_cfg.pdcch.search_space[1].nof_candidates[1] = 1; - phy_cfg.pdcch.search_space[1].nof_candidates[2] = 1; - phy_cfg.pdcch.search_space[1].nof_candidates[3] = 0; - phy_cfg.pdcch.search_space[1].nof_candidates[4] = 0; - phy_cfg.pdcch.search_space[1].formats[0] = srsran_dci_format_nr_0_0; // DCI format for PUSCH - phy_cfg.pdcch.search_space[1].formats[1] = srsran_dci_format_nr_1_0; // DCI format for PDSCH - phy_cfg.pdcch.search_space[1].nof_formats = 2; - phy_cfg.pdcch.search_space[1].type = srsran_search_space_type_common_3; - - phy_cfg.pdcch.search_space_present[2] = true; - phy_cfg.pdcch.search_space[2].id = 2; - phy_cfg.pdcch.search_space[2].coreset_id = 2; - phy_cfg.pdcch.search_space[2].duration = 1; - phy_cfg.pdcch.search_space[2].nof_candidates[0] = 0; - phy_cfg.pdcch.search_space[2].nof_candidates[1] = 2; - phy_cfg.pdcch.search_space[2].nof_candidates[2] = 1; - phy_cfg.pdcch.search_space[2].nof_candidates[3] = 0; - phy_cfg.pdcch.search_space[2].nof_candidates[4] = 0; - phy_cfg.pdcch.search_space[2].formats[0] = srsran_dci_format_nr_0_1; - phy_cfg.pdcch.search_space[2].formats[1] = srsran_dci_format_nr_1_1; - phy_cfg.pdcch.search_space[2].nof_formats = 2; - phy_cfg.pdcch.search_space[2].type = srsran_search_space_type_ue; - - phy_cfg.pdcch.ra_search_space_present = true; - phy_cfg.pdcch.ra_search_space = phy_cfg.pdcch.search_space[1]; - phy_cfg.pdcch.ra_search_space.type = srsran_search_space_type_common_1; - - phy_cfg.pdsch.common_time_ra[0].mapping_type = srsran_sch_mapping_type_A; - phy_cfg.pdsch.common_time_ra[0].sliv = 40; - phy_cfg.pdsch.common_time_ra[1].mapping_type = srsran_sch_mapping_type_A; - phy_cfg.pdsch.common_time_ra[1].sliv = 57; - phy_cfg.pdsch.nof_common_time_ra = 2; - - phy_cfg.pusch.common_time_ra[0].k = 4; - phy_cfg.pusch.common_time_ra[0].mapping_type = srsran_sch_mapping_type_A; - phy_cfg.pusch.common_time_ra[0].sliv = 27; - phy_cfg.pusch.common_time_ra[1].k = 5; - phy_cfg.pusch.common_time_ra[1].mapping_type = srsran_sch_mapping_type_A; - phy_cfg.pusch.common_time_ra[1].sliv = 27; - phy_cfg.pusch.nof_common_time_ra = 2; - - phy_cfg.pdsch.typeA_pos = srsran_dmrs_sch_typeA_pos_2; - phy_cfg.pusch.typeA_pos = srsran_dmrs_sch_typeA_pos_2; - - phy_cfg.tdd.pattern1.period_ms = 10; - phy_cfg.tdd.pattern1.nof_dl_slots = 5; - phy_cfg.tdd.pattern1.nof_dl_symbols = 0; - phy_cfg.tdd.pattern1.nof_ul_slots = 5; - phy_cfg.tdd.pattern1.nof_ul_symbols = 0; - - phy_cfg.pdsch.dmrs_typeA.additional_pos = srsran_dmrs_sch_add_pos_1; - phy_cfg.pdsch.dmrs_typeA.present = true; - phy_cfg.pdsch.alloc = srsran_resource_alloc_type1; - - phy_cfg.pucch.enabled = true; - srsran_pucch_nr_resource_t& pucch0 = phy_cfg.pucch.sets[0].resources[0]; - srsran_pucch_nr_resource_t& pucch1 = phy_cfg.pucch.sets[0].resources[1]; - srsran_pucch_nr_resource_t& pucch2 = phy_cfg.pucch.sets[0].resources[2]; - srsran_pucch_nr_resource_t& pucch3 = phy_cfg.pucch.sets[0].resources[3]; - srsran_pucch_nr_resource_t& pucch4 = phy_cfg.pucch.sets[0].resources[4]; - srsran_pucch_nr_resource_t& pucch5 = phy_cfg.pucch.sets[0].resources[5]; - srsran_pucch_nr_resource_t& pucch6 = phy_cfg.pucch.sets[0].resources[6]; - srsran_pucch_nr_resource_t& pucch7 = phy_cfg.pucch.sets[0].resources[7]; - phy_cfg.pucch.sets[0].nof_resources = 8; - srsran_pucch_nr_resource_t& pucch8 = phy_cfg.pucch.sets[1].resources[0]; - srsran_pucch_nr_resource_t& pucch9 = phy_cfg.pucch.sets[1].resources[1]; - srsran_pucch_nr_resource_t& pucch10 = phy_cfg.pucch.sets[1].resources[2]; - srsran_pucch_nr_resource_t& pucch11 = phy_cfg.pucch.sets[1].resources[3]; - srsran_pucch_nr_resource_t& pucch12 = phy_cfg.pucch.sets[1].resources[4]; - srsran_pucch_nr_resource_t& pucch13 = phy_cfg.pucch.sets[1].resources[5]; - srsran_pucch_nr_resource_t& pucch14 = phy_cfg.pucch.sets[1].resources[6]; - srsran_pucch_nr_resource_t& pucch15 = phy_cfg.pucch.sets[1].resources[7]; - phy_cfg.pucch.sets[1].nof_resources = 8; - - pucch0.starting_prb = 0; - pucch0.format = SRSRAN_PUCCH_NR_FORMAT_1; - pucch0.initial_cyclic_shift = 0; - pucch0.nof_symbols = 14; - pucch0.start_symbol_idx = 0; - pucch0.time_domain_occ = 0; - pucch1 = pucch0; - pucch1.initial_cyclic_shift = 4; - pucch1.time_domain_occ = 0; - pucch2 = pucch0; - pucch2.initial_cyclic_shift = 8; - pucch2.time_domain_occ = 0; - pucch3 = pucch0; - pucch3.initial_cyclic_shift = 0; - pucch3.time_domain_occ = 1; - pucch4 = pucch0; - pucch4.initial_cyclic_shift = 0; - pucch4.time_domain_occ = 1; - pucch5 = pucch0; - pucch5.initial_cyclic_shift = 4; - pucch5.time_domain_occ = 1; - pucch6 = pucch0; - pucch6.initial_cyclic_shift = 0; - pucch6.time_domain_occ = 2; - pucch7 = pucch0; - pucch7.initial_cyclic_shift = 4; - pucch7.time_domain_occ = 2; - - pucch8.starting_prb = 51; - pucch8.format = SRSRAN_PUCCH_NR_FORMAT_2; - pucch8.nof_prb = 1; - pucch8.nof_symbols = 2; - pucch8.start_symbol_idx = 0; - - pucch9 = pucch8; - pucch9.start_symbol_idx = 2; - pucch10 = pucch8; - pucch10.start_symbol_idx = 4; - pucch11 = pucch8; - pucch11.start_symbol_idx = 6; - pucch12 = pucch8; - pucch12.start_symbol_idx = 8; - pucch13 = pucch8; - pucch13.start_symbol_idx = 10; - pucch14 = pucch8; - pucch14.start_symbol_idx = 12; - pucch15 = pucch8; - pucch15.starting_prb = 1; - pucch15.start_symbol_idx = 0; - - srsran_pucch_nr_resource_t& pucch16 = phy_cfg.pucch.sr_resources[1].resource; - pucch16.starting_prb = 0; - pucch16.format = SRSRAN_PUCCH_NR_FORMAT_1; - pucch16.initial_cyclic_shift = 8; - pucch16.nof_symbols = 14; - pucch16.start_symbol_idx = 0; - pucch16.time_domain_occ = 2; - - phy_cfg.pucch.sr_resources[1].configured = true; - phy_cfg.pucch.sr_resources[1].sr_id = 0; - phy_cfg.pucch.sr_resources[1].period = 40; - phy_cfg.pucch.sr_resources[1].offset = 8; - phy_cfg.pucch.sr_resources[1].resource = pucch16; - - phy_cfg.harq_ack.dl_data_to_ul_ack[0] = 8; - phy_cfg.harq_ack.dl_data_to_ul_ack[1] = 7; - phy_cfg.harq_ack.dl_data_to_ul_ack[2] = 6; - phy_cfg.harq_ack.dl_data_to_ul_ack[3] = 5; - phy_cfg.harq_ack.dl_data_to_ul_ack[4] = 4; - phy_cfg.harq_ack.dl_data_to_ul_ack[5] = 4; - phy_cfg.harq_ack.dl_data_to_ul_ack[6] = 4; - phy_cfg.harq_ack.dl_data_to_ul_ack[7] = 4; - phy_cfg.harq_ack.harq_ack_codebook = srsran_pdsch_harq_ack_codebook_dynamic; - - phy_cfg.prach.freq_offset = 2; + // Load default reference configuration + srsran::phy_cfg_nr_default_t::reference_cfg_t reference_cfg; + phy_cfg = srsran::phy_cfg_nr_default_t(reference_cfg); cell_list.resize(1); cell_list[0].carrier = phy_cfg.carrier;