PentHertz
/
srsLTE
mirror of https://github.com/PentHertz/srsLTE.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

sched,nr: remove phy cfg types from sched_nr_cell_cfg_t

This commit is contained in:
Francisco 2022-01-18 18:04:25 +00:00 committed by Francisco Paisana
parent b25814de27
commit 52106be3d5
20 changed files with 250 additions and 151 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/include/srsran/common/band_helper.h
View File

@ -80,7 +80,7 @@ public:
* @param scs SSB Subcarrier spacing
* @return The SSB pattern case if band and subcarrier spacing match, SRSRAN_SSB_PATTERN_INVALID otherwise
*/
srsran_ssb_patern_t get_ssb_pattern(uint16_t band, srsran_subcarrier_spacing_t scs) const;
static srsran_ssb_patern_t get_ssb_pattern(uint16_t band, srsran_subcarrier_spacing_t scs);
/**
* @brief Select the lower SSB subcarrier spacing valid for this band

2
lib/src/asn1/rrc_nr_utils.cc
View File

@ -1574,7 +1574,7 @@ bool make_phy_mib(const asn1::rrc_nr::mib_s& mib_cfg, srsran_mib_nr_t* mib)
{
mib->sfn = 0;
mib->ssb_idx = 0;
mib->hrf = 0;
mib->hrf = false;
mib->scs_common =
mib_cfg.sub_carrier_spacing_common.value == asn1::rrc_nr::mib_s::sub_carrier_spacing_common_opts::scs15or60
? srsran_subcarrier_spacing_15kHz

2
lib/src/common/band_helper.cc
View File

@ -166,7 +166,7 @@ uint32_t srsran_band_helper::get_abs_freq_ssb_arfcn(uint16_t
return find_lower_bound_abs_freq_ssb(band, scs, freq_point_a_hz + coreset0_offset_hz);
}
srsran_ssb_patern_t srsran_band_helper::get_ssb_pattern(uint16_t band, srsran_subcarrier_spacing_t scs) const
srsran_ssb_patern_t srsran_band_helper::get_ssb_pattern(uint16_t band, srsran_subcarrier_spacing_t scs)
{
// Look for the given band and SCS
for (const nr_band_ss_raster& ss_raster : nr_band_ss_raster_table) {

35
srsgnb/hdr/stack/mac/sched_nr_cfg.h
View File

@ -56,17 +56,17 @@ void get_dci_locs(const srsran_coreset_t& coreset,
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
struct cell_params_t;
struct cell_config_manager;
/// Structure that extends the sched_nr_interface::bwp_cfg_t passed by upper layers with other
/// derived BWP-specific params
struct bwp_params_t {
const uint32_t bwp_id;
const uint32_t cc;
const bwp_cfg_t cfg;
const cell_params_t& cell_cfg;
const sched_args_t& sched_cfg;
sched_nr_bwp_cfg_t bwp_cfg;
const uint32_t bwp_id;
const uint32_t cc;
const bwp_cfg_t cfg;
const cell_config_manager& cell_cfg;
const sched_args_t& sched_cfg;
sched_nr_bwp_cfg_t bwp_cfg;
// derived params
srslog::basic_logger& logger;
@ -93,7 +93,7 @@ struct bwp_params_t {
srsran::optional_vector<bwp_cce_pos_list> common_cce_list;
bwp_params_t(const cell_params_t& cell, uint32_t bwp_id, const sched_nr_bwp_cfg_t& bwp_cfg);
bwp_params_t(const cell_config_manager& cell, uint32_t bwp_id, const sched_nr_bwp_cfg_t& bwp_cfg);
prb_interval coreset_prb_range(uint32_t cs_id) const { return coresets[cs_id].prb_limits; }
prb_interval dci_fmt_1_0_prb_lims(uint32_t cs_id) const { return coresets[cs_id].dci_1_0_prb_limits; }
@ -115,12 +115,12 @@ private:
};
/// Structure packing a single cell config params, and sched args
struct cell_params_t {
struct cell_config_manager {
const uint32_t cc;
srsran_carrier_nr_t carrier = {};
srsran::phy_cfg_nr_t::ssb_cfg_t ssb = {};
std::vector<bwp_params_t> bwps; // idx0 for BWP-common
srsran_mib_nr_t mib;
srsran::phy_cfg_nr_t::ssb_cfg_t ssb = {};
std::vector<bwp_params_t> bwps; // idx0 for BWP-common
std::vector<sched_nr_cell_cfg_sib_t> sibs;
asn1::copy_ptr<asn1::rrc_nr::dl_cfg_common_sib_s> dl_cfg_common;
asn1::copy_ptr<asn1::rrc_nr::ul_cfg_common_sib_s> ul_cfg_common;
@ -128,22 +128,15 @@ struct cell_params_t {
const sched_args_t& sched_args;
const srsran::phy_cfg_nr_t default_ue_phy_cfg;
cell_params_t(uint32_t cc_, const sched_nr_cell_cfg_t& cell, const sched_args_t& sched_args_);
cell_config_manager(uint32_t cc_, const sched_nr_cell_cfg_t& cell, const sched_args_t& sched_args_);
uint32_t nof_prb() const { return carrier.nof_prb; }
/// Table specifying if a slot has DL or UL enabled
struct slot_cfg {
bool is_dl;
bool is_ul;
};
srsran::bounded_vector<slot_cfg, SRSRAN_NOF_SF_X_FRAME> slots;
};
/// Structure packing both the sched args and all gNB NR cell configurations
struct sched_params_t {
sched_args_t sched_cfg;
std::vector<cell_params_t> cells;
sched_args_t sched_cfg;
std::vector<cell_config_manager> cells;
sched_params_t() = default;
explicit sched_params_t(const sched_args_t& sched_cfg_);

33
srsgnb/hdr/stack/mac/sched_nr_interface.h
View File

@ -76,15 +76,30 @@ struct sched_nr_cell_cfg_sib_t {
};
struct sched_nr_cell_cfg_t {
static const size_t MAX_SIBS = 2;
srsran_carrier_nr_t carrier = {};
srsran::phy_cfg_nr_t::ssb_cfg_t ssb = {};
std::vector<sched_nr_bwp_cfg_t> bwps{1}; // idx0 for BWP-common
srsran_mib_nr_t mib;
std::vector<sched_nr_cell_cfg_sib_t> sibs;
asn1::copy_ptr<asn1::rrc_nr::dl_cfg_common_sib_s> dl_cfg_common;
asn1::copy_ptr<asn1::rrc_nr::ul_cfg_common_sib_s> ul_cfg_common;
asn1::copy_ptr<asn1::rrc_nr::tdd_ul_dl_cfg_common_s> tdd_ul_dl_cfg_common;
static const size_t MAX_SIBS = 2;
using ssb_positions_in_burst_t = asn1::rrc_nr::serving_cell_cfg_common_sib_s::ssb_positions_in_burst_s_;
uint32_t nof_layers;
uint32_t pci;
uint32_t dl_cell_nof_prb;
uint32_t ul_cell_nof_prb;
asn1::copy_ptr<asn1::rrc_nr::dl_cfg_common_sib_s> dl_cfg_common;
asn1::copy_ptr<asn1::rrc_nr::ul_cfg_common_sib_s> ul_cfg_common;
srsran::optional<asn1::rrc_nr::tdd_ul_dl_cfg_common_s> tdd_ul_dl_cfg_common;
ssb_positions_in_burst_t ssb_positions_in_burst;
uint32_t ssb_periodicity_ms = 0;
asn1::rrc_nr::mib_s::dmrs_type_a_position_e_ dmrs_type_a_position;
asn1::rrc_nr::subcarrier_spacing_e ssb_scs;
asn1::rrc_nr::pdcch_cfg_sib1_s pdcch_cfg_sib1;
int ss_pbch_block_power = 0;
// Extras
std::vector<sched_nr_bwp_cfg_t> bwps{1}; // idx0 for BWP-common
std::vector<sched_nr_cell_cfg_sib_t> sibs;
double dl_center_frequency_hz;
double ul_center_frequency_hz;
double ssb_center_freq_hz;
uint32_t offset_to_carrier;
srsran_subcarrier_spacing_t scs;
};
class sched_nr_interface

2
srsgnb/hdr/stack/mac/sched_nr_interface_utils.h
View File

@ -61,6 +61,8 @@ inline bool operator==(srsran_dci_location_t lhs, srsran_dci_location_t rhs)
//////////////////////////////////// UE configuration Helpers ////////////////////////////////////////////
void make_mib_cfg(const sched_nr_cell_cfg_t& cfg, srsran_mib_nr_t* mib);
void make_ssb_cfg(const sched_nr_cell_cfg_t& cfg, srsran::phy_cfg_nr_t::ssb_cfg_t* ssb);
srsran::phy_cfg_nr_t get_common_ue_phy_cfg(const sched_nr_cell_cfg_t& cfg);
} // namespace srsenb

8
srsgnb/hdr/stack/mac/sched_nr_ue.h
View File

@ -81,7 +81,7 @@ class ue_carrier
public:
ue_carrier(uint16_t rnti,
const ue_cfg_manager& cfg,
const cell_params_t& cell_params_,
const cell_config_manager& cell_params_,
const ue_context_common& ctxt,
const ue_buffer_manager::pdu_builder& pdu_builder_);
@ -91,9 +91,9 @@ public:
int dl_ack_info(uint32_t pid, uint32_t tb_idx, bool ack);
int ul_crc_info(uint32_t pid, bool crc);
const uint16_t rnti;
const uint32_t cc;
const cell_params_t& cell_params;
const uint16_t rnti;
const uint32_t cc;
const cell_config_manager& cell_params;
// Channel state
uint32_t dl_cqi = 1;

6
srsgnb/hdr/stack/mac/sched_nr_worker.h
View File

@ -33,7 +33,7 @@ namespace sched_nr_impl {
class cc_worker
{
public:
explicit cc_worker(const cell_params_t& params);
explicit cc_worker(const cell_config_manager& params);
void dl_rach_info(const sched_nr_interface::rar_info_t& rar_info);
@ -41,8 +41,8 @@ public:
ul_sched_t* get_ul_sched(slot_point sl);
// const params
const cell_params_t& cfg;
srslog::basic_logger& logger;
const cell_config_manager& cfg;
srslog::basic_logger& logger;
// cc-specific resources
srsran::bounded_vector<bwp_manager, SCHED_NR_MAX_BWP_PER_CELL> bwps;

2
srsgnb/src/stack/mac/mac_nr.cc
View File

@ -273,7 +273,7 @@ void mac_nr::get_metrics_nolock(srsenb::mac_metrics_t& metrics)
metrics.cc_info.resize(detected_rachs.size());
for (unsigned cc = 0, e = detected_rachs.size(); cc != e; ++cc) {
metrics.cc_info[cc].cc_rach_counter = detected_rachs[cc];
metrics.cc_info[cc].pci = (cc < cell_config.size()) ? cell_config[cc].carrier.pci : 0;
metrics.cc_info[cc].pci = (cc < cell_config.size()) ? cell_config[cc].pci : 0;
}
}

38
srsgnb/src/stack/mac/sched_nr_cfg.cc
View File

@ -39,7 +39,7 @@ void get_dci_locs(const srsran_coreset_t& coreset,
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
bwp_params_t::bwp_params_t(const cell_params_t& cell, uint32_t bwp_id_, const sched_nr_bwp_cfg_t& bwp_cfg) :
bwp_params_t::bwp_params_t(const cell_config_manager& cell, uint32_t bwp_id_, const sched_nr_bwp_cfg_t& bwp_cfg) :
cell_cfg(cell),
sched_cfg(cell.sched_args),
cc(cell.cc),
@ -131,22 +131,38 @@ bwp_params_t::bwp_params_t(const cell_params_t& cell, uint32_t bwp_id_, const sc
}
}
cell_params_t::cell_params_t(uint32_t cc_, const sched_nr_cell_cfg_t& cell, const sched_args_t& sched_args_) :
cc(cc_),
sched_args(sched_args_),
default_ue_phy_cfg(get_common_ue_phy_cfg(cell)),
ssb(cell.ssb),
carrier(cell.carrier),
mib(cell.mib),
sibs(cell.sibs)
cell_config_manager::cell_config_manager(uint32_t cc_,
const sched_nr_cell_cfg_t& cell,
const sched_args_t& sched_args_) :
cc(cc_), sched_args(sched_args_), default_ue_phy_cfg(get_common_ue_phy_cfg(cell)), sibs(cell.sibs)
{
// Conversion 36.331 ASN1 TDD-UL-DL-ConfigCommon to srsran_duplex_config_nr_t
carrier.pci = cell.pci;
carrier.dl_center_frequency_hz = cell.dl_center_frequency_hz;
carrier.ul_center_frequency_hz = cell.ul_center_frequency_hz;
carrier.ssb_center_freq_hz = cell.ssb_center_freq_hz;
carrier.offset_to_carrier = cell.offset_to_carrier;
carrier.scs = cell.scs;
carrier.nof_prb = cell.dl_cell_nof_prb;
carrier.start = 0; // TODO: Check
carrier.max_mimo_layers = cell.nof_layers;
if (cell.dl_cfg_common.is_present()) {
carrier.offset_to_carrier = cell.dl_cfg_common->freq_info_dl.scs_specific_carrier_list[0].offset_to_carrier;
carrier.scs = (srsran_subcarrier_spacing_t)cell.dl_cfg_common->init_dl_bwp.generic_params.subcarrier_spacing.value;
}
// TDD-UL-DL-ConfigCommon
duplex.mode = SRSRAN_DUPLEX_MODE_FDD;
if (cell.tdd_ul_dl_cfg_common.is_present()) {
if (cell.tdd_ul_dl_cfg_common.has_value()) {
bool success = srsran::make_phy_tdd_cfg(*cell.tdd_ul_dl_cfg_common, &duplex);
srsran_assert(success, "Failed to generate Cell TDD config");
}
// Set SSB params
make_ssb_cfg(cell, &ssb);
// MIB
make_mib_cfg(cell, &mib);
bwps.reserve(cell.bwps.size());
for (uint32_t i = 0; i < cell.bwps.size(); ++i) {
bwps.emplace_back(*this, i, cell.bwps[i]);

78
srsgnb/src/stack/mac/sched_nr_interface_utils.cc
View File

@ -12,6 +12,7 @@
#include "srsgnb/hdr/stack/mac/sched_nr_interface_utils.h"
#include "srsran/asn1/rrc_nr_utils.h"
#include "srsran/common/band_helper.h"
namespace srsenb {
@ -22,20 +23,72 @@ uint32_t coreset_nof_cces(const srsran_coreset_t& coreset)
return nof_freq_res * coreset.duration;
}
void make_mib_cfg(const sched_nr_cell_cfg_t& cfg, srsran_mib_nr_t* mib)
{
*mib = {};
mib->scs_common = cfg.scs;
mib->ssb_offset = 6; // TODO
mib->dmrs_typeA_pos = (srsran_dmrs_sch_typeA_pos_t)cfg.dmrs_type_a_position.value;
mib->coreset0_idx = cfg.pdcch_cfg_sib1.ctrl_res_set_zero;
mib->ss0_idx = cfg.pdcch_cfg_sib1.search_space_zero;
mib->cell_barred = false;
mib->intra_freq_reselection = true;
}
void make_ssb_cfg(const sched_nr_cell_cfg_t& cfg, srsran::phy_cfg_nr_t::ssb_cfg_t* ssb)
{
ssb->periodicity_ms = cfg.ssb_periodicity_ms;
ssb->position_in_burst = {};
uint32_t N = cfg.ssb_positions_in_burst.in_one_group.length();
for (uint32_t i = 0; i < N; ++i) {
ssb->position_in_burst[i] = cfg.ssb_positions_in_burst.in_one_group.get(i);
}
if (cfg.ssb_positions_in_burst.group_presence_present) {
for (uint32_t i = 1; i < cfg.ssb_positions_in_burst.group_presence.length(); ++i) {
if (cfg.ssb_positions_in_burst.group_presence.get(i)) {
std::copy(
ssb->position_in_burst.begin(), ssb->position_in_burst.begin() + N, ssb->position_in_burst.begin() + i * N);
}
}
}
ssb->scs = (srsran_subcarrier_spacing_t)cfg.ssb_scs.value;
ssb->pattern = SRSRAN_SSB_PATTERN_A;
if (cfg.dl_cfg_common.is_present()) {
if (cfg.dl_cfg_common->freq_info_dl.freq_band_list.size() > 0 and
cfg.dl_cfg_common->freq_info_dl.freq_band_list[0].freq_band_ind_nr_present) {
uint32_t band = cfg.dl_cfg_common->freq_info_dl.freq_band_list[0].freq_band_ind_nr;
ssb->pattern = srsran::srsran_band_helper::get_ssb_pattern(band, ssb->scs);
}
}
}
srsran::phy_cfg_nr_t get_common_ue_phy_cfg(const sched_nr_cell_cfg_t& cfg)
{
srsran::phy_cfg_nr_t ue_phy_cfg;
ue_phy_cfg.csi = {}; // disable CSI until RA is complete
// TDD UL-DL config
ue_phy_cfg.duplex.mode = SRSRAN_DUPLEX_MODE_FDD;
if (cfg.tdd_ul_dl_cfg_common.has_value()) {
bool success = srsran::make_phy_tdd_cfg(*cfg.tdd_ul_dl_cfg_common, &ue_phy_cfg.duplex);
srsran_sanity_check(success, "Failed to convert Cell TDDConfig to UEPHYConfig");
}
ue_phy_cfg.carrier = cfg.carrier;
ue_phy_cfg.ssb = cfg.ssb;
ue_phy_cfg.pdcch = cfg.bwps[0].pdcch;
ue_phy_cfg.pdsch = cfg.bwps[0].pdsch;
ue_phy_cfg.pusch = cfg.bwps[0].pusch;
ue_phy_cfg.pucch = cfg.bwps[0].pucch;
ue_phy_cfg.prach = cfg.bwps[0].prach;
ue_phy_cfg.harq_ack = cfg.bwps[0].harq_ack;
ue_phy_cfg.pdcch = cfg.bwps[0].pdcch;
ue_phy_cfg.pdsch = cfg.bwps[0].pdsch;
ue_phy_cfg.pusch = cfg.bwps[0].pusch;
ue_phy_cfg.pucch = cfg.bwps[0].pucch;
ue_phy_cfg.prach = cfg.bwps[0].prach;
ue_phy_cfg.harq_ack = cfg.bwps[0].harq_ack;
ue_phy_cfg.csi = {}; // disable CSI until RA is complete
ue_phy_cfg.carrier.pci = cfg.pci;
ue_phy_cfg.carrier.dl_center_frequency_hz = cfg.dl_center_frequency_hz;
ue_phy_cfg.carrier.ul_center_frequency_hz = cfg.ul_center_frequency_hz;
ue_phy_cfg.carrier.ssb_center_freq_hz = cfg.ssb_center_freq_hz;
ue_phy_cfg.carrier.offset_to_carrier = cfg.offset_to_carrier;
ue_phy_cfg.carrier.scs = cfg.scs;
ue_phy_cfg.carrier.nof_prb = cfg.dl_cell_nof_prb;
ue_phy_cfg.carrier.max_mimo_layers = cfg.nof_layers;
make_ssb_cfg(cfg, &ue_phy_cfg.ssb);
// remove UE-specific SearchSpaces (they will be added later via RRC)
for (uint32_t i = 0; i < SRSRAN_UE_DL_NR_MAX_NOF_SEARCH_SPACE; ++i) {
@ -46,13 +99,6 @@ srsran::phy_cfg_nr_t get_common_ue_phy_cfg(const sched_nr_cell_cfg_t& cfg)
}
}
// TDD UL-DL config
ue_phy_cfg.duplex.mode = SRSRAN_DUPLEX_MODE_FDD;
if (cfg.tdd_ul_dl_cfg_common.is_present()) {
bool success = srsran::make_phy_tdd_cfg(*cfg.tdd_ul_dl_cfg_common, &ue_phy_cfg.duplex);
srsran_sanity_check(success, "Failed to convert Cell TDDConfig to UEPHYConfig");
}
return ue_phy_cfg;
}

2
srsgnb/src/stack/mac/sched_nr_ue.cc
View File

@ -84,7 +84,7 @@ slot_ue::slot_ue(ue_carrier& ue_, slot_point slot_tx_) : ue(&ue_), pdcch_slot(sl
ue_carrier::ue_carrier(uint16_t rnti_,
const ue_cfg_manager& uecfg_,
const cell_params_t& cell_params_,
const cell_config_manager& cell_params_,
const ue_context_common& ctxt,
const ue_buffer_manager::pdu_builder& pdu_builder_) :
rnti(rnti_),

2
srsgnb/src/stack/mac/sched_nr_worker.cc
View File

@ -18,7 +18,7 @@
namespace srsenb {
namespace sched_nr_impl {
cc_worker::cc_worker(const cell_params_t& params) :
cc_worker::cc_worker(const cell_config_manager& params) :
cfg(params), logger(srslog::fetch_basic_logger(params.sched_args.logger_name))
{
for (uint32_t bwp_id = 0; bwp_id < cfg.bwps.size(); ++bwp_id) {

29
srsgnb/src/stack/mac/test/sched_nr_cfg_generators.h
View File

@ -49,10 +49,23 @@ inline sched_nr_cell_cfg_t get_default_cell_cfg(const srsran::phy_cfg_nr_t& phy_
{
sched_nr_cell_cfg_t cell_cfg{};
cell_cfg.carrier = phy_cfg.carrier;
cell_cfg.ssb = phy_cfg.ssb;
cell_cfg.mib.coreset0_idx = 6;
cell_cfg.mib.scs_common = srsran_subcarrier_spacing_15kHz;
cell_cfg.pci = phy_cfg.carrier.pci;
cell_cfg.dl_center_frequency_hz = phy_cfg.carrier.dl_center_frequency_hz;
cell_cfg.ul_center_frequency_hz = phy_cfg.carrier.ul_center_frequency_hz;
cell_cfg.ssb_center_freq_hz = phy_cfg.carrier.ssb_center_freq_hz;
cell_cfg.offset_to_carrier = phy_cfg.carrier.offset_to_carrier;
cell_cfg.scs = phy_cfg.carrier.scs;
cell_cfg.dl_cell_nof_prb = phy_cfg.carrier.nof_prb;
cell_cfg.nof_layers = phy_cfg.carrier.max_mimo_layers;
cell_cfg.ssb_periodicity_ms = phy_cfg.ssb.periodicity_ms;
for (uint32_t i = 0; i < cell_cfg.ssb_positions_in_burst.in_one_group.length(); ++i) {
cell_cfg.ssb_positions_in_burst.in_one_group.set(i, phy_cfg.ssb.position_in_burst[i]);
}
// TODO: phy_cfg.ssb_positions_in_burst.group_presence_present
cell_cfg.dmrs_type_a_position.value = asn1::rrc_nr::mib_s::dmrs_type_a_position_opts::pos2;
cell_cfg.ssb_scs.value = (asn1::rrc_nr::subcarrier_spacing_opts::options)phy_cfg.ssb.scs;
cell_cfg.pdcch_cfg_sib1.ctrl_res_set_zero = 6;
cell_cfg.pdcch_cfg_sib1.search_space_zero = 0;
cell_cfg.bwps.resize(1);
cell_cfg.bwps[0].pdcch = phy_cfg.pdcch;
@ -64,10 +77,10 @@ inline sched_nr_cell_cfg_t get_default_cell_cfg(const srsran::phy_cfg_nr_t& phy_
cell_cfg.bwps[0].rb_width = phy_cfg.carrier.nof_prb;
if (phy_cfg.duplex.mode == SRSRAN_DUPLEX_MODE_TDD) {
cell_cfg.tdd_ul_dl_cfg_common.reset(new asn1::rrc_nr::tdd_ul_dl_cfg_common_s{});
srsran_assert(
srsran::make_phy_tdd_cfg(phy_cfg.duplex, srsran_subcarrier_spacing_15kHz, cell_cfg.tdd_ul_dl_cfg_common.get()),
"Failed to generate TDD config");
cell_cfg.tdd_ul_dl_cfg_common.emplace();
srsran_assert(srsran::make_phy_tdd_cfg(
phy_cfg.duplex, srsran_subcarrier_spacing_15kHz, &cell_cfg.tdd_ul_dl_cfg_common.value()),
"Failed to generate TDD config");
}
return cell_cfg;

5
srsgnb/src/stack/mac/test/sched_nr_common_test.cc
View File

@ -83,7 +83,8 @@ void test_pdcch_collisions(const srsran_pdcch_cfg_nr_t& pdcch_cfg,
}
}
void test_dl_pdcch_consistency(const cell_params_t& cell_cfg, srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcchs)
void test_dl_pdcch_consistency(const cell_config_manager& cell_cfg,
srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcchs)
{
for (const auto& pdcch : dl_pdcchs) {
TESTASSERT(pdcch.dci.bwp_id < cell_cfg.bwps.size());
@ -119,7 +120,7 @@ void test_pdsch_consistency(srsran::const_span<mac_interface_phy_nr::pdsch_t> pd
void test_ssb_scheduled_grant(
const srsran::slot_point& sl_point,
const sched_nr_impl::cell_params_t& cell_cfg,
const sched_nr_impl::cell_config_manager& cell_cfg,
const srsran::bounded_vector<mac_interface_phy_nr::ssb_t, mac_interface_phy_nr::MAX_SSB>& ssb_list)
{
/*

4
srsgnb/src/stack/mac/test/sched_nr_common_test.h
View File

@ -26,13 +26,13 @@ void test_pdcch_collisions(const srsran_pdcch_cfg_nr_t& pdcch_c
srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcchs,
srsran::const_span<sched_nr_impl::pdcch_ul_t> ul_pddchs);
void test_dl_pdcch_consistency(const sched_nr_impl::cell_params_t& cell_cfg,
void test_dl_pdcch_consistency(const sched_nr_impl::cell_config_manager& cell_cfg,
srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcch);
void test_pdsch_consistency(srsran::const_span<mac_interface_phy_nr::pdsch_t> dl_pdcch);
/// @brief Test whether the SSB grant gets scheduled with the correct periodicity.
void test_ssb_scheduled_grant(
const srsran::slot_point& sl_point,
const sched_nr_impl::cell_params_t& cell_cfg,
const sched_nr_impl::cell_config_manager& cell_cfg,
const srsran::bounded_vector<mac_interface_phy_nr::ssb_t, mac_interface_phy_nr::MAX_SSB>& ssb_list);
} // namespace srsenb

20
srsgnb/src/stack/mac/test/sched_nr_pdcch_test.cc
View File

@ -31,9 +31,9 @@ void test_coreset0_cfg()
srsran::test_delimit_logger delimiter{"Test PDCCH Allocation in CORESET#0"};
sched_nr_interface::sched_args_t sched_args;
sched_nr_impl::cell_params_t cell_cfg{0, get_default_sa_cell_cfg_common(), sched_args};
bwp_params_t& bwp_params = cell_cfg.bwps[0];
sched_nr_interface::sched_args_t sched_args;
sched_nr_impl::cell_config_manager cell_cfg{0, get_default_sa_cell_cfg_common(), sched_args};
bwp_params_t& bwp_params = cell_cfg.bwps[0];
// UE config
ue_cfg_manager uecfg{get_rach_ue_cfg(0)};
@ -145,9 +145,9 @@ void test_coreset2_cfg()
cell_cfg.bwps[0].pdcch.search_space_present[2] = true;
cell_cfg.bwps[0].pdcch.search_space[2] = get_default_ue_specific_search_space(2, 2);
cell_cfg.bwps[0].pdcch.coreset_present[2] = true;
cell_cfg.bwps[0].pdcch.coreset[2] = get_default_ue_specific_coreset(2, cell_cfg.carrier.pci);
sched_nr_impl::cell_params_t cellparams{0, cell_cfg, sched_args};
bwp_params_t& bwp_params = cellparams.bwps[0];
cell_cfg.bwps[0].pdcch.coreset[2] = get_default_ue_specific_coreset(2, cell_cfg.pci);
sched_nr_impl::cell_config_manager cellparams{0, cell_cfg, sched_args};
bwp_params_t& bwp_params = cellparams.bwps[0];
// UE config
ue_cfg_manager uecfg{get_rach_ue_cfg(0)};
@ -235,14 +235,14 @@ void test_invalid_params()
cell_cfg.bwps[0].pdcch.search_space_present[2] = true;
cell_cfg.bwps[0].pdcch.search_space[2] = get_default_ue_specific_search_space(2, 2);
cell_cfg.bwps[0].pdcch.coreset_present[2] = true;
cell_cfg.bwps[0].pdcch.coreset[2] = get_default_ue_specific_coreset(2, cell_cfg.carrier.pci);
cell_cfg.bwps[0].pdcch.coreset[2] = get_default_ue_specific_coreset(2, cell_cfg.pci);
cell_cfg.bwps[0].pdcch.search_space_present[3] = true;
cell_cfg.bwps[0].pdcch.search_space[3] = get_default_ue_specific_search_space(3, 2);
cell_cfg.bwps[0].pdcch.search_space[3].nof_formats = 1; // only DL
cell_cfg.bwps[0].pdcch.search_space[3].formats[0] = srsran_dci_format_nr_1_0;
sched_nr_interface::sched_args_t sched_args;
sched_nr_impl::cell_params_t cellparams{0, cell_cfg, sched_args};
bwp_params_t& bwp_params = cellparams.bwps[0];
sched_nr_interface::sched_args_t sched_args;
sched_nr_impl::cell_config_manager cellparams{0, cell_cfg, sched_args};
bwp_params_t& bwp_params = cellparams.bwps[0];
// UE config
ue_cfg_manager uecfg{get_rach_ue_cfg(0)};

68
srsgnb/src/stack/mac/test/sched_nr_sch_test.cc
View File

@ -28,7 +28,7 @@ sched_nr_cell_cfg_t get_cell_cfg()
cell_cfg.bwps[0].pdcch.search_space_present[2] = true;
cell_cfg.bwps[0].pdcch.search_space[2] = get_default_ue_specific_search_space(2, 2);
cell_cfg.bwps[0].pdcch.coreset_present[2] = true;
cell_cfg.bwps[0].pdcch.coreset[2] = get_default_ue_specific_coreset(2, cell_cfg.carrier.pci);
cell_cfg.bwps[0].pdcch.coreset[2] = get_default_ue_specific_coreset(2, cell_cfg.pci);
return cell_cfg;
}
@ -86,10 +86,10 @@ void test_si()
static const uint32_t ss_id = 0;
// Create Cell and UE configs
sched_nr_interface::sched_args_t sched_args;
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_params_t cell_params{0, cellcfg, sched_args};
const bwp_params_t& bwp_params = cell_params.bwps[0];
sched_nr_interface::sched_args_t sched_args;
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_config_manager cell_params{0, cellcfg, sched_args};
const bwp_params_t& bwp_params = cell_params.bwps[0];
pdsch_list_t pdschs;
pdsch_alloc_result alloc_res;
@ -145,9 +145,9 @@ void test_rar()
static const uint32_t ss_id = 1;
// Create Cell and UE configs
sched_nr_interface::sched_args_t sched_args;
sched_nr_impl::cell_params_t cell_cfg{0, get_cell_cfg(), sched_args};
const bwp_params_t& bwp_params = cell_cfg.bwps[0];
sched_nr_interface::sched_args_t sched_args;
sched_nr_impl::cell_config_manager cell_cfg{0, get_cell_cfg(), sched_args};
const bwp_params_t& bwp_params = cell_cfg.bwps[0];
pdsch_list_t pdschs;
pdsch_alloc_result alloc_res;
@ -202,12 +202,12 @@ void test_ue_pdsch()
srsran::test_delimit_logger delimiter{"Test PDSCH UE Allocation"};
// Create Cell and UE configs
sched_nr_interface::sched_args_t sched_args;
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_params_t cell_params{0, get_cell_cfg(), sched_args};
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cellcfg)};
const bwp_params_t& bwp_params = cell_params.bwps[0];
ue_carrier_params_t ue_cc{0x4601, bwp_params, uecfg};
sched_nr_interface::sched_args_t sched_args;
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_config_manager cell_params{0, get_cell_cfg(), sched_args};
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cellcfg)};
const bwp_params_t& bwp_params = cell_params.bwps[0];
ue_carrier_params_t ue_cc{0x4601, bwp_params, uecfg};
pdsch_list_t pdschs;
pdsch_alloc_result alloc_res;
@ -270,12 +270,12 @@ void test_pdsch_fail()
srsran::test_delimit_logger delimiter{"Test PDSCH Allocation Failure"};
// Create Cell and UE configs
sched_nr_interface::sched_args_t sched_args;
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_params_t cell_params{0, cellcfg, sched_args};
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cellcfg)};
const bwp_params_t& bwp_params = cell_params.bwps[0];
ue_carrier_params_t ue_cc{0x4601, bwp_params, uecfg};
sched_nr_interface::sched_args_t sched_args;
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_config_manager cell_params{0, cellcfg, sched_args};
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cellcfg)};
const bwp_params_t& bwp_params = cell_params.bwps[0];
ue_carrier_params_t ue_cc{0x4601, bwp_params, uecfg};
pdsch_list_t pdschs;
pdsch_alloc_result alloc_res;
@ -320,13 +320,13 @@ void test_multi_pdsch()
srsran::test_delimit_logger delimiter{"Test Multiple PDSCH Allocations"};
// Create Cell and UE configs
sched_nr_interface::sched_args_t sched_args;
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_params_t cell_params{0, cellcfg, sched_args};
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cellcfg)};
const bwp_params_t& bwp_params = cell_params.bwps[0];
ue_carrier_params_t ue_cc{0x4601, bwp_params, uecfg};
ue_carrier_params_t ue_cc2{0x4602, bwp_params, uecfg};
sched_nr_interface::sched_args_t sched_args;
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_config_manager cell_params{0, cellcfg, sched_args};
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cellcfg)};
const bwp_params_t& bwp_params = cell_params.bwps[0];
ue_carrier_params_t ue_cc{0x4601, bwp_params, uecfg};
ue_carrier_params_t ue_cc2{0x4602, bwp_params, uecfg};
pdsch_list_t pdschs;
pdsch_alloc_result alloc_res;
@ -412,13 +412,13 @@ void test_multi_pusch()
srsran::test_delimit_logger delimiter{"Test Multiple PUSCH Allocations"};
// Create Cell and UE configs
sched_nr_interface::sched_args_t sched_args;
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_params_t cell_params{0, cellcfg, sched_args};
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cellcfg)};
const bwp_params_t& bwp_params = cell_params.bwps[0];
ue_carrier_params_t ue_cc{0x4601, bwp_params, uecfg};
ue_carrier_params_t ue_cc2{0x4602, bwp_params, uecfg};
sched_nr_interface::sched_args_t sched_args;
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_config_manager cell_params{0, cellcfg, sched_args};
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cellcfg)};
const bwp_params_t& bwp_params = cell_params.bwps[0];
ue_carrier_params_t ue_cc{0x4601, bwp_params, uecfg};
ue_carrier_params_t ue_cc2{0x4602, bwp_params, uecfg};
pusch_list_t puschs;
pusch_alloc_result alloc_res;

16
srsgnb/src/stack/mac/test/sched_nr_sim_ue.h
View File

@ -82,8 +82,8 @@ struct sim_nr_ue_ctxt_t {
}
};
struct sim_nr_enb_ctxt_t {
srsran::span<const sched_nr_impl::cell_params_t> cell_params;
std::map<uint16_t, const sim_nr_ue_ctxt_t*> ue_db;
srsran::span<const sched_nr_impl::cell_config_manager> cell_params;
std::map<uint16_t, const sim_nr_ue_ctxt_t*> ue_db;
};
class sched_nr_ue_sim
@ -133,7 +133,7 @@ public:
void add_rlc_dl_bytes(uint16_t rnti, uint32_t lcid, uint32_t pdu_size_bytes);
srsran::const_span<sched_nr_impl::cell_params_t> get_cell_params() const { return cell_params; }
srsran::const_span<sched_nr_impl::cell_config_manager> get_cell_params() const { return cell_params; }
/**
* @brief Specify external events that will be forwarded to the scheduler (CQI, ACKs, etc.) in the given slot
@ -167,11 +167,11 @@ protected:
/// Runs general tests to verify result consistency, and updates UE state
void process_results();
std::unique_ptr<srsran::test_delimit_logger> test_delimiter;
srslog::basic_logger& logger;
srslog::basic_logger& mac_logger;
std::unique_ptr<sched_nr> sched_ptr;
std::vector<sched_nr_impl::cell_params_t> cell_params;
std::unique_ptr<srsran::test_delimit_logger> test_delimiter;
srslog::basic_logger& logger;
srslog::basic_logger& mac_logger;
std::unique_ptr<sched_nr> sched_ptr;
std::vector<sched_nr_impl::cell_config_manager> cell_params;
std::vector<std::unique_ptr<srsran::task_worker> > cc_workers;

47
srsgnb/src/stack/rrc/rrc_nr.cc
View File

@ -303,31 +303,44 @@ void rrc_nr::config_mac()
sched_nr_cell_cfg_t& cell = sched_cells_cfg[0];
// Derive cell config from rrc_nr_cfg_t
cell.bwps[0].pdcch = cfg.cell_list[0].phy_cell.pdcch;
bool valid_cfg = srsran::make_phy_mib(cell_ctxt->mib, &cell.mib);
srsran_assert(valid_cfg, "Invalid NR cell MIB configuration.");
cell.ssb.periodicity_ms = cfg.cell_list[0].ssb_cfg.periodicity_ms;
cell.ssb.position_in_burst[0] = true;
cell.ssb.scs = cfg.cell_list[0].ssb_cfg.scs;
cell.ssb.pattern = cfg.cell_list[0].ssb_cfg.pattern;
cell.bwps[0].pdcch = cfg.cell_list[0].phy_cell.pdcch;
cell.pci = cfg.cell_list[0].phy_cell.carrier.pci;
cell.nof_layers = cfg.cell_list[0].phy_cell.carrier.max_mimo_layers;
cell.dl_cell_nof_prb = cfg.cell_list[0].phy_cell.carrier.nof_prb;
cell.ul_cell_nof_prb = cfg.cell_list[0].phy_cell.carrier.nof_prb;
cell.dl_center_frequency_hz = cfg.cell_list[0].phy_cell.carrier.dl_center_frequency_hz;
cell.ul_center_frequency_hz = cfg.cell_list[0].phy_cell.carrier.ul_center_frequency_hz;
cell.ssb_center_freq_hz = cfg.cell_list[0].phy_cell.carrier.ssb_center_freq_hz;
cell.offset_to_carrier = cfg.cell_list[0].phy_cell.carrier.offset_to_carrier;
cell.scs = cfg.cell_list[0].phy_cell.carrier.scs;
if (not cfg.is_standalone) {
const serving_cell_cfg_common_s& serv_cell = base_sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common;
// Derive cell config from ASN1
valid_cfg = srsran::make_pdsch_cfg_from_serv_cell(base_sp_cell_cfg.sp_cell_cfg_ded, &cell.bwps[0].pdsch);
bool valid_cfg = srsran::make_pdsch_cfg_from_serv_cell(base_sp_cell_cfg.sp_cell_cfg_ded, &cell.bwps[0].pdsch);
srsran_assert(valid_cfg, "Invalid NR cell configuration.");
if (base_sp_cell_cfg.sp_cell_cfg_ded.tdd_ul_dl_cfg_ded_present) {
cell.tdd_ul_dl_cfg_common.reset(
new tdd_ul_dl_cfg_common_s{base_sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.tdd_ul_dl_cfg_common});
if (serv_cell.tdd_ul_dl_cfg_common_present) {
cell.tdd_ul_dl_cfg_common.emplace(serv_cell.tdd_ul_dl_cfg_common);
}
cell.ssb_positions_in_burst.in_one_group.set(0, true);
cell.ssb_periodicity_ms = serv_cell.ssb_periodicity_serving_cell.to_number();
cell.ssb_scs = serv_cell.ssb_subcarrier_spacing;
cell.ss_pbch_block_power = serv_cell.ss_pbch_block_pwr;
} else {
cell.bwps[0].pdsch.p_zp_csi_rs_set = {};
const serving_cell_cfg_common_sib_s& serv_cell = cell_ctxt->sib1.serving_cell_cfg_common;
cell.bwps[0].pdsch.p_zp_csi_rs_set = {};
bzero(cell.bwps[0].pdsch.nzp_csi_rs_sets, sizeof(cell.bwps[0].pdsch.nzp_csi_rs_sets));
cell.dl_cfg_common.reset(new dl_cfg_common_sib_s{cell_ctxt->sib1.serving_cell_cfg_common.dl_cfg_common});
cell.ul_cfg_common.reset(new ul_cfg_common_sib_s{cell_ctxt->sib1.serving_cell_cfg_common.ul_cfg_common});
if (cell_ctxt->sib1.serving_cell_cfg_common.tdd_ul_dl_cfg_common_present) {
cell.tdd_ul_dl_cfg_common.reset(
new tdd_ul_dl_cfg_common_s{cell_ctxt->sib1.serving_cell_cfg_common.tdd_ul_dl_cfg_common});
cell.dl_cfg_common.reset(new dl_cfg_common_sib_s{serv_cell.dl_cfg_common});
cell.ul_cfg_common.reset(new ul_cfg_common_sib_s{serv_cell.ul_cfg_common});
if (serv_cell.tdd_ul_dl_cfg_common_present) {
cell.tdd_ul_dl_cfg_common.emplace(serv_cell.tdd_ul_dl_cfg_common);
}
cell.ssb_positions_in_burst = serv_cell.ssb_positions_in_burst;
cell.ssb_periodicity_ms = serv_cell.ssb_periodicity_serving_cell.to_number();
cell.ssb_scs.value = (subcarrier_spacing_e::options)cfg.cell_list[0].phy_cell.carrier.scs;
cell.ss_pbch_block_power = serv_cell.ss_pbch_block_pwr;
}
cell.dmrs_type_a_position = cell_ctxt->mib.dmrs_type_a_position;
cell.pdcch_cfg_sib1 = cell_ctxt->mib.pdcch_cfg_sib1;
// Set SIB1 and SI messages
cell.sibs.resize(cell_ctxt->sib_buffer.size());