mirror of https://github.com/PentHertz/srsLTE.git
nr,gnb,mac: implement basic sib1 scheduling
This commit is contained in:
parent
30c0ffe3e5
commit
60d4d12070
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@ -89,8 +89,9 @@ private:
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void get_metrics_nolock(srsenb::mac_metrics_t& metrics);
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// Encoding
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srsran::byte_buffer_t* assemble_rar(srsran::const_span<sched_nr_interface::msg3_grant_t> grants);
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srsran::unique_byte_buffer_t rar_pdu_buffer = nullptr;
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srsran::byte_buffer_t* assemble_rar(srsran::const_span<sched_nr_interface::msg3_grant_t> grants);
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srsran::unique_byte_buffer_t rar_pdu_buffer;
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// Interaction with other components
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phy_interface_stack_nr* phy = nullptr;
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@ -15,36 +15,13 @@
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#include "sched_nr_cfg.h"
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#include "sched_nr_grant_allocator.h"
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#include "sched_nr_signalling.h"
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#include "sched_nr_time_rr.h"
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#include "srsran/adt/pool/cached_alloc.h"
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namespace srsenb {
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namespace sched_nr_impl {
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/// SIB scheduler
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class si_sched
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{
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public:
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explicit si_sched(const bwp_params_t& bwp_cfg_);
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void run_slot(bwp_slot_allocator& slot_alloc);
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private:
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const bwp_params_t* bwp_cfg = nullptr;
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srslog::basic_logger& logger;
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struct sched_si_t {
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uint32_t n = 0;
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uint32_t len = 0;
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uint32_t win_len = 0;
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uint32_t period = 0;
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uint32_t n_tx = 0;
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alloc_result result = alloc_result::invalid_coderate;
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slot_point win_start;
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};
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srsran::bounded_vector<sched_si_t, 10> pending_sis;
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};
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using dl_sched_rar_info_t = sched_nr_interface::rar_info_t;
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/// RAR/Msg3 scheduler
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@ -87,6 +64,7 @@ public:
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const bwp_params_t* cfg;
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// channel-specific schedulers
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si_sched si;
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ra_sched ra;
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std::unique_ptr<sched_nr_base> data_sched;
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@ -54,6 +54,8 @@ struct bwp_slot_grid {
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slot_coreset_list coresets;
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harq_ack_list_t pending_acks;
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srsran::bounded_vector<uint32_t, MAX_GRANTS> sib_idxs;
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srsran::unique_pool_ptr<tx_harq_softbuffer> rar_softbuffer;
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bwp_slot_grid() = default;
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@ -98,11 +100,14 @@ public:
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alloc_result alloc_pdsch(slot_ue& ue, const prb_grant& dl_grant);
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alloc_result alloc_pusch(slot_ue& ue, const prb_grant& dl_mask);
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slot_point get_pdcch_tti() const { return pdcch_slot; }
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slot_point get_tti_rx() const { return pdcch_slot - TX_ENB_DELAY; }
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const bwp_res_grid& res_grid() const { return bwp_grid; }
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slot_point get_pdcch_tti() const { return pdcch_slot; }
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slot_point get_tti_rx() const { return pdcch_slot - TX_ENB_DELAY; }
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const bwp_res_grid& res_grid() const { return bwp_grid; }
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const bwp_slot_grid& tx_slot_grid() const { return bwp_grid[pdcch_slot]; }
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bwp_slot_grid& tx_slot_grid() { return bwp_grid[pdcch_slot]; }
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const bwp_params_t& cfg;
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srslog::basic_logger& logger;
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const bwp_params_t& cfg;
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private:
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alloc_result
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@ -110,8 +115,7 @@ private:
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alloc_result verify_pusch_space(bwp_slot_grid& pusch_grid, bwp_slot_grid* pdcch_grid = nullptr) const;
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alloc_result verify_ue_cfg(const ue_carrier_params_t& ue_cfg, harq_proc* harq) const;
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srslog::basic_logger& logger;
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bwp_res_grid& bwp_grid;
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bwp_res_grid& bwp_grid;
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slot_point pdcch_slot;
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slot_ue_map_t& slot_ues;
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@ -25,6 +25,8 @@ struct bwp_res_grid;
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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bool fill_dci_sib(prb_interval interv, uint32_t sib_idx, const bwp_params_t& bwp_cfg, srsran_dci_dl_nr_t& dci);
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bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params_t& bwp_cfg, srsran_dci_dl_nr_t& dci);
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bool fill_dci_msg3(const slot_ue& ue, const bwp_params_t& bwp_cfg, srsran_dci_ul_nr_t& dci);
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@ -89,7 +89,7 @@ public:
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using ue_cc_cfg_t = sched_nr_ue_cc_cfg_t;
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using ue_cfg_t = sched_nr_ue_cfg_t;
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////// RA procedure //////
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////// RA signalling //////
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struct rar_info_t {
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uint32_t preamble_idx; // is this the RAPID?
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@ -117,6 +117,8 @@ public:
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struct dl_res_t {
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dl_sched_t phy;
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sched_rar_list_t rar;
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srsran::bounded_vector<uint32_t, MAX_GRANTS> sib_idxs;
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};
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virtual ~sched_nr_interface() = default;
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@ -13,12 +13,15 @@
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#ifndef SRSRAN_SCHED_NR_SIGNALLING_H
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#define SRSRAN_SCHED_NR_SIGNALLING_H
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#include "../sched_common.h"
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#include "sched_nr_cfg.h"
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#include "sched_nr_interface.h"
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namespace srsenb {
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namespace sched_nr_impl {
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class bwp_slot_allocator;
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/// Schedule NZP-CSI-RS resources for given slot
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void sched_nzp_csi_rs(srsran::const_span<srsran_csi_rs_nzp_set_t> nzp_csi_rs_sets,
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const srsran_slot_cfg_t& slot_cfg,
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@ -41,11 +44,35 @@ void sched_nzp_csi_rs(srsran::const_span<srsran_csi_rs_nzp_set_t> nzp_csi_rs_set
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*/
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void sched_ssb_basic(const slot_point& sl_point, uint32_t ssb_periodicity, ssb_list& ssb_list);
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/// Fill DCI fields with SIB info
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bool fill_dci_sib(prb_interval interv, uint32_t sib_idx, const bwp_params_t& bwp_cfg, srsran_dci_dl_nr_t& dci);
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/// For a given BWP and slot, schedule SSB, NZP CSI RS and SIBs
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void sched_dl_signalling(const bwp_params_t& bwp_params,
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slot_point sl_pdcch,
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ssb_list& ssb_list,
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nzp_csi_rs_list& nzp_csi_rs);
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void sched_dl_signalling(bwp_slot_allocator& bwp_alloc);
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/// scheduler for SIBs
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class si_sched
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{
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public:
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explicit si_sched(const bwp_params_t& bwp_cfg_);
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void run_slot(bwp_slot_allocator& slot_alloc);
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private:
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const bwp_params_t* bwp_cfg = nullptr;
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srslog::basic_logger& logger;
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struct si_msg_ctxt_t {
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uint32_t n = 0; /// index in schedulingInfoList in si-SchedulingInfo in SIB1
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uint32_t len = 0;
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uint32_t win_len = 0;
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uint32_t period = 0;
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uint32_t n_tx = 0;
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alloc_result result = alloc_result::invalid_coderate; /// last attempt to schedule SI
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slot_point win_start; /// start of SI window, invalid if outside
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};
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srsran::bounded_vector<si_msg_ctxt_t, 10> pending_sis;
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};
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} // namespace sched_nr_impl
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} // namespace srsenb
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@ -260,7 +260,7 @@ int mac_nr::cell_cfg(const std::vector<srsenb::sched_nr_interface::cell_cfg_t>&
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if (true) {
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sib_info_t sib = {};
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sib.index = i;
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sib.periodicity = 4; // TODO: read period_rf from config
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sib.periodicity = 160; // TODO: read period_rf from config
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sib.payload = srsran::make_byte_buffer();
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if (sib.payload == nullptr) {
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logger.error("Couldn't allocate PDU in %s().", __FUNCTION__);
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@ -460,7 +460,7 @@ mac_nr::dl_sched_t* mac_nr::get_dl_sched(const srsran_slot_cfg_t& slot_cfg)
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}
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// Generate MAC DL PDUs
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uint32_t rar_count = 0;
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uint32_t rar_count = 0, si_count = 0;
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srsran::rwlock_read_guard rw_lock(rwmutex);
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for (pdsch_t& pdsch : dl_res->phy.pdsch) {
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if (pdsch.sch.grant.rnti_type == srsran_rnti_type_c) {
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@ -484,6 +484,9 @@ mac_nr::dl_sched_t* mac_nr::get_dl_sched(const srsran_slot_cfg_t& slot_cfg)
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sched_nr_interface::rar_t& rar = dl_res->rar[rar_count++];
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// for RARs we could actually move the byte_buffer to the PHY, as there are no retx
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pdsch.data[0] = assemble_rar(rar.grants);
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} else if (pdsch.sch.grant.rnti_type == srsran_rnti_type_si) {
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uint32_t sib_idx = dl_res->sib_idxs[si_count++];
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pdsch.data[0] = bcch_dlsch_payload[sib_idx].payload.get();
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}
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}
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for (auto& u : ue_db) {
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@ -17,66 +17,6 @@
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namespace srsenb {
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namespace sched_nr_impl {
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si_sched::si_sched(const bwp_params_t& bwp_cfg_) :
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bwp_cfg(&bwp_cfg_), logger(srslog::fetch_basic_logger(bwp_cfg_.sched_cfg.logger_name))
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{}
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void si_sched::run_slot(bwp_slot_allocator& slot_alloc)
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{
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const uint32_t si_aggr_level = 2;
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slot_point pdcch_slot = slot_alloc.get_pdcch_tti();
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const prb_bitmap& prbs = slot_alloc.res_grid()[pdcch_slot].dl_prbs.prbs();
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// Update SI windows
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uint32_t N = bwp_cfg->slots.size();
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for (sched_si_t& si : pending_sis) {
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uint32_t x = (si.n - 1) * si.win_len;
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if (not si.win_start.valid() and (pdcch_slot.sfn() % si.period == x / N) and
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pdcch_slot.slot_idx() == x % bwp_cfg->slots.size()) {
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// If start o SI message window
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si.win_start = pdcch_slot;
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} else if (si.win_start.valid() and si.win_start + si.win_len >= pdcch_slot) {
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// If end of SI message window
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logger.warning(
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"SCHED: Could not allocate SI message idx=%d, len=%d. Cause: %s", si.n, si.len, to_string(si.result));
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si.win_start.clear();
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}
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}
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// Schedule pending SIs
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if (bwp_cfg->slots[pdcch_slot.slot_idx()].is_dl) {
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for (sched_si_t& si : pending_sis) {
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if (not si.win_start.valid()) {
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continue;
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}
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// TODO: NOTE 2: The UE is not required to monitor PDCCH monitoring occasion(s) corresponding to each transmitted
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// SSB in SI-window.
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// Attempt grants with increasing number of PRBs (if the number of PRBs is too low, the coderate is invalid)
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si.result = alloc_result::invalid_coderate;
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uint32_t prb_start_idx = 0;
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for (uint32_t nprbs = 4; nprbs < bwp_cfg->cfg.rb_width and si.result == alloc_result::invalid_coderate; ++nprbs) {
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prb_interval grant = find_empty_interval_of_length(prbs, nprbs, prb_start_idx);
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prb_start_idx = grant.start();
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if (grant.length() != nprbs) {
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si.result = alloc_result::no_sch_space;
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break;
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}
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si.result = slot_alloc.alloc_si(si_aggr_level, si.n, si.n_tx, grant);
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if (si.result == alloc_result::success) {
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// SIB scheduled successfully
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si.win_start.clear();
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si.n_tx++;
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}
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}
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}
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}
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}
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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ra_sched::ra_sched(const bwp_params_t& bwp_cfg_) :
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bwp_cfg(&bwp_cfg_), logger(srslog::fetch_basic_logger(bwp_cfg_.sched_cfg.logger_name))
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{}
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@ -221,7 +161,7 @@ int ra_sched::dl_rach_info(const dl_sched_rar_info_t& rar_info)
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}
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bwp_manager::bwp_manager(const bwp_params_t& bwp_cfg) :
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cfg(&bwp_cfg), ra(bwp_cfg), grid(bwp_cfg), data_sched(new sched_nr_time_rr())
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cfg(&bwp_cfg), ra(bwp_cfg), si(bwp_cfg), grid(bwp_cfg), data_sched(new sched_nr_time_rr())
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{}
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} // namespace sched_nr_impl
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@ -47,6 +47,7 @@ void bwp_slot_grid::reset()
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dl.phy.pdcch_ul.clear();
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dl.phy.pdsch.clear();
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dl.rar.clear();
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dl.sib_idxs.clear();
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ul.pusch.clear();
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ul.pucch.clear();
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pending_acks.clear();
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@ -68,20 +69,42 @@ bwp_slot_allocator::bwp_slot_allocator(bwp_res_grid& bwp_grid_, slot_point pdcch
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alloc_result bwp_slot_allocator::alloc_si(uint32_t aggr_idx, uint32_t si_idx, uint32_t si_ntx, const prb_interval& prbs)
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{
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bwp_slot_grid& bwp_pdcch_slot = bwp_grid[pdcch_slot];
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if (not bwp_pdcch_slot.is_dl()) {
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logger.warning("SCHED: Trying to allocate PDSCH in TDD non-DL slot index=%d", bwp_pdcch_slot.slot_idx);
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return alloc_result::no_sch_space;
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}
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pdcch_dl_list_t& pdsch_grants = bwp_pdcch_slot.dl.phy.pdcch_dl;
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if (pdsch_grants.full()) {
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logger.warning("SCHED: Maximum number of DL allocations reached");
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return alloc_result::no_grant_space;
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alloc_result ret = verify_pdsch_space(bwp_pdcch_slot, bwp_pdcch_slot);
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if (ret != alloc_result::success) {
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return ret;
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}
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if (bwp_pdcch_slot.dl_prbs.collides(prbs)) {
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return alloc_result::sch_collision;
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}
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// TODO: Allocate PDCCH and PDSCH
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const uint32_t coreset_id = 0;
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const uint32_t ss_id = 0;
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if (not bwp_pdcch_slot.coresets[coreset_id]->alloc_dci(pdcch_grant_type_t::sib, aggr_idx, ss_id)) {
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logger.warning("SCHED: Cannot allocate SIB1.");
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return alloc_result::no_cch_space;
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}
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// RAR allocation successful.
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bwp_pdcch_slot.dl_prbs |= prbs;
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// Generate DCI for RAR with given RA-RNTI
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pdcch_dl_t& pdcch = bwp_pdcch_slot.dl.phy.pdcch_dl.back();
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if (not fill_dci_sib(prbs, si_idx, *bwp_grid.cfg, pdcch.dci)) {
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// Cancel on-going PDCCH allocation
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bwp_pdcch_slot.coresets[coreset_id]->rem_last_dci();
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return alloc_result::invalid_coderate;
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}
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// Generate PDSCH
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bwp_pdcch_slot.dl.phy.pdsch.emplace_back();
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pdsch_t& pdsch = bwp_pdcch_slot.dl.phy.pdsch.back();
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srsran_slot_cfg_t slot_cfg;
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slot_cfg.idx = pdcch_slot.to_uint();
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int code = srsran_ra_dl_dci_to_grant_nr(
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&cfg.cell_cfg.carrier, &slot_cfg, &cfg.cfg.pdsch, &pdcch.dci, &pdsch.sch, &pdsch.sch.grant);
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srsran_assert(code == SRSRAN_SUCCESS, "Error converting DCI to grant");
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// Store SI msg index
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bwp_pdcch_slot.sib_idxs.push_back(si_idx);
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return alloc_result::success;
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}
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@ -104,6 +127,11 @@ alloc_result bwp_slot_allocator::alloc_rar_and_msg3(uint16_t
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if (ret != alloc_result::success) {
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return ret;
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}
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if (not bwp_pdcch_slot.dl.phy.ssb.empty()) {
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// TODO: support concurrent PDSCH and SSB
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logger.debug("SCHED: skipping RAR allocation. Cause: concurrent PDSCH and SSB not yet supported");
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return alloc_result::no_sch_space;
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}
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if (pending_rachs.size() > bwp_pdcch_slot.dl.rar.capacity() - bwp_pdcch_slot.dl.rar.size()) {
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logger.error("SCHED: Trying to allocate too many Msg3 grants in a single slot (%zd)", pending_rachs.size());
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return alloc_result::invalid_grant_params;
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@ -210,6 +238,11 @@ alloc_result bwp_slot_allocator::alloc_pdsch(slot_ue& ue, const prb_grant& dl_gr
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if (result != alloc_result::success) {
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return result;
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}
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if (not bwp_pdsch_slot.dl.phy.ssb.empty()) {
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// TODO: support concurrent PDSCH and SSB
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logger.debug("SCHED: skipping PDSCH allocation. Cause: concurrent PDSCH and SSB not yet supported");
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return alloc_result::no_sch_space;
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}
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if (bwp_pdsch_slot.dl_prbs.collides(dl_grant)) {
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return alloc_result::sch_collision;
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}
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@ -386,11 +419,6 @@ alloc_result bwp_slot_allocator::verify_pdsch_space(bwp_slot_grid& pdsch_grid,
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return alloc_result::no_grant_space;
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}
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}
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if (not pdsch_grid.dl.phy.ssb.empty()) {
|
||||
// TODO: support concurrent PDSCH and SSB
|
||||
logger.debug("SCHED: skipping PDSCH allocation. Cause: concurrent PDSCH and SSB not yet supported");
|
||||
return alloc_result::no_sch_space;
|
||||
}
|
||||
return alloc_result::success;
|
||||
}
|
||||
|
||||
|
|
|
@ -55,7 +55,6 @@ bool coreset_region::alloc_dci(pdcch_grant_type_t alloc_type,
|
|||
srsran_assert((user == nullptr) xor
|
||||
(alloc_type == pdcch_grant_type_t::dl_data or alloc_type == pdcch_grant_type_t::ul_data),
|
||||
"UE should be only provided for DL or UL data allocations");
|
||||
srsran_assert(not dci_list.full(), "SCHED: Unable to allocate DCI");
|
||||
saved_dfs_tree.clear();
|
||||
|
||||
alloc_record record;
|
||||
|
|
|
@ -11,6 +11,7 @@
|
|||
*/
|
||||
|
||||
#include "srsgnb/hdr/stack/mac/sched_nr_signalling.h"
|
||||
#include "srsgnb/hdr/stack/mac/sched_nr_grant_allocator.h"
|
||||
|
||||
#define POS_IN_BURST_FIRST_BIT_IDX 0
|
||||
#define POS_IN_BURST_SECOND_BIT_IDX 1
|
||||
|
@ -83,23 +84,119 @@ void sched_ssb_basic(const slot_point& sl_point, uint32_t ssb_periodicity, ssb_l
|
|||
}
|
||||
}
|
||||
|
||||
void sched_dl_signalling(const bwp_params_t& bwp_params,
|
||||
slot_point sl_pdcch,
|
||||
ssb_list& ssb_list,
|
||||
nzp_csi_rs_list& nzp_csi_rs)
|
||||
void sched_dl_signalling(bwp_slot_allocator& bwp_alloc)
|
||||
{
|
||||
const bwp_params_t& bwp_params = bwp_alloc.cfg;
|
||||
slot_point sl_pdcch = bwp_alloc.get_pdcch_tti();
|
||||
bwp_slot_grid& sl_grid = bwp_alloc.tx_slot_grid();
|
||||
|
||||
srsran_slot_cfg_t cfg;
|
||||
cfg.idx = sl_pdcch.to_uint();
|
||||
|
||||
// Schedule SSB
|
||||
sched_ssb_basic(sl_pdcch, bwp_params.cell_cfg.ssb.periodicity_ms, ssb_list);
|
||||
sched_ssb_basic(sl_pdcch, bwp_params.cell_cfg.ssb.periodicity_ms, sl_grid.dl.phy.ssb);
|
||||
|
||||
// Schedule NZP-CSI-RS
|
||||
sched_nzp_csi_rs(bwp_params.cfg.pdsch.nzp_csi_rs_sets, cfg, nzp_csi_rs);
|
||||
|
||||
// Schedule SIBs
|
||||
// TODO
|
||||
sched_nzp_csi_rs(bwp_params.cfg.pdsch.nzp_csi_rs_sets, cfg, sl_grid.dl.phy.nzp_csi_rs);
|
||||
}
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
bool fill_dci_sib(prb_interval interv, uint32_t sib_id, const bwp_params_t& bwp_cfg, srsran_dci_dl_nr_t& dci)
|
||||
{
|
||||
dci.mcs = 5;
|
||||
dci.ctx.format = srsran_dci_format_nr_1_0;
|
||||
dci.ctx.ss_type = srsran_search_space_type_common_0;
|
||||
dci.ctx.rnti_type = srsran_rnti_type_si;
|
||||
dci.ctx.rnti = SRSRAN_SIRNTI;
|
||||
dci.ctx.coreset_id = 0;
|
||||
dci.freq_domain_assigment = srsran_ra_nr_type1_riv(bwp_cfg.cfg.rb_width, interv.start(), interv.length());
|
||||
dci.time_domain_assigment = 0;
|
||||
dci.tpc = 1;
|
||||
dci.bwp_id = bwp_cfg.bwp_id;
|
||||
dci.cc_id = bwp_cfg.cc;
|
||||
dci.rv = 0;
|
||||
dci.sii = sib_id == 1 ? 0 : 1;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
si_sched::si_sched(const bwp_params_t& bwp_cfg_) :
|
||||
bwp_cfg(&bwp_cfg_), logger(srslog::fetch_basic_logger(bwp_cfg_.sched_cfg.logger_name))
|
||||
{}
|
||||
|
||||
void si_sched::run_slot(bwp_slot_allocator& bwp_alloc)
|
||||
{
|
||||
if (true) {
|
||||
// CORESET#0 must be present, otherwise SIs are not allocated
|
||||
// TODO: provide proper config
|
||||
return;
|
||||
}
|
||||
const uint32_t si_aggr_level = 2;
|
||||
slot_point sl_pdcch = bwp_alloc.get_pdcch_tti();
|
||||
const prb_bitmap& prbs = bwp_alloc.res_grid()[sl_pdcch].dl_prbs.prbs();
|
||||
|
||||
// SIB1 case
|
||||
if (sl_pdcch.to_uint() % 160 == 0) {
|
||||
// TODO: compute if SIB1 slot based on config
|
||||
const uint32_t aggr_lvl_idx = 2;
|
||||
const uint32_t sib_id = 1;
|
||||
const uint32_t sib1len = 77; // TODO: extract from config
|
||||
alloc_result ret = bwp_alloc.alloc_si(aggr_lvl_idx, sib_id, sib1len, prb_interval{0, 7});
|
||||
if (ret != alloc_result::success) {
|
||||
bwp_alloc.logger.warning("SCHED: Cannot allocate SIB1.");
|
||||
}
|
||||
}
|
||||
|
||||
// Update SI windows
|
||||
uint32_t N = bwp_cfg->slots.size();
|
||||
for (si_msg_ctxt_t& si : pending_sis) {
|
||||
uint32_t x = (si.n - 1) * si.win_len;
|
||||
|
||||
if (not si.win_start.valid() and (sl_pdcch.sfn() % si.period == x / N) and
|
||||
sl_pdcch.slot_idx() == x % bwp_cfg->slots.size()) {
|
||||
// If start of SI message window
|
||||
si.win_start = sl_pdcch;
|
||||
} else if (si.win_start.valid() and si.win_start + si.win_len >= sl_pdcch) {
|
||||
// If end of SI message window
|
||||
logger.warning(
|
||||
"SCHED: Could not allocate SI message idx=%d, len=%d. Cause: %s", si.n, si.len, to_string(si.result));
|
||||
si.win_start.clear();
|
||||
}
|
||||
}
|
||||
|
||||
// Schedule pending SIs
|
||||
if (bwp_cfg->slots[sl_pdcch.slot_idx()].is_dl) {
|
||||
for (si_msg_ctxt_t& si : pending_sis) {
|
||||
if (not si.win_start.valid()) {
|
||||
continue;
|
||||
}
|
||||
|
||||
// TODO: NOTE 2: The UE is not required to monitor PDCCH monitoring occasion(s) corresponding to each transmitted
|
||||
// SSB in SI-window.
|
||||
|
||||
// Attempt grants with increasing number of PRBs (if the number of PRBs is too low, the coderate is invalid)
|
||||
si.result = alloc_result::invalid_coderate;
|
||||
uint32_t prb_start_idx = 0;
|
||||
for (uint32_t nprbs = 4; nprbs < bwp_cfg->cfg.rb_width and si.result == alloc_result::invalid_coderate; ++nprbs) {
|
||||
prb_interval grant = find_empty_interval_of_length(prbs, nprbs, prb_start_idx);
|
||||
prb_start_idx = grant.start();
|
||||
if (grant.length() != nprbs) {
|
||||
si.result = alloc_result::no_sch_space;
|
||||
break;
|
||||
}
|
||||
si.result = bwp_alloc.alloc_si(si_aggr_level, si.n, si.n_tx, grant);
|
||||
if (si.result == alloc_result::success) {
|
||||
// SIB scheduled successfully
|
||||
si.win_start.clear();
|
||||
si.n_tx++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
} // namespace sched_nr_impl
|
||||
} // namespace srsenb
|
||||
|
|
|
@ -69,8 +69,10 @@ dl_sched_res_t* cc_worker::run_slot(slot_point pdcch_slot, ue_map_t& ue_db)
|
|||
log_sched_slot_ues(logger, pdcch_slot, cfg.cc, slot_ues);
|
||||
|
||||
// Allocate cell DL signalling
|
||||
bwp_slot_grid& bwp_pdcch_slot = bwps[0].grid[pdcch_slot];
|
||||
sched_dl_signalling(*bwps[0].cfg, pdcch_slot, bwp_pdcch_slot.dl.phy.ssb, bwp_pdcch_slot.dl.phy.nzp_csi_rs);
|
||||
sched_dl_signalling(bwp_alloc);
|
||||
|
||||
// Allocate pending SIBs
|
||||
bwps[0].si.run_slot(bwp_alloc);
|
||||
|
||||
// Allocate pending RARs
|
||||
bwps[0].ra.run_slot(bwp_alloc);
|
||||
|
@ -88,7 +90,7 @@ dl_sched_res_t* cc_worker::run_slot(slot_point pdcch_slot, ue_map_t& ue_db)
|
|||
// releases UE resources
|
||||
slot_ues.clear();
|
||||
|
||||
return &bwp_pdcch_slot.dl;
|
||||
return &bwp_alloc.tx_slot_grid().dl;
|
||||
}
|
||||
|
||||
ul_sched_t* cc_worker::get_ul_sched(slot_point sl)
|
||||
|
|
Loading…
Reference in New Issue