mirror of https://github.com/PentHertz/srsLTE.git
nr,gnb,sched: account for CORESET RB offset in the DCI RB indexing in case of common search spaces
This commit is contained in:
parent
90ed04afd1
commit
6df8b6bb9e
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@ -77,6 +77,17 @@ public:
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bool contains(T point) const { return start_ <= point and point < stop_; }
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bool contains(T point) const { return start_ <= point and point < stop_; }
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interval<T>& intersect(const interval<T>& other)
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{
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if (not overlaps(other)) {
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*this = interval<T>{};
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} else {
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start_ = std::max(start(), other.start());
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stop_ = std::min(stop(), other.stop());
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}
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return *this;
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}
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private:
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private:
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T start_;
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T start_;
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T stop_;
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T stop_;
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@ -99,8 +99,8 @@ public:
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uint32_t aggr_idx,
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uint32_t aggr_idx,
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prb_interval interv,
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prb_interval interv,
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srsran::const_span<dl_sched_rar_info_t> pending_rars);
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srsran::const_span<dl_sched_rar_info_t> pending_rars);
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alloc_result alloc_pdsch(slot_ue& ue, const prb_grant& dl_grant);
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alloc_result alloc_pdsch(slot_ue& ue, prb_grant dl_grant);
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alloc_result alloc_pusch(slot_ue& ue, const prb_grant& dl_mask);
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alloc_result alloc_pusch(slot_ue& ue, prb_grant dl_mask);
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slot_point get_pdcch_tti() const { return pdcch_slot; }
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slot_point get_pdcch_tti() const { return pdcch_slot; }
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slot_point get_tti_rx() const { return pdcch_slot - TX_ENB_DELAY; }
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slot_point get_tti_rx() const { return pdcch_slot - TX_ENB_DELAY; }
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@ -106,6 +106,16 @@ struct prb_grant {
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return alloc.interv;
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return alloc.interv;
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}
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}
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prb_grant& operator&=(const prb_interval interv)
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{
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if (is_alloc_type0()) {
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alloc.rbgs &= rbg_bitmap{alloc.rbgs.size()}.fill(interv.start(), interv.stop());
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} else {
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alloc.interv.intersect(interv);
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}
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return *this;
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}
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private:
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private:
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bool alloc_type_0 = false;
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bool alloc_type_0 = false;
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union alloc_t {
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union alloc_t {
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@ -118,6 +118,7 @@ public:
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slot_ue make_slot_ue(slot_point pdcch_slot, uint32_t cc);
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slot_ue make_slot_ue(slot_point pdcch_slot, uint32_t cc);
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/// Update UE CC configuration
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void set_cfg(const ue_cfg_t& cfg);
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void set_cfg(const ue_cfg_t& cfg);
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const ue_cfg_t& cfg() const { return ue_cfg; }
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const ue_cfg_t& cfg() const { return ue_cfg; }
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@ -295,7 +295,7 @@ alloc_result bwp_slot_allocator::alloc_rar_and_msg3(uint16_t
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// ue is the UE (1 only) that will be allocated
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// ue is the UE (1 only) that will be allocated
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// func computes the grant allocation for this UE
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// func computes the grant allocation for this UE
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alloc_result bwp_slot_allocator::alloc_pdsch(slot_ue& ue, const prb_grant& dl_grant)
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alloc_result bwp_slot_allocator::alloc_pdsch(slot_ue& ue, prb_grant dl_grant)
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{
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{
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static const uint32_t aggr_idx = 2;
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static const uint32_t aggr_idx = 2;
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static const std::array<srsran_dci_format_nr_t, 2> dci_fmt_list{srsran_dci_format_nr_1_1, srsran_dci_format_nr_1_0};
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static const std::array<srsran_dci_format_nr_t, 2> dci_fmt_list{srsran_dci_format_nr_1_1, srsran_dci_format_nr_1_0};
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@ -334,6 +334,9 @@ alloc_result bwp_slot_allocator::alloc_pdsch(slot_ue& ue, const prb_grant& dl_gr
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return alloc_result::no_cch_space;
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return alloc_result::no_cch_space;
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}
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}
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uint32_t coreset_id = ss[0]->coreset_id;
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uint32_t coreset_id = ss[0]->coreset_id;
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if (SRSRAN_SEARCH_SPACE_IS_COMMON(ss[0]->type)) {
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dl_grant &= prb_interval{ue->phy().pdcch.coreset[ss[0]->coreset_id].offset_rb, ue->phy().carrier.nof_prb};
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}
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if (not bwp_pdcch_slot.coresets[coreset_id]->alloc_dci(pdcch_grant_type_t::dl_data, aggr_idx, ss[0]->id, &ue.cfg())) {
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if (not bwp_pdcch_slot.coresets[coreset_id]->alloc_dci(pdcch_grant_type_t::dl_data, aggr_idx, ss[0]->id, &ue.cfg())) {
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// Could not find space in PDCCH
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// Could not find space in PDCCH
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return alloc_result::no_cch_space;
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return alloc_result::no_cch_space;
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@ -406,7 +409,7 @@ alloc_result bwp_slot_allocator::alloc_pdsch(slot_ue& ue, const prb_grant& dl_gr
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return alloc_result::success;
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return alloc_result::success;
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}
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}
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alloc_result bwp_slot_allocator::alloc_pusch(slot_ue& ue, const prb_grant& ul_prbs)
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alloc_result bwp_slot_allocator::alloc_pusch(slot_ue& ue, prb_grant ul_grant)
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{
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{
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static const uint32_t aggr_idx = 2;
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static const uint32_t aggr_idx = 2;
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static const std::array<srsran_dci_format_nr_t, 2> dci_fmt_list{srsran_dci_format_nr_0_1, srsran_dci_format_nr_0_0};
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static const std::array<srsran_dci_format_nr_t, 2> dci_fmt_list{srsran_dci_format_nr_0_1, srsran_dci_format_nr_0_0};
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@ -422,7 +425,7 @@ alloc_result bwp_slot_allocator::alloc_pusch(slot_ue& ue, const prb_grant& ul_pr
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return ret;
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return ret;
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}
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}
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pdcch_ul_list_t& pdcchs = bwp_pdcch_slot.dl.phy.pdcch_ul;
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pdcch_ul_list_t& pdcchs = bwp_pdcch_slot.dl.phy.pdcch_ul;
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if (bwp_pusch_slot.ul_prbs.collides(ul_prbs)) {
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if (bwp_pusch_slot.ul_prbs.collides(ul_grant)) {
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return alloc_result::sch_collision;
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return alloc_result::sch_collision;
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}
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}
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@ -435,6 +438,9 @@ alloc_result bwp_slot_allocator::alloc_pusch(slot_ue& ue, const prb_grant& ul_pr
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return alloc_result::no_cch_space;
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return alloc_result::no_cch_space;
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}
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}
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uint32_t coreset_id = ss[0]->coreset_id;
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uint32_t coreset_id = ss[0]->coreset_id;
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if (SRSRAN_SEARCH_SPACE_IS_COMMON(ss[0]->type)) {
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ul_grant &= prb_interval{ue->phy().pdcch.coreset[ss[0]->coreset_id].offset_rb, ue->phy().carrier.nof_prb};
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}
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if (not bwp_pdcch_slot.coresets[coreset_id].value().alloc_dci(
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if (not bwp_pdcch_slot.coresets[coreset_id].value().alloc_dci(
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pdcch_grant_type_t::ul_data, aggr_idx, ss[0]->id, &ue.cfg())) {
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pdcch_grant_type_t::ul_data, aggr_idx, ss[0]->id, &ue.cfg())) {
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// Could not find space in PDCCH
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// Could not find space in PDCCH
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@ -445,10 +451,10 @@ alloc_result bwp_slot_allocator::alloc_pusch(slot_ue& ue, const prb_grant& ul_pr
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if (ue.h_ul->empty()) {
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if (ue.h_ul->empty()) {
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int mcs = ue->fixed_pusch_mcs();
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int mcs = ue->fixed_pusch_mcs();
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bool success = ue.h_ul->new_tx(ue.pusch_slot, ue.pusch_slot, ul_prbs, mcs, ue->ue_cfg().maxharq_tx);
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bool success = ue.h_ul->new_tx(ue.pusch_slot, ue.pusch_slot, ul_grant, mcs, ue->ue_cfg().maxharq_tx);
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srsran_assert(success, "Failed to allocate UL HARQ");
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srsran_assert(success, "Failed to allocate UL HARQ");
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} else {
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} else {
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bool success = ue.h_ul->new_retx(ue.pusch_slot, ue.pusch_slot, ul_prbs);
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bool success = ue.h_ul->new_retx(ue.pusch_slot, ue.pusch_slot, ul_grant);
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srsran_assert(success, "Failed to allocate UL HARQ retx");
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srsran_assert(success, "Failed to allocate UL HARQ retx");
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}
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}
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@ -457,7 +463,7 @@ alloc_result bwp_slot_allocator::alloc_pusch(slot_ue& ue, const prb_grant& ul_pr
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fill_ul_dci_ue_fields(ue, *bwp_grid.cfg, ss[0]->id, pdcch.dci.ctx.location, pdcch.dci);
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fill_ul_dci_ue_fields(ue, *bwp_grid.cfg, ss[0]->id, pdcch.dci.ctx.location, pdcch.dci);
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pdcch.dci_cfg = ue->phy().get_dci_cfg();
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pdcch.dci_cfg = ue->phy().get_dci_cfg();
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// Generate PUSCH
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// Generate PUSCH
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bwp_pusch_slot.ul_prbs |= ul_prbs;
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bwp_pusch_slot.ul_prbs |= ul_grant;
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bwp_pusch_slot.ul.pusch.emplace_back();
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bwp_pusch_slot.ul.pusch.emplace_back();
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pusch_t& pusch = bwp_pusch_slot.ul.pusch.back();
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pusch_t& pusch = bwp_pusch_slot.ul.pusch.back();
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srsran_slot_cfg_t slot_cfg;
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srsran_slot_cfg_t slot_cfg;
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@ -22,7 +22,7 @@ namespace sched_nr_impl {
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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template <typename DciDlOrUl>
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template <typename DciDlOrUl>
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void fill_dci_common(const slot_ue& ue, const bwp_params_t& bwp_cfg, DciDlOrUl& dci)
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void fill_dci_common(const slot_ue& ue, const bwp_params_t& bwp_cfg, const srsran_dci_ctx_t& dci_ctx, DciDlOrUl& dci)
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{
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{
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const static uint32_t rv_idx[4] = {0, 2, 3, 1};
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const static uint32_t rv_idx[4] = {0, 2, 3, 1};
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@ -40,9 +40,16 @@ void fill_dci_common(const slot_ue& ue, const bwp_params_t& bwp_cfg, DciDlOrUl&
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const prb_grant& grant = h->prbs();
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const prb_grant& grant = h->prbs();
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if (grant.is_alloc_type0()) {
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if (grant.is_alloc_type0()) {
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dci.freq_domain_assigment = grant.rbgs().to_uint64();
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dci.freq_domain_assigment = grant.rbgs().to_uint64();
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if (SRSRAN_SEARCH_SPACE_IS_COMMON(dci_ctx.ss_type) and dci_ctx.coreset_start_rb > 0) {
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dci.freq_domain_assigment =
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(dci.freq_domain_assigment << dci_ctx.coreset_start_rb) & ((1U << grant.rbgs().size()) - 1);
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}
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} else {
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} else {
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dci.freq_domain_assigment =
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uint32_t rb_start = grant.prbs().start();
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srsran_ra_nr_type1_riv(bwp_cfg.cfg.rb_width, grant.prbs().start(), grant.prbs().length());
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if (SRSRAN_SEARCH_SPACE_IS_COMMON(dci_ctx.ss_type)) {
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rb_start -= dci_ctx.coreset_start_rb;
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}
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dci.freq_domain_assigment = srsran_ra_nr_type1_riv(bwp_cfg.cfg.rb_width, rb_start, grant.prbs().length());
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}
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}
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dci.time_domain_assigment = 0;
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dci.time_domain_assigment = 0;
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}
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}
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@ -51,13 +58,14 @@ bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params_t& bwp
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{
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{
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uint32_t cs_id = bwp_cfg.cfg.pdcch.ra_search_space.coreset_id;
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uint32_t cs_id = bwp_cfg.cfg.pdcch.ra_search_space.coreset_id;
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dci.mcs = 5;
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dci.ctx.format = srsran_dci_format_nr_1_0;
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dci.ctx.format = srsran_dci_format_nr_1_0;
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dci.ctx.ss_type = srsran_search_space_type_common_1;
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dci.ctx.ss_type = srsran_search_space_type_common_1;
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dci.ctx.rnti_type = srsran_rnti_type_ra;
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dci.ctx.rnti_type = srsran_rnti_type_ra;
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dci.ctx.rnti = ra_rnti;
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dci.ctx.rnti = ra_rnti;
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dci.ctx.coreset_id = cs_id;
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dci.ctx.coreset_id = cs_id;
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dci.ctx.coreset_start_rb = bwp_cfg.cfg.pdcch.coreset[cs_id].offset_rb;
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dci.ctx.coreset_start_rb = srsran_coreset_start_rb(&bwp_cfg.cfg.pdcch.coreset[cs_id]);
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dci.mcs = 5;
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if (bwp_cfg.cfg.pdcch.coreset_present[0] and cs_id == 0) {
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if (bwp_cfg.cfg.pdcch.coreset_present[0] and cs_id == 0) {
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dci.coreset0_bw = srsran_coreset_get_bw(&bwp_cfg.cfg.pdcch.coreset[cs_id]);
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dci.coreset0_bw = srsran_coreset_get_bw(&bwp_cfg.cfg.pdcch.coreset[cs_id]);
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}
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}
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@ -73,7 +81,6 @@ bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params_t& bwp
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bool fill_dci_msg3(const slot_ue& ue, const bwp_params_t& bwp_cfg, srsran_dci_ul_nr_t& msg3_dci)
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bool fill_dci_msg3(const slot_ue& ue, const bwp_params_t& bwp_cfg, srsran_dci_ul_nr_t& msg3_dci)
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{
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{
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fill_dci_common(ue, bwp_cfg, msg3_dci);
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msg3_dci.ctx.coreset_id = ue->phy().pdcch.ra_search_space.coreset_id;
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msg3_dci.ctx.coreset_id = ue->phy().pdcch.ra_search_space.coreset_id;
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msg3_dci.ctx.rnti_type = srsran_rnti_type_tc;
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msg3_dci.ctx.rnti_type = srsran_rnti_type_tc;
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msg3_dci.ctx.rnti = ue->rnti;
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msg3_dci.ctx.rnti = ue->rnti;
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@ -83,6 +90,7 @@ bool fill_dci_msg3(const slot_ue& ue, const bwp_params_t& bwp_cfg, srsran_dci_ul
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} else {
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} else {
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msg3_dci.ctx.format = srsran_dci_format_nr_0_0;
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msg3_dci.ctx.format = srsran_dci_format_nr_0_0;
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}
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}
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fill_dci_common(ue, bwp_cfg, msg3_dci.ctx, msg3_dci);
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return true;
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return true;
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}
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}
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@ -98,7 +106,7 @@ void fill_dl_dci_ue_fields(const slot_ue& ue,
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bool ret = ue->phy().get_dci_ctx_pdsch_rnti_c(ss_id, dci_pos, ue->rnti, dci.ctx);
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bool ret = ue->phy().get_dci_ctx_pdsch_rnti_c(ss_id, dci_pos, ue->rnti, dci.ctx);
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srsran_assert(ret, "Invalid DL DCI format");
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srsran_assert(ret, "Invalid DL DCI format");
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fill_dci_common(ue, bwp_cfg, dci);
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fill_dci_common(ue, bwp_cfg, dci.ctx, dci);
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if (dci.ctx.format == srsran_dci_format_nr_1_0) {
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if (dci.ctx.format == srsran_dci_format_nr_1_0) {
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dci.harq_feedback = (ue.uci_slot - ue.pdsch_slot) - 1;
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dci.harq_feedback = (ue.uci_slot - ue.pdsch_slot) - 1;
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} else {
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} else {
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@ -115,7 +123,7 @@ void fill_ul_dci_ue_fields(const slot_ue& ue,
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bool ret = ue->phy().get_dci_ctx_pusch_rnti_c(ss_id, dci_pos, ue->rnti, dci.ctx);
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bool ret = ue->phy().get_dci_ctx_pusch_rnti_c(ss_id, dci_pos, ue->rnti, dci.ctx);
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srsran_assert(ret, "Invalid DL DCI format");
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srsran_assert(ret, "Invalid DL DCI format");
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fill_dci_common(ue, bwp_cfg, dci);
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fill_dci_common(ue, bwp_cfg, dci.ctx, dci);
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}
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}
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void log_sched_slot_ues(srslog::basic_logger& logger, slot_point pdcch_slot, uint32_t cc, const slot_ue_map_t& slot_ues)
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void log_sched_slot_ues(srslog::basic_logger& logger, slot_point pdcch_slot, uint32_t cc, const slot_ue_map_t& slot_ues)
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