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srsLTE
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use of a common tti_params struct to store all values derived from tti_rx

This commit is contained in:
Francisco Paisana 2019-11-28 15:41:56 +00:00
parent b4b1ab94af
commit 7990e2f563
4 changed files with 63 additions and 61 deletions
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18
srsenb/hdr/stack/mac/scheduler_carrier.h
View File

@ -88,14 +88,14 @@ public:
void generate_dcis();
// dl_tti_sched itf
alloc_outcome_t alloc_dl_user(sched_ue* user, const rbgmask_t& user_mask, uint32_t pid) final;
uint32_t get_tti_tx_dl() const final { return tti_alloc.get_tti_tx_dl(); }
uint32_t get_tti_tx_dl() const final { return tti_params.tti_tx_dl; }
uint32_t get_nof_ctrl_symbols() const final;
const rbgmask_t& get_dl_mask() const final { return tti_alloc.get_dl_mask(); }
// ul_tti_sched itf
alloc_outcome_t alloc_ul_user(sched_ue* user, ul_harq_proc::ul_alloc_t alloc) final;
alloc_outcome_t alloc_ul_msg3(sched_ue* user, ul_harq_proc::ul_alloc_t alloc, uint32_t mcs);
const prbmask_t& get_ul_mask() const final { return tti_alloc.get_ul_mask(); }
uint32_t get_tti_tx_ul() const final { return tti_alloc.get_tti_tx_ul(); }
uint32_t get_tti_tx_ul() const final { return tti_params.tti_tx_ul; }
// getters
const pdcch_mask_t& get_pdcch_mask() const { return pdcch_mask; }
@ -103,9 +103,9 @@ public:
prbmask_t& get_ul_mask() { return tti_alloc.get_ul_mask(); }
const std::vector<ul_alloc_t>& get_ul_allocs() const { return ul_data_allocs; }
uint32_t get_cfi() const { return tti_alloc.get_cfi(); }
uint32_t get_tti_rx() const { return tti_alloc.get_tti_rx(); }
uint32_t get_sfn() const { return tti_alloc.get_sfn(); }
uint32_t get_sf_idx() const { return tti_alloc.get_sf_idx(); }
uint32_t get_tti_rx() const { return tti_params.tti_rx; }
uint32_t get_sfn() const { return tti_params.sfn; }
uint32_t get_sf_idx() const { return tti_params.sf_idx; }
private:
bool is_dl_alloc(sched_ue* user) const final;
@ -130,9 +130,9 @@ public:
carrier_sched* parent_carrier = nullptr;
sched_params_t* sched_params = nullptr;
srslte::log* log_h = nullptr;
cell_cfg_sib_t* sibs_cfg = nullptr;
// internal state
tti_params_t tti_params{10241};
tti_grid_t tti_alloc;
std::vector<rar_alloc_t> rar_allocs;
std::vector<bc_alloc_t> bc_allocs;
@ -166,9 +166,9 @@ public:
prbmask_t pucch_mask;
// TTI result storage and management
std::array<tti_sched_result_t, 10> tti_scheds;
tti_sched_result_t* get_tti_sched(uint32_t tti_rx) { return &tti_scheds[tti_rx % tti_scheds.size()]; }
std::vector<uint8_t> tti_dl_mask; ///< Some TTIs may be forbidden for DL sched due to MBMS
std::array<tti_sched_result_t, TTIMOD_SZ> tti_scheds;
tti_sched_result_t* get_tti_sched(uint32_t tti_rx) { return &tti_scheds[tti_rx % tti_scheds.size()]; }
std::vector<uint8_t> tti_dl_mask; ///< Some TTIs may be forbidden for DL sched due to MBMS
std::unique_ptr<bc_sched> bc_sched_ptr;
std::unique_ptr<ra_sched> ra_sched_ptr;

47
srsenb/hdr/stack/mac/scheduler_grid.h
View File

@ -41,7 +41,17 @@ struct alloc_outcome_t {
alloc_outcome_t(result_enum e) : result(e) {}
operator result_enum() { return result; }
operator bool() { return result == SUCCESS; }
const char* to_string() const;
const char* to_string() const;
};
//! Params relative to a single TTI
struct tti_params_t {
uint32_t tti_rx;
uint32_t tti_tx_dl;
uint32_t tti_tx_ul;
uint32_t sf_idx;
uint32_t sfn;
explicit tti_params_t(uint32_t tti_rx_);
};
//! Class responsible for managing a PDCCH CCE grid, namely cce allocs, and avoid collisions.
@ -51,13 +61,13 @@ public:
struct alloc_t {
uint16_t rnti = 0;
srslte_dci_location_t dci_pos = {0, 0};
pdcch_mask_t current_mask;
pdcch_mask_t total_mask;
pdcch_mask_t current_mask; ///< this PDCCH alloc mask
pdcch_mask_t total_mask; ///< Accumulation of all PDCCH masks for the current solution (tree route)
};
using alloc_result_t = std::vector<const alloc_t*>;
void init(const sched_params_t& sched_params);
void new_tti(uint32_t tti_rx_, uint32_t start_cfi);
void new_tti(const tti_params_t& tti_params_, uint32_t start_cfi);
bool alloc_dci(alloc_type_t alloc_type, uint32_t aggr_idx, sched_ue* user = nullptr);
bool set_cfi(uint32_t cfi);
@ -68,7 +78,6 @@ public:
size_t nof_allocs() const { return nof_dci_allocs; }
size_t nof_alloc_combinations() const { return prev_end - prev_start; }
std::string result_to_string(bool verbose = false) const;
uint32_t get_sf_idx() const { return sf_idx; }
private:
const static uint32_t nof_cfis = 3;
@ -87,8 +96,7 @@ private:
srslte::log* log_h = nullptr;
// tti vars
uint32_t tti_rx = 0;
uint32_t sf_idx = 0;
const tti_params_t* tti_params = nullptr;
uint32_t current_cfix = 0;
size_t prev_start = 0, prev_end = 0;
std::vector<tree_node_t> dci_alloc_tree;
@ -104,42 +112,33 @@ public:
rbg_range_t rbg_range;
};
void init(const sched_params_t& sched_params_);
void new_tti(uint32_t tti_rx_, uint32_t start_cfi);
void init(const sched_params_t& sched_params_, uint32_t cc_idx_);
void new_tti(const tti_params_t& tti_params_, uint32_t start_cfi);
dl_ctrl_alloc_t alloc_dl_ctrl(uint32_t aggr_lvl, alloc_type_t alloc_type);
alloc_outcome_t alloc_dl_data(sched_ue* user, const rbgmask_t& user_mask);
alloc_outcome_t alloc_ul_data(sched_ue* user, ul_harq_proc::ul_alloc_t alloc, bool needs_pdcch);
// getters
uint32_t get_avail_rbgs() const { return avail_rbg; }
rbgmask_t& get_dl_mask() { return dl_mask; }
const rbgmask_t& get_dl_mask() const { return dl_mask; }
prbmask_t& get_ul_mask() { return ul_mask; }
const prbmask_t& get_ul_mask() const { return ul_mask; }
uint32_t get_cfi() const { return pdcch_alloc.get_cfi(); }
const pdcch_grid_t& get_pdcch_grid() const { return pdcch_alloc; }
uint32_t get_tti_rx() const { return tti_rx; }
uint32_t get_tti_tx_dl() const { return tti_tx_dl; }
uint32_t get_tti_tx_ul() const { return tti_tx_ul; }
uint32_t get_sfn() const { return sfn; }
uint32_t get_sf_idx() const { return pdcch_alloc.get_sf_idx(); }
private:
alloc_outcome_t alloc_dl(uint32_t aggr_lvl, alloc_type_t alloc_type, rbgmask_t alloc_mask, sched_ue* user = nullptr);
// consts
const sched_params_t* sched_params = nullptr;
srslte::log* log_h = nullptr;
sched_interface::cell_cfg_t* cell_cfg = nullptr;
uint32_t nof_prbs = 0;
uint32_t nof_rbgs = 0;
uint32_t si_n_rbg = 0, rar_n_rbg = 0;
const sched_params_t* sched_params = nullptr;
srslte::log* log_h = nullptr;
uint32_t nof_rbgs = 0;
uint32_t si_n_rbg = 0, rar_n_rbg = 0;
uint32_t cc_idx = 0;
// tti const
uint32_t tti_rx = 10241;
const tti_params_t* tti_params = nullptr;
// derived
uint32_t tti_tx_dl = 0, tti_tx_ul = 0;
uint32_t sfn = 0;
pdcch_grid_t pdcch_alloc = {};
// internal state

14
srsenb/src/stack/mac/scheduler_carrier.cc
View File

@ -37,13 +37,13 @@ void sched::carrier_sched::tti_sched_result_t::init(carrier_sched* carrier_)
parent_carrier = carrier_;
sched_params = &carrier_->sched_ptr->sched_params;
log_h = sched_params->log_h;
sibs_cfg = sched_params->cfg->sibs;
tti_alloc.init(*sched_params);
tti_alloc.init(*sched_params, 0);
}
void sched::carrier_sched::tti_sched_result_t::new_tti(uint32_t tti_rx_, uint32_t start_cfi)
{
tti_alloc.new_tti(tti_rx_, start_cfi);
tti_params = tti_params_t{tti_rx_};
tti_alloc.new_tti(tti_params, start_cfi);
// internal state
rar_allocs.clear();
@ -110,7 +110,7 @@ sched::carrier_sched::tti_sched_result_t::alloc_dl_ctrl(uint32_t aggr_lvl, uint3
alloc_outcome_t
sched::carrier_sched::tti_sched_result_t::alloc_bc(uint32_t aggr_lvl, uint32_t sib_idx, uint32_t sib_ntx)
{
uint32_t sib_len = sibs_cfg[sib_idx].len;
uint32_t sib_len = sched_params->cfg->sibs[sib_idx].len;
uint32_t rv = get_rvidx(sib_ntx);
ctrl_code_t ret = alloc_dl_ctrl(aggr_lvl, sib_len, SRSLTE_SIRNTI);
if (not ret.first) {
@ -291,7 +291,7 @@ void sched::carrier_sched::tti_sched_result_t::set_bc_sched_result(const pdcch_g
bc->dci.location.ncce,
bc_alloc.rv,
bc_alloc.req_bytes,
sibs_cfg[bc_alloc.sib_idx].period_rf,
sched_params->cfg->sibs[bc_alloc.sib_idx].period_rf,
bc->dci.tb[0].mcs_idx);
} else {
// Paging
@ -512,7 +512,7 @@ void sched::carrier_sched::tti_sched_result_t::generate_dcis()
uint32_t sched::carrier_sched::tti_sched_result_t::get_nof_ctrl_symbols() const
{
return tti_alloc.get_cfi() + ((parent_carrier->cfg->cell.nof_prb <= 10) ? 1 : 0);
return tti_alloc.get_cfi() + ((sched_params->cfg->cell.nof_prb <= 10) ? 1 : 0);
}
int sched::carrier_sched::tti_sched_result_t::generate_format1a(uint32_t rb_start,
@ -554,7 +554,7 @@ int sched::carrier_sched::tti_sched_result_t::generate_format1a(uint32_t
dci->alloc_type = SRSLTE_RA_ALLOC_TYPE2;
dci->type2_alloc.mode = srslte_ra_type2_t::SRSLTE_RA_TYPE2_LOC;
dci->type2_alloc.riv = srslte_ra_type2_to_riv(l_crb, rb_start, parent_carrier->cfg->cell.nof_prb);
dci->type2_alloc.riv = srslte_ra_type2_to_riv(l_crb, rb_start, sched_params->cfg->cell.nof_prb);
dci->pid = 0;
dci->tb[0].mcs_idx = mcs;
dci->tb[0].rv = rv;

45
srsenb/src/stack/mac/scheduler_grid.cc
View File

@ -40,6 +40,15 @@ const char* alloc_outcome_t::to_string() const
return "unknown error";
}
tti_params_t::tti_params_t(uint32_t tti_rx_) :
tti_rx(tti_rx_),
sf_idx(TTI_TX(tti_rx) % 10),
tti_tx_dl(TTI_TX(tti_rx)),
tti_tx_ul(TTI_RX_ACK(tti_rx)),
sfn(TTI_TX(tti_rx) / 10)
{
}
/*******************************************************
* PDCCH Allocation Methods
*******************************************************/
@ -52,10 +61,9 @@ void pdcch_grid_t::init(const sched_params_t& sched_params_)
reset();
}
void pdcch_grid_t::new_tti(uint32_t tti_rx_, uint32_t start_cfi)
void pdcch_grid_t::new_tti(const tti_params_t& tti_params_, uint32_t start_cfi)
{
tti_rx = tti_rx_;
sf_idx = TTI_TX(tti_rx) % 10;
tti_params = &tti_params_;
current_cfix = start_cfi - 1;
reset();
}
@ -68,11 +76,11 @@ const sched_ue::sched_dci_cce_t* pdcch_grid_t::get_cce_loc_table(alloc_type_t al
case alloc_type_t::DL_PCCH:
return &sched_params->common_locations[current_cfix];
case alloc_type_t::DL_RAR:
return &sched_params->rar_locations[current_cfix][sf_idx];
return &sched_params->rar_locations[current_cfix][tti_params->sf_idx];
case alloc_type_t::DL_DATA:
return user->get_locations(current_cfix + 1, sf_idx);
return user->get_locations(current_cfix + 1, tti_params->sf_idx);
case alloc_type_t::UL_DATA:
return user->get_locations(current_cfix + 1, sf_idx);
return user->get_locations(current_cfix + 1, tti_params->sf_idx);
}
return nullptr;
}
@ -131,7 +139,7 @@ void pdcch_grid_t::update_alloc_tree(int parent_nod
for (uint32_t i = 0; i < nof_locs; ++i) {
uint32_t startpos = dci_locs->cce_start[aggr_idx][i];
if (alloc_type == alloc_type_t::DL_DATA and user->pucch_sr_collision(TTI_TX(tti_rx), startpos)) {
if (alloc_type == alloc_type_t::DL_DATA and user->pucch_sr_collision(tti_params->tti_tx_dl, startpos)) {
// will cause a collision in the PUCCH
continue;
}
@ -250,35 +258,29 @@ std::string pdcch_grid_t::result_to_string(bool verbose) const
* TTI resource Scheduling Methods
*******************************************************/
void tti_grid_t::init(const sched_params_t& sched_params_)
void tti_grid_t::init(const sched_params_t& sched_params_, uint32_t cc_idx_)
{
sched_params = &sched_params_;
log_h = sched_params->log_h;
cell_cfg = sched_params->cfg;
nof_prbs = cell_cfg->cell.nof_prb;
nof_rbgs = sched_params->nof_rbgs;
si_n_rbg = srslte::ceil_div(4, sched_params->P);
rar_n_rbg = srslte::ceil_div(3, sched_params->P);
cc_idx = cc_idx_;
pdcch_alloc.init(*sched_params);
}
void tti_grid_t::new_tti(uint32_t tti_rx_, uint32_t start_cfi)
void tti_grid_t::new_tti(const tti_params_t& tti_params_, uint32_t start_cfi)
{
tti_rx = tti_rx_;
// derived
tti_tx_dl = TTI_TX(tti_rx);
tti_tx_ul = TTI_RX_ACK(tti_rx);
sfn = tti_tx_dl / 10;
tti_params = &tti_params_;
// internal state
avail_rbg = nof_rbgs;
dl_mask.reset();
dl_mask.resize(nof_rbgs);
ul_mask.reset();
ul_mask.resize(nof_prbs);
pdcch_alloc.new_tti(tti_rx, start_cfi);
ul_mask.resize(sched_params->cfg->cell.nof_prb);
pdcch_alloc.new_tti(*tti_params, start_cfi);
}
//! Allocates CCEs and RBs for the given mask and allocation type (e.g. data, BC, RAR, paging)
@ -335,7 +337,8 @@ tti_grid_t::dl_ctrl_alloc_t tti_grid_t::alloc_dl_ctrl(uint32_t aggr_lvl, alloc_t
alloc_outcome_t tti_grid_t::alloc_dl_data(sched_ue* user, const rbgmask_t& user_mask)
{
srslte_dci_format_t dci_format = user->get_dci_format();
uint32_t aggr_level = user->get_aggr_level(srslte_dci_format_sizeof(&cell_cfg->cell, nullptr, nullptr, dci_format));
uint32_t aggr_level =
user->get_aggr_level(srslte_dci_format_sizeof(&sched_params->cfg->cell, nullptr, nullptr, dci_format));
return alloc_dl(aggr_level, alloc_type_t::DL_DATA, user_mask, user);
}
@ -354,7 +357,7 @@ alloc_outcome_t tti_grid_t::alloc_ul_data(sched_ue* user, ul_harq_proc::ul_alloc
// Generate PDCCH except for RAR and non-adaptive retx
if (needs_pdcch) {
uint32_t aggr_idx =
user->get_aggr_level(srslte_dci_format_sizeof(&cell_cfg->cell, nullptr, nullptr, SRSLTE_DCI_FORMAT0));
user->get_aggr_level(srslte_dci_format_sizeof(&sched_params->cfg->cell, nullptr, nullptr, SRSLTE_DCI_FORMAT0));
if (not pdcch_alloc.alloc_dci(alloc_type_t::UL_DATA, aggr_idx, user)) {
if (log_h->get_level() == srslte::LOG_LEVEL_DEBUG) {
log_h->debug("No space in PDCCH for rnti=0x%x UL tx. Current PDCCH allocation: %s\n",