diff --git a/lib/include/srsran/common/phy_cfg_nr_default.h b/lib/include/srsran/common/phy_cfg_nr_default.h index eff787dc2..953086ca8 100644 --- a/lib/include/srsran/common/phy_cfg_nr_default.h +++ b/lib/include/srsran/common/phy_cfg_nr_default.h @@ -39,15 +39,22 @@ public: */ R_CARRIER_CUSTOM_20MHZ, R_CARRIER_COUNT - } carrier = R_CARRIER_CUSTOM_10MHZ; - const std::vector R_CARRIER_STRING = {"10MHz", "20MHz", "Invalid"}; + } carrier = R_CARRIER_CUSTOM_10MHZ; + const std::array R_CARRIER_STRING = {"10MHz", "20MHz"}; enum { /** * @brief TDD custom reference 5 slot DL and 5 slot UL */ R_TDD_CUSTOM_6_4 = 0, - } tdd = R_TDD_CUSTOM_6_4; + + /** + * @brief TDD pattern FR1.15-1 defined in TS38.101-4 Table A.1.2-1 + */ + R_TDD_FR1_15_1, + R_TDD_COUNT, + } tdd = R_TDD_CUSTOM_6_4; + const std::array R_TDD_STRING = {"6D+4U", "FR1.15-1"}; enum { /** @@ -77,8 +84,8 @@ public: */ R_PDSCH_COUNT - } pdsch = R_PDSCH_DEFAULT; - const std::vector R_PDSCH_STRING = {"default", "ts38101/5.2-1", "Invalid"}; + } pdsch = R_PDSCH_DEFAULT; + const std::array R_PDSCH_STRING = {"default", "ts38101/5.2-1"}; enum { /** @@ -138,6 +145,7 @@ private: * TDD make helper methods */ static void make_tdd_custom_6_4(srsran_tdd_config_nr_t& tdd); + static void make_tdd_fr1_15_1(srsran_tdd_config_nr_t& tdd); /** * PDCCH make helper methods diff --git a/lib/src/common/phy_cfg_nr_default.cc b/lib/src/common/phy_cfg_nr_default.cc index b0668f4aa..1c1eca71e 100644 --- a/lib/src/common/phy_cfg_nr_default.cc +++ b/lib/src/common/phy_cfg_nr_default.cc @@ -44,6 +44,13 @@ phy_cfg_nr_default_t::reference_cfg_t::reference_cfg_t(const std::string& args) } } srsran_assert(carrier != R_CARRIER_COUNT, "Invalid carrier reference configuration '%s'", param.back().c_str()); + } else if (param.front() == "tdd") { + for (tdd = R_TDD_CUSTOM_6_4; tdd < R_TDD_COUNT; tdd = inc(tdd)) { + if (R_TDD_STRING[tdd] == param.back()) { + break; + } + } + srsran_assert(tdd != R_TDD_COUNT, "Invalid TDD reference configuration '%s'", param.back().c_str()); } else if (param.front() == "pdsch") { for (pdsch = R_PDSCH_DEFAULT; pdsch < R_PDSCH_COUNT; pdsch = inc(pdsch)) { if (R_PDSCH_STRING[pdsch] == param.back()) { @@ -91,6 +98,18 @@ void phy_cfg_nr_default_t::make_tdd_custom_6_4(srsran_tdd_config_nr_t& tdd) tdd.pattern2.period_ms = 0; } +void phy_cfg_nr_default_t::make_tdd_fr1_15_1(srsran_tdd_config_nr_t& tdd) +{ + tdd.pattern1.period_ms = 5; + tdd.pattern1.nof_dl_slots = 3; + tdd.pattern1.nof_dl_symbols = 10; + tdd.pattern1.nof_ul_slots = 1; + tdd.pattern1.nof_ul_symbols = 2; + + // Disable pattern 2 + tdd.pattern2.period_ms = 0; +} + void phy_cfg_nr_default_t::make_pdcch_custom_common_ss(srsran_pdcch_cfg_nr_t& pdcch, const srsran_carrier_nr_t& carrier) { // Configure CORESET ID 1 @@ -253,7 +272,7 @@ void phy_cfg_nr_default_t::make_pucch_custom_one(srsran_pucch_nr_hl_cfg_t& pucch resource_big.format = SRSRAN_PUCCH_NR_FORMAT_2; resource_big.nof_prb = 1; resource_big.nof_symbols = 2; - resource_big.start_symbol_idx = 0; + resource_big.start_symbol_idx = 12; // Resource for SR srsran_pucch_nr_resource_t resource_sr = {}; @@ -302,11 +321,14 @@ void phy_cfg_nr_default_t::make_harq_auto(srsran_harq_ack_cfg_hl_t& harq, { // Generate as many entries as DL slots harq.nof_dl_data_to_ul_ack = SRSRAN_MIN(tdd_cfg.pattern1.nof_dl_slots, SRSRAN_MAX_NOF_DL_DATA_TO_UL); + if (tdd_cfg.pattern1.nof_dl_symbols > 0) { + harq.nof_dl_data_to_ul_ack++; + } // Set PDSCH to ACK timing delay to 4 or more for (uint32_t n = 0; n < harq.nof_dl_data_to_ul_ack; n++) { // Set the first slots into the first UL slot - if (n < (harq.nof_dl_data_to_ul_ack - 4)) { + if (harq.nof_dl_data_to_ul_ack >= 4 and n < (harq.nof_dl_data_to_ul_ack - 4)) { harq.dl_data_to_ul_ack[n] = harq.nof_dl_data_to_ul_ack - n; continue; } @@ -318,7 +340,7 @@ void phy_cfg_nr_default_t::make_harq_auto(srsran_harq_ack_cfg_hl_t& harq, } // Otherwise set delay to the first UL slot of the next TDD period - harq.dl_data_to_ul_ack[n] = 2 * harq.nof_dl_data_to_ul_ack - n; + harq.dl_data_to_ul_ack[n] = (tdd_cfg.pattern1.period_ms + tdd_cfg.pattern1.nof_dl_slots) - n; } // Zero the rest @@ -355,6 +377,11 @@ phy_cfg_nr_default_t::phy_cfg_nr_default_t(const reference_cfg_t& reference_cfg) case reference_cfg_t::R_TDD_CUSTOM_6_4: make_tdd_custom_6_4(tdd); break; + case reference_cfg_t::R_TDD_FR1_15_1: + make_tdd_fr1_15_1(tdd); + break; + case reference_cfg_t::R_TDD_COUNT: + srsran_terminate("Invalid TDD reference"); } switch (reference_cfg.pdcch) { diff --git a/test/phy/CMakeLists.txt b/test/phy/CMakeLists.txt index 0a3fabd72..36d24b555 100644 --- a/test/phy/CMakeLists.txt +++ b/test/phy/CMakeLists.txt @@ -25,53 +25,50 @@ if (RF_FOUND AND ENABLE_SRSUE AND ENABLE_SRSENB) ${Boost_LIBRARIES} ${ATOMIC_LIBS}) - add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_dl_default nr_phy_test - --reference=carrier=${NR_PHY_TEST_BW} - --duration=100 - --gnb.stack.pdsch.slots=0,1,2,3,4,5 - --gnb.stack.pusch.slots=none - --gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS} - --ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS} - ) + foreach (NR_PHY_TEST_TDD "6D+4U" "FR1.15-1") + set(NR_PHY_TEST_DURATION_MS 20) - add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_ts38101/5.2-1 nr_phy_test - --reference=carrier=${NR_PHY_TEST_BW},pdsch=ts38101/5.2-1 - --duration=100 - --gnb.stack.pdsch.mcs=27 - --gnb.stack.pdsch.start=0 - --gnb.stack.pdsch.length=52 - --gnb.stack.pdsch.slots=0,1,2,3,4,5 - --gnb.stack.pusch.slots=none - --gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS} - --ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS} - ) + foreach (NR_PHY_TEST_PDSCH "default" "ts38101/5.2-1") + add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_${NR_PHY_TEST_TDD}_dl_${NR_PHY_TEST_PDSCH} nr_phy_test + --reference=carrier=${NR_PHY_TEST_BW},tdd=${NR_PHY_TEST_TDD},pdsch=${NR_PHY_TEST_PDSCH} + --duration=${NR_PHY_TEST_DURATION_MS} + --gnb.stack.pdsch.slots=0,1,2,3,4,5 # All possible DL slots + --gnb.stack.pdsch.start=0 # Start at RB 0 + --gnb.stack.pdsch.length=52 # Full 10 MHz BW + --gnb.stack.pdsch.mcs=28 # Maximum MCS + --gnb.stack.pusch.slots=none + --gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS} + --ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS} + ) + endforeach () - add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_ul_only nr_phy_test - --reference=carrier=${NR_PHY_TEST_BW} - --duration=100 # 100 slots - --gnb.stack.pdsch.slots=6 # No PDSCH - --gnb.stack.pusch.slots=6,7,8,9 # All possible UL slots - --gnb.stack.pusch.start=0 # Start at RB 0 - --gnb.stack.pusch.length=52 # Full 10 MHz BW - --gnb.stack.pusch.mcs=28 # Maximum MCS - --gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS} - --ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS} - ) + add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_${NR_PHY_TEST_TDD}_ul_only nr_phy_test + --reference=carrier=${NR_PHY_TEST_BW},tdd=${NR_PHY_TEST_TDD} + --duration=${NR_PHY_TEST_DURATION_MS} + --gnb.stack.pdsch.slots=6 # No PDSCH + --gnb.stack.pusch.slots=6,7,8,9 # All possible UL slots + --gnb.stack.pusch.start=0 # Start at RB 0 + --gnb.stack.pusch.length=52 # Full 10 MHz BW + --gnb.stack.pusch.mcs=28 # Maximum MCS + --gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS} + --ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS} + ) - add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_bidir nr_phy_test - --reference=carrier=${NR_PHY_TEST_BW} - --duration=100 # 100 slots - --gnb.stack.pdsch.slots=0,1,2,3,4,5 # All possible DL slots - --gnb.stack.pdsch.start=0 # Start at RB 0 - --gnb.stack.pdsch.length=52 # Full 10 MHz BW - --gnb.stack.pdsch.mcs=28 # Maximum MCS - --gnb.stack.pusch.slots=6,7,8,9 # All possible UL slots - --gnb.stack.pusch.start=0 # Start at RB 0 - --gnb.stack.pusch.length=52 # Full 10 MHz BW - --gnb.stack.pusch.mcs=28 # Maximum MCS - --gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS} - --ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS} - ) + add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_${NR_PHY_TEST_TDD}_bidir nr_phy_test + --reference=carrier=${NR_PHY_TEST_BW},tdd=${NR_PHY_TEST_TDD} + --duration=${NR_PHY_TEST_DURATION_MS} + --gnb.stack.pdsch.slots=0,1,2,3,4,5 # All possible DL slots + --gnb.stack.pdsch.start=0 # Start at RB 0 + --gnb.stack.pdsch.length=52 # Full 10 MHz BW + --gnb.stack.pdsch.mcs=28 # Maximum MCS + --gnb.stack.pusch.slots=6,7,8,9 # All possible UL slots + --gnb.stack.pusch.start=0 # Start at RB 0 + --gnb.stack.pusch.length=52 # Full 10 MHz BW + --gnb.stack.pusch.mcs=28 # Maximum MCS + --gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS} + --ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS} + ) + endforeach () add_nr_test(nr_phy_test_10MHz_bidir_sched nr_phy_test --duration=100 # 100 slots diff --git a/test/phy/dummy_gnb_stack.h b/test/phy/dummy_gnb_stack.h index 0c9e30bff..ce93fc6b0 100644 --- a/test/phy/dummy_gnb_stack.h +++ b/test/phy/dummy_gnb_stack.h @@ -393,7 +393,7 @@ public: // Setup DL Data to ACK timing for (uint32_t i = 0; i < SRSRAN_NOF_SF_X_FRAME; i++) { - dl_data_to_ul_ack[i] = args.phy_cfg.harq_ack.dl_data_to_ul_ack[i % SRSRAN_MAX_NOF_DL_DATA_TO_UL]; + dl_data_to_ul_ack[i] = args.phy_cfg.harq_ack.dl_data_to_ul_ack[i % args.phy_cfg.tdd.pattern1.period_ms]; } // If reached this point the configuration is valid