mirror of https://github.com/PentHertz/srsLTE.git
extended resource allocation for NR
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@ -155,6 +155,18 @@ typedef enum SRSLTE_API {
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srslte_dci_format_nr_2_3 ///< @brief Transmission of a group of TPC commands for SRS transmissions by one or more UEs
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srslte_dci_format_nr_2_3 ///< @brief Transmission of a group of TPC commands for SRS transmissions by one or more UEs
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} srslte_dci_format_nr_t;
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} srslte_dci_format_nr_t;
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/**
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* @brief Overhead configuration provided by higher layers
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* @remark Described in TS 38.331 V15.10.0 PDSCH-ServingCellConfig
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* @remark Described in TS 38.331 V15.10.0 PUSCH-ServingCellConfig
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*/
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typedef enum SRSLTE_API {
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srslte_xoverhead_0 = 0,
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srslte_xoverhead_6,
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srslte_xoverhead_12,
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srslte_xoverhead_18
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} srslte_xoverhead_t;
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/**
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/**
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* @brief NR carrier parameters. It is a combination of fixed cell and bandwidth-part (BWP)
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* @brief NR carrier parameters. It is a combination of fixed cell and bandwidth-part (BWP)
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*/
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*/
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@ -236,6 +248,15 @@ typedef struct SRSLTE_API {
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uint32_t n_cce;
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uint32_t n_cce;
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} srslte_pdcch_cfg_nr_t;
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} srslte_pdcch_cfg_nr_t;
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typedef struct SRSLTE_API {
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uint32_t max_mimo_layers; ///< @brief DL: Indicates the maximum number of MIMO layers to be used for PDSCH in all BWPs
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///< of this serving cell. (see TS 38.212 [17], clause 5.4.2.1). UL: Indicates the maximum
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///< MIMO layer to be used for PUSCH in all BWPs of the normal UL of this serving cell (see
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///< TS 38.212 [17], clause 5.4.2.1)
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srslte_xoverhead_t xoverhead; ///< Accounts for overhead from CSI-RS, CORESET, etc. If the field is absent, the UE
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///< applies value xOh0 (see TS 38.214 [19], clause 5.1.3.2).
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} srslte_serving_cell_cfg_t;
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/**
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/**
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* @brief Calculates the bandwidth of a given CORESET in physical resource blocks (PRB) . This function uses the
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* @brief Calculates the bandwidth of a given CORESET in physical resource blocks (PRB) . This function uses the
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* frequency domain resources bit-map for counting the number of PRB.
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* frequency domain resources bit-map for counting the number of PRB.
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@ -32,7 +32,6 @@
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#include "srslte/phy/common/phy_common_nr.h"
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#include "srslte/phy/common/phy_common_nr.h"
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#include "srslte/phy/fec/softbuffer.h"
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#include "srslte/phy/fec/softbuffer.h"
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#include "srslte/phy/phch/ra.h"
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/**
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/**
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* @brief PDSCH DMRS type
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* @brief PDSCH DMRS type
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@ -151,6 +150,10 @@ typedef struct SRSLTE_API {
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srslte_pdsch_dmrs_cfg_t dmrs_cfg_typeA;
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srslte_pdsch_dmrs_cfg_t dmrs_cfg_typeA;
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srslte_pdsch_dmrs_cfg_t dmrs_cfg_typeB;
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srslte_pdsch_dmrs_cfg_t dmrs_cfg_typeB;
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srslte_mcs_table_t mcs_table;
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srslte_mcs_table_t mcs_table;
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/// Parameters provided by PDSCH-ServingCellConfig
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srslte_serving_cell_cfg_t serving_cell_cfg;
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} srslte_pdsch_cfg_nr_t;
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} srslte_pdsch_cfg_nr_t;
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#endif // SRSLTE_PDSCH_CFG_NR_H
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#endif // SRSLTE_PDSCH_CFG_NR_H
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@ -43,7 +43,9 @@
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typedef struct SRSLTE_API {
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typedef struct SRSLTE_API {
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srslte_mod_t mod;
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srslte_mod_t mod;
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int tbs;
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uint32_t N_L; ///< the number of transmission layers that the transport block is mapped onto
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int tbs; ///< Payload size, TS 38.212 refers to it as A
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double R; ///< Target LDPC rate
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int rv;
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int rv;
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uint32_t nof_bits;
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uint32_t nof_bits;
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uint32_t cw_idx;
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uint32_t cw_idx;
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@ -51,9 +53,27 @@ typedef struct SRSLTE_API {
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// this is for debugging and metrics purposes
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// this is for debugging and metrics purposes
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uint32_t mcs_idx;
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uint32_t mcs_idx;
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/// Soft-buffers pointers
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union {
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srslte_softbuffer_tx_t* tx;
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srslte_softbuffer_rx_t* rx;
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} softbuffer;
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} srslte_ra_tb_nr_t;
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} srslte_ra_tb_nr_t;
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SRSLTE_API int
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/**
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srslte_ra_nr_tbs(const srslte_pdsch_cfg_nr_t* pdsch_cfg, const srslte_pdsch_grant_nr_t* grant, uint32_t mcs_idx);
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* @brief Calculates shared channel TBS
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* @param N_re Number of resource elements
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* @param S TB scaling, used in rare occasions. Set to 1, 0, NAN or INF if unused.
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* @param R Target Rate
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* @param Qm Modulation level
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* @param nof_layers Number of layers
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* @return The transport block size
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*/
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SRSLTE_API uint32_t srslte_ra_nr_tbs(uint32_t N_re, double S, double R, uint32_t Qm, uint32_t nof_layers);
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SRSLTE_API int srslte_ra_nr_fill_tb(const srslte_pdsch_cfg_nr_t* pdsch_cfg,
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const srslte_pdsch_grant_nr_t* grant,
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uint32_t mcs_idx,
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srslte_ra_tb_nr_t* tb);
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#endif // SRSLTE_RA_NR_H
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#endif // SRSLTE_RA_NR_H
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@ -106,7 +106,7 @@ RA_NR_READ_TABLE(2)
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RA_NR_READ_TABLE(3)
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RA_NR_READ_TABLE(3)
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/**
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/**
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* TS 38.214 V15.10.0 Table 5.1.3.2-1: TBS for N inf o ≤ 3824
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* TS 38.214 V15.10.0 Table 5.1.3.2-1: TBS for N info ≤ 3824
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*/
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*/
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static const uint32_t ra_nr_tbs_table[RA_NR_TBS_SIZE_TABLE] = {
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static const uint32_t ra_nr_tbs_table[RA_NR_TBS_SIZE_TABLE] = {
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24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168,
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24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168,
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@ -222,6 +222,20 @@ static int ra_nr_determine_N_re(const srslte_pdsch_cfg_nr_t* pdsch_cfg, const sr
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// the overhead configured by higher layer parameter xOverhead in PDSCH-ServingCellConfig
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// the overhead configured by higher layer parameter xOverhead in PDSCH-ServingCellConfig
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uint32_t n_prb_oh = 0;
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uint32_t n_prb_oh = 0;
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switch (pdsch_cfg->serving_cell_cfg.xoverhead) {
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case srslte_xoverhead_0:
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n_prb_oh = 0;
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break;
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case srslte_xoverhead_6:
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n_prb_oh = 6;
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break;
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case srslte_xoverhead_12:
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n_prb_oh = 12;
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break;
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case srslte_xoverhead_18:
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n_prb_oh = 18;
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break;
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}
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// Compute total number of n_re used for PDSCH
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// Compute total number of n_re used for PDSCH
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uint32_t n_re_prime = SRSLTE_NRE * n_sh_symb - n_prb_dmrs - n_prb_oh;
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uint32_t n_re_prime = SRSLTE_NRE * n_sh_symb - n_prb_dmrs - n_prb_oh;
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@ -291,7 +305,27 @@ static double ra_nr_get_scaling(uint32_t tb_scaling_field)
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return NAN;
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return NAN;
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}
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}
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int srslte_ra_nr_tbs(const srslte_pdsch_cfg_nr_t* pdsch_cfg, const srslte_pdsch_grant_nr_t* grant, uint32_t mcs_idx)
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uint32_t srslte_ra_nr_tbs(uint32_t N_re, double S, double R, uint32_t Qm, uint32_t nof_layers)
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{
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if (!isnormal(S)) {
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S = 1.0;
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}
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// 2) Intermediate number of information bits (N info ) is obtained by N inf o = N RE · R · Q m · υ .
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uint32_t n_info = (uint32_t)(N_re * S * R * Qm * nof_layers);
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// 3) When n_info ≤ 3824
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if (n_info <= 3824) {
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return ra_nr_tbs_from_n_info3(n_info);
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}
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// 4) When n_info > 3824
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return ra_nr_tbs_from_n_info4(n_info, R);
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}
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int srslte_ra_nr_fill_tb(const srslte_pdsch_cfg_nr_t* pdsch_cfg,
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const srslte_pdsch_grant_nr_t* grant,
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uint32_t mcs_idx,
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srslte_ra_tb_nr_t* tb)
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{
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{
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// Get target Rate
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// Get target Rate
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double R =
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double R =
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@ -330,19 +364,16 @@ int srslte_ra_nr_tbs(const srslte_pdsch_cfg_nr_t* pdsch_cfg, const srslte_pdsch_
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}
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}
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// 1) The UE shall first determine the number of REs (N RE ) within the slot.
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// 1) The UE shall first determine the number of REs (N RE ) within the slot.
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int n_re = ra_nr_determine_N_re(pdsch_cfg, grant);
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int N_re = ra_nr_determine_N_re(pdsch_cfg, grant);
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if (n_re < SRSLTE_SUCCESS) {
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if (N_re < SRSLTE_SUCCESS) {
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return SRSLTE_ERROR;
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return SRSLTE_ERROR;
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}
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}
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// 2) Intermediate number of information bits (N info ) is obtained by N inf o = N RE · R · Q m · υ .
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// Steps 2,3,4
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uint32_t n_info = (uint32_t)(n_re * S * R * Qm * grant->nof_layers);
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tb->tbs = (int)srslte_ra_nr_tbs(N_re, S, R, Qm, grant->nof_layers);
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tb->R = R;
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tb->mod = m;
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tb->nof_bits = N_re * Qm * grant->nof_layers;
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// 3) When n_info ≤ 3824
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return SRSLTE_SUCCESS;
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if (n_info <= 3824) {
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return (int)ra_nr_tbs_from_n_info3(n_info);
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}
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// 4) When n_info > 3824
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return (int)ra_nr_tbs_from_n_info4(n_info, R);
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}
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}
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