mirror of https://github.com/PentHertz/srsLTE.git
added initial_dl_cqi to the enb rr.cfg parser
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bcbb08ebae
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9ad80ee29f
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@ -296,7 +296,7 @@ public:
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* Segmentation happens in this function. RLC PDU is stored in payload. */
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virtual int read_pdu(uint16_t rnti, uint32_t lcid, uint8_t* payload, uint32_t nof_bytes) = 0;
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virtual void read_pdu_pcch(uint8_t* payload, uint32_t buffer_size) = 0;
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virtual void read_pdu_pcch(uint8_t* payload, uint32_t buffer_size) = 0;
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/* MAC calls RLC to push an RLC PDU. This function is called from an independent MAC thread.
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* PDU gets placed into the buffer and higher layer thread gets notified. */
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@ -370,9 +370,9 @@ public:
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class rrc_interface_rlc
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{
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public:
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virtual void read_pdu_pcch(uint8_t* payload, uint32_t payload_size) = 0;
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virtual void max_retx_attempted(uint16_t rnti) = 0;
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virtual void write_pdu(uint16_t rnti, uint32_t lcid, srslte::unique_byte_buffer_t sdu) = 0;
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virtual void read_pdu_pcch(uint8_t* payload, uint32_t payload_size) = 0;
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virtual void max_retx_attempted(uint16_t rnti) = 0;
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virtual void write_pdu(uint16_t rnti, uint32_t lcid, srslte::unique_byte_buffer_t sdu) = 0;
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};
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// RRC interface for MAC
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@ -409,6 +409,7 @@ struct cell_cfg_t {
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float dl_freq_hz;
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uint32_t ul_earfcn;
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float ul_freq_hz;
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uint32_t initial_dl_cqi;
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std::vector<scell_cfg_t> scell_list;
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};
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typedef std::vector<cell_cfg_t> cell_list_t;
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@ -88,6 +88,7 @@ public:
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uint32_t nrb_cqi;
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uint32_t ncs_an;
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uint32_t initial_dl_cqi;
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uint32_t srs_subframe_config;
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uint32_t srs_subframe_offset;
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@ -701,7 +701,7 @@ static int parse_meas_report_desc(rrc_meas_cfg_t* meas_cfg, Setting& root)
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static int parse_cell_list(all_args_t* args, rrc_cfg_t* rrc_cfg, Setting& root)
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{
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auto cell_id_parser = [](uint32_t& cell_id, Setting& root) { return parse_bounded_number(cell_id, root, 0u, 255u); };
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auto cell_id_parser = [](uint32_t& cell_id, Setting& root) { return parse_bounded_number(cell_id, root, 0u, 255u); };
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rrc_cfg->cell_list.resize(root.getLength());
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for (uint32_t n = 0; n < rrc_cfg->cell_list.size(); ++n) {
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@ -717,6 +717,7 @@ static int parse_cell_list(all_args_t* args, rrc_cfg_t* rrc_cfg, Setting& root)
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cell_cfg.ul_earfcn = cellroot["ul_earfcn"]; // will be derived from DL EARFCN If not set
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parse_default_field(
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cell_cfg.root_seq_idx, cellroot, "root_seq_idx", rrc_cfg->sibs[1].sib2().rr_cfg_common.prach_cfg.root_seq_idx);
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parse_default_field(cell_cfg.initial_dl_cqi, cellroot, "initial_dl_cqi", 5u);
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if (cellroot["ho_active"]) {
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HANDLEPARSERCODE(parse_meas_cell_list(&rrc_cfg->meas_cfg, cellroot["meas_cell_list"]));
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@ -770,7 +771,7 @@ int parse_cell_cfg(all_args_t* args_, srslte_cell_t* cell)
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cell->nof_prb = args_->enb.n_prb;
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// PCI not configured yet
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phich_cfg_s phichcfg;
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phich_cfg_s phichcfg;
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parser::section phy_cnfg("phy_cnfg");
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parser::section phich_cnfg("phich_cnfg");
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phy_cnfg.add_subsection(&phich_cnfg);
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@ -44,7 +44,6 @@ namespace srsenb {
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namespace sched_utils {
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const uint32_t initial_dl_cqi = 5;
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const uint32_t conres_ce_size = 6;
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//! Obtains TB size *in bytes* for a given MCS and N_{PRB}
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@ -1193,7 +1192,7 @@ sched_ue_carrier::sched_ue_carrier(const sched_interface::ue_cfg_t& cfg_,
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// only PCell starts active. Remaining ones wait for valid CQI
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active = ue_cc_idx == 0;
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dl_cqi_rx = false;
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dl_cqi = (ue_cc_idx == 0) ? sched_utils::initial_dl_cqi : 0;
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dl_cqi = (ue_cc_idx == 0) ? cell_params->cfg.initial_dl_cqi : 0;
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// set max mcs
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max_mcs_ul = cell_params->sched_cfg->pusch_max_mcs >= 0 ? cell_params->sched_cfg->pusch_max_mcs : 28;
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@ -791,6 +791,7 @@ void rrc::config_mac()
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cfg.sibs[1].sib2().rr_cfg_common.rach_cfg_common.ra_supervision_info.ra_resp_win_size.to_number();
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item.prach_freq_offset = cfg.sibs[1].sib2().rr_cfg_common.prach_cfg.prach_cfg_info.prach_freq_offset;
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item.maxharq_msg3tx = cfg.sibs[1].sib2().rr_cfg_common.rach_cfg_common.max_harq_msg3_tx;
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item.initial_dl_cqi = cfg.cell_list[ccidx].initial_dl_cqi;
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item.nrb_pucch = SRSLTE_MAX(cfg.sr_cfg.nof_prb, cfg.cqi_cfg.nof_prb);
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rrc_log->info("Allocating %d PRBs for PUCCH\n", item.nrb_pucch);
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@ -1296,8 +1297,8 @@ void rrc::ue::handle_rrc_reconf_complete(rrc_conn_recfg_complete_s* msg, srslte:
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// Finally, add SRB2 and DRB1 to the scheduler
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srsenb::sched_interface::ue_bearer_cfg_t bearer_cfg = {};
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bearer_cfg.direction = srsenb::sched_interface::ue_bearer_cfg_t::BOTH;
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bearer_cfg.group = 0;
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bearer_cfg.direction = srsenb::sched_interface::ue_bearer_cfg_t::BOTH;
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bearer_cfg.group = 0;
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parent->mac->bearer_ue_cfg(rnti, 2, &bearer_cfg);
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bearer_cfg.group = last_rrc_conn_recfg.crit_exts.c1()
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.rrc_conn_recfg_r8()
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@ -110,6 +110,7 @@ inline srsenb::sched_interface::cell_cfg_t generate_default_cell_cfg(uint32_t no
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cell_cfg.prach_freq_offset = (cell_cfg_phy.nof_prb == 6) ? 0 : 2;
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cell_cfg.prach_rar_window = 3;
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cell_cfg.maxharq_msg3tx = 3;
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cell_cfg.initial_dl_cqi = 5;
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return cell_cfg;
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}
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