mirror of https://github.com/PentHertz/srsLTE.git
Added NR DCI packing/unpacking format 1_1
This commit is contained in:
Xavier Arteaga
Xavier Arteaga
parent
11b9990224
commit
bccfa8d875
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@ -167,6 +167,24 @@ typedef struct SRSRAN_API {
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// SI-RNTI specific fields
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uint32_t sii; ///< System information indicator
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// Second TB
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uint32_t mcs2; ///< Modulation and coding scheme for the second transport block
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uint32_t ndi2; ///< New data indicator for the second transport block
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uint32_t rv2; ///< Redundancy version for the second transport block
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// Other fields
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uint32_t cc_id; ///< Carrier indicator
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uint32_t bwp_id; ///< BWP indicator
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uint32_t rm_pattern1; ///< Rate matching pattern 1 indicator
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uint32_t rm_pattern2; ///< Rate matching pattern 2 indicator
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uint32_t zp_csi_rs_id; ///< ZP-CSI-RS trigger
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uint32_t ports; ///< Antenna ports
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uint32_t tci; ///< Transmission configuration indication
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uint32_t srs_request; ///< SRS request
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uint32_t cbg_info; ///< CBG transmission information (CBGTI)
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uint32_t cbg_flush; ///< CBG flushing out information (CBGFI)
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uint32_t dmrs_id; ///< DMRS sequence initialization
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} srsran_dci_dl_nr_t;
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/**
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@ -1168,10 +1168,7 @@ static uint32_t dci_nr_format_1_1_sizeof(const srsran_dci_cfg_nr_t* cfg, srsran_
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}
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// SRS request – 2 or 3 bits
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count += 2;
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if (cfg->enable_sul) {
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count++;
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}
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count += cfg->enable_sul ? 2 : 3;
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// CBG transmission information (CBGTI) – 0, 2, 4, 6, or 8 bits
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count += cfg->pdsch_nof_cbg;
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@ -1189,14 +1186,260 @@ static uint32_t dci_nr_format_1_1_sizeof(const srsran_dci_cfg_nr_t* cfg, srsran_
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static int dci_nr_format_1_1_pack(const srsran_dci_nr_t* q, const srsran_dci_dl_nr_t* dci, srsran_dci_msg_nr_t* msg)
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{
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// TODO!
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uint8_t* y = msg->payload;
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srsran_rnti_type_t rnti_type = msg->ctx.rnti_type;
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const srsran_dci_cfg_nr_t* cfg = &q->cfg;
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if (rnti_type != srsran_rnti_type_c && rnti_type != srsran_rnti_type_cs && rnti_type != srsran_rnti_type_mcs_c) {
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ERROR("Invalid RNTI (%s) for format 1_1", srsran_rnti_type_str(rnti_type));
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return SRSRAN_ERROR;
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}
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// Identifier for DCI formats – 1 bits
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*(y++) = 1;
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// Carrier indicator – 0 or 3 bits
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srsran_bit_unpack(dci->cc_id, &y, cfg->carrier_indicator_size);
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// Bandwidth part indicator – 0, 1 or 2 bits
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srsran_bit_unpack(dci->bwp_id, &y, dci_nr_bwp_id_size(cfg->nof_ul_bwp));
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// Frequency domain resource assignment
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srsran_bit_unpack(dci->freq_domain_assigment,
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&y,
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dci_nr_freq_resource_size(cfg->pdsch_alloc_type, cfg->nof_rb_groups, cfg->bwp_dl_active_bw));
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// Time domain resource assignment – 0, 1, 2, 3, or 4 bits
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srsran_bit_unpack(dci->time_domain_assigment, &y, dci_nr_time_res_size(cfg->nof_dl_time_res));
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// VRB-to-PRB mapping – 0 or 1
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if (cfg->pdsch_alloc_type != srsran_resource_alloc_type0 && cfg->pdsch_inter_prb_to_prb) {
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srsran_bit_unpack(dci->vrb_to_prb_mapping, &y, 1);
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}
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// PRB bundling size indicator – 0 or 1 bits
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// ... not implemented
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// Rate matching indicator – 0, 1, or 2 bits
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if (cfg->pdsch_rm_pattern1) {
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srsran_bit_unpack(dci->rm_pattern1, &y, 1);
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}
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if (cfg->pdsch_rm_pattern2) {
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srsran_bit_unpack(dci->rm_pattern2, &y, 1);
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}
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// ZP CSI-RS trigger - 0, 1, or 2 bits
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srsran_bit_unpack(dci->zp_csi_rs_id, &y, CEIL_LOG2(cfg->nof_aperiodic_zp + 1));
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// For transport block 1:
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// Modulation and coding scheme – 5 bits
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srsran_bit_unpack(dci->mcs, &y, 5);
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// New data indicator – 1 bit
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srsran_bit_unpack(dci->ndi, &y, 1);
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// Redundancy version – 2 bits
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srsran_bit_unpack(dci->rv, &y, 2);
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// For transport block 2:
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if (cfg->pdsch_2cw) {
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// Modulation and coding scheme – 5 bits
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srsran_bit_unpack(dci->mcs2, &y, 5);
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// New data indicator – 1 bit
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srsran_bit_unpack(dci->ndi2, &y, 1);
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// Redundancy version – 2 bits
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srsran_bit_unpack(dci->rv2, &y, 2);
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}
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// HARQ process number – 4 bits
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srsran_bit_unpack(dci->pid, &y, 4);
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// Downlink assignment index (dynamic HARQ-ACK codebook only)
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if (cfg->harq_ack_codebok == srsran_pdsch_harq_ack_codebook_dynamic) {
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if (cfg->multiple_scell) {
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srsran_bit_unpack(dci->dai, &y, 4);
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} else {
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srsran_bit_unpack(dci->dai, &y, 2);
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}
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}
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// TPC command for scheduled PUCCH – 2 bits
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srsran_bit_unpack(dci->tpc, &y, 2);
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// PDSCH-to-HARQ_feedback timing indicator – 0, 1, 2, or 3 bits
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srsran_bit_unpack(dci->harq_feedback, &y, cfg->nof_dl_to_ul_ack);
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// Antenna port(s) – 4, 5, or 6 bits
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srsran_bit_unpack(dci->ports, &y, 4);
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if (cfg->pdsch_dmrs_type2) {
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y++;
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}
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if (cfg->pdsch_dmrs_double) {
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y++;
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}
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// Transmission configuration indication – 0 or 3 bits
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if (cfg->pdsch_tci) {
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srsran_bit_unpack(dci->tci, &y, 3);
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}
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// SRS request – 2 or 3 bits
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srsran_bit_unpack(dci->srs_request, &y, cfg->enable_sul ? 2 : 3);
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// CBG transmission information (CBGTI) – 0, 2, 4, 6, or 8 bits
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srsran_bit_unpack(dci->cbg_info, &y, cfg->pdsch_nof_cbg);
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// CBG flushing out information (CBGFI) – 0 or 1 bit
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if (cfg->pdsch_cbg_flush) {
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srsran_bit_unpack(dci->cbg_flush, &y, 1);
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}
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// DMRS sequence initialization – 1 bit
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srsran_bit_unpack(dci->dmrs_id, &y, 1);
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msg->nof_bits = srsran_dci_nr_size(q, msg->ctx.ss_type, srsran_dci_format_nr_1_1);
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uint32_t nof_bits = (uint32_t)(y - msg->payload);
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if (msg->nof_bits != nof_bits) {
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ERROR("Unpacked bits read (%d) do NOT match payload size (%d)", msg->nof_bits, nof_bits);
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return SRSRAN_ERROR;
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}
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return SRSRAN_SUCCESS;
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}
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static int dci_nr_format_1_1_unpack(const srsran_dci_nr_t* q, srsran_dci_msg_nr_t* msg, srsran_dci_dl_nr_t* dci)
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{
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// TODO!
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uint8_t* y = msg->payload;
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srsran_rnti_type_t rnti_type = msg->ctx.rnti_type;
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const srsran_dci_cfg_nr_t* cfg = &q->cfg;
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if (rnti_type != srsran_rnti_type_c && rnti_type != srsran_rnti_type_cs && rnti_type != srsran_rnti_type_mcs_c) {
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ERROR("Invalid RNTI (%s) for format 1_1", srsran_rnti_type_str(rnti_type));
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return SRSRAN_ERROR;
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}
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uint32_t nof_bits = srsran_dci_nr_size(q, msg->ctx.ss_type, srsran_dci_format_nr_1_0);
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if (msg->nof_bits != nof_bits) {
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ERROR("Invalid number of bits %d, expected %d", msg->nof_bits, nof_bits);
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return SRSRAN_ERROR;
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}
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// Identifier for DCI formats – 1 bits
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// The value of this bit field is always set to 1, indicating a DL DCI format
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if (*(y++) != 1) {
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ERROR("Wrond DCI format");
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return SRSRAN_ERROR;
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}
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// Carrier indicator – 0 or 3 bits
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dci->cc_id = srsran_bit_pack(&y, cfg->carrier_indicator_size);
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// Bandwidth part indicator – 0, 1 or 2 bits
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dci->bwp_id = srsran_bit_pack(&y, dci_nr_bwp_id_size(cfg->nof_ul_bwp));
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// Frequency domain resource assignment
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dci->freq_domain_assigment =
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srsran_bit_pack(&y, dci_nr_freq_resource_size(cfg->pdsch_alloc_type, cfg->nof_rb_groups, cfg->bwp_dl_active_bw));
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// Time domain resource assignment – 0, 1, 2, 3, or 4 bits
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dci->time_domain_assigment = srsran_bit_pack(&y, dci_nr_time_res_size(cfg->nof_dl_time_res));
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// VRB-to-PRB mapping – 0 or 1
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if (cfg->pdsch_alloc_type != srsran_resource_alloc_type0 && cfg->pdsch_inter_prb_to_prb) {
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dci->vrb_to_prb_mapping = srsran_bit_pack(&y, 1);
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}
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// PRB bundling size indicator – 0 or 1 bits
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// ... not implemented
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// Rate matching indicator – 0, 1, or 2 bits
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if (cfg->pdsch_rm_pattern1) {
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dci->rm_pattern1 = srsran_bit_pack(&y, 1);
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}
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if (cfg->pdsch_rm_pattern2) {
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dci->rm_pattern2 = srsran_bit_pack(&y, 1);
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}
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// ZP CSI-RS trigger - 0, 1, or 2 bits
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dci->zp_csi_rs_id = srsran_bit_pack(&y, CEIL_LOG2(cfg->nof_aperiodic_zp + 1));
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// For transport block 1:
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// Modulation and coding scheme – 5 bits
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dci->mcs = srsran_bit_pack(&y, 5);
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// New data indicator – 1 bit
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dci->ndi = srsran_bit_pack(&y, 1);
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// Redundancy version – 2 bits
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dci->rv = srsran_bit_pack(&y, 2);
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// For transport block 2:
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if (cfg->pdsch_2cw) {
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// Modulation and coding scheme – 5 bits
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dci->mcs2 = srsran_bit_pack(&y, 5);
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// New data indicator – 1 bit
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dci->ndi2 = srsran_bit_pack(&y, 1);
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// Redundancy version – 2 bits
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dci->rv2 = srsran_bit_pack(&y, 2);
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}
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// HARQ process number – 4 bits
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dci->pid = srsran_bit_pack(&y, 4);
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// Downlink assignment index (dynamic HARQ-ACK codebook only)
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if (cfg->harq_ack_codebok == srsran_pdsch_harq_ack_codebook_dynamic) {
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if (cfg->multiple_scell) {
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dci->dai = srsran_bit_pack(&y, 4);
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} else {
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dci->dai = srsran_bit_pack(&y, 2);
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}
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}
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// TPC command for scheduled PUCCH – 2 bits
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dci->tpc = srsran_bit_pack(&y, 2);
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// PDSCH-to-HARQ_feedback timing indicator – 0, 1, 2, or 3 bits
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dci->harq_feedback = srsran_bit_pack(&y, cfg->nof_dl_to_ul_ack);
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// Antenna port(s) – 4, 5, or 6 bits
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dci->ports = srsran_bit_pack(&y, 4);
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if (cfg->pdsch_dmrs_type2) {
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y++;
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}
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if (cfg->pdsch_dmrs_double) {
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y++;
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}
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// Transmission configuration indication – 0 or 3 bits
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if (cfg->pdsch_tci) {
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dci->tci = srsran_bit_pack(&y, 3);
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}
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// SRS request – 2 or 3 bits
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dci->srs_request = srsran_bit_pack(&y, cfg->enable_sul ? 2 : 3);
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// CBG transmission information (CBGTI) – 0, 2, 4, 6, or 8 bits
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dci->cbg_info = srsran_bit_pack(&y, cfg->pdsch_nof_cbg);
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// CBG flushing out information (CBGFI) – 0 or 1 bit
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if (cfg->pdsch_cbg_flush) {
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dci->cbg_flush = srsran_bit_pack(&y, 1);
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}
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// DMRS sequence initialization – 1 bit
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dci->dmrs_id = srsran_bit_pack(&y, 1);
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uint32_t nof_unpacked_bits = (uint32_t)(y - msg->payload);
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if (nof_unpacked_bits != nof_bits) {
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ERROR("Unpacked bits read (%d) do NOT match payload size (%d)", msg->nof_bits, nof_bits);
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return SRSRAN_ERROR;
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}
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return SRSRAN_SUCCESS;
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}
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