mirror of https://github.com/PentHertz/srsLTE.git
Separate TPC PUSCH and PUCCH target SINR (#2740)
* separate target pusch and pucch sinr configurations in tpc class and rr.conf
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38bf895efa
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d39183419c
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@ -56,7 +56,8 @@ struct cell_cfg_t {
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double dl_freq_hz;
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uint32_t ul_earfcn;
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double ul_freq_hz;
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int target_ul_sinr_db;
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int target_pucch_sinr_db;
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int target_pusch_sinr_db;
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uint32_t initial_dl_cqi;
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bool enable_phr_handling;
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std::vector<scell_cfg_t> scell_list;
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@ -65,9 +65,12 @@ public:
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cell_cfg_sib_t sibs[MAX_SIBS];
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uint32_t si_window_ms;
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/* pucch configuration */
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float target_pucch_ul_sinr;
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/* pusch configuration */
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srsran_pusch_hopping_cfg_t pusch_hopping_cfg;
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float target_ul_sinr;
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float target_pusch_ul_sinr;
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bool enable_phr_handling;
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bool enable_64qam;
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@ -35,15 +35,23 @@ public:
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static constexpr uint32_t PUSCH_CODE = 0, PUCCH_CODE = 1;
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static constexpr int PHR_NEG_NOF_PRB = 1;
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explicit tpc(uint32_t cell_nof_prb, float target_snr_dB_ = -1.0, bool phr_handling_flag_ = false) :
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explicit tpc(uint32_t cell_nof_prb,
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float target_pucch_snr_dB_ = -1.0,
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float target_pusch_sn_dB_ = -1.0,
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bool phr_handling_flag_ = false) :
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nof_prb(cell_nof_prb),
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target_snr_dB(target_snr_dB_),
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snr_estim_list({ul_ch_snr_estim{target_snr_dB_}, ul_ch_snr_estim{target_snr_dB_}}),
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target_pucch_snr_dB(target_pucch_snr_dB_),
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target_pusch_snr_dB(target_pusch_sn_dB_),
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snr_estim_list({ul_ch_snr_estim{target_pusch_snr_dB}, ul_ch_snr_estim{target_pucch_snr_dB}}),
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phr_handling_flag(phr_handling_flag_)
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{
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max_prbs_cached = nof_prb;
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}
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void set_cfg(float target_snr_dB_) { target_snr_dB = target_snr_dB_; }
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void set_cfg(float target_pusch_snr_dB_, float target_pucch_snr_dB_)
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{
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target_pucch_snr_dB = target_pucch_snr_dB_;
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target_pusch_snr_dB = target_pusch_snr_dB_;
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}
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void set_snr(float snr, uint32_t ul_ch_code)
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{
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@ -72,7 +80,9 @@ public:
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void new_tti()
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{
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for (auto& ch_snr : snr_estim_list) {
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for (size_t chidx = 0; chidx < 2; ++chidx) {
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float target_snr_dB = chidx == PUSCH_CODE ? target_pusch_snr_dB : target_pucch_snr_dB;
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auto& ch_snr = snr_estim_list[chidx];
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if (target_snr_dB < 0) {
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ch_snr.pending_delta = 0;
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continue;
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@ -130,7 +140,8 @@ private:
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}
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uint8_t enconde_tpc(uint32_t cc)
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{
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auto& ch_snr = snr_estim_list[cc];
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float target_snr_dB = cc == PUSCH_CODE ? target_pusch_snr_dB : target_pucch_snr_dB;
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auto& ch_snr = snr_estim_list[cc];
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assert(ch_snr.pending_delta == 0); // ensure called once per {cc,tti}
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if (target_snr_dB < 0) {
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// undefined target SINR case. Increase Tx power once per PHR, considering the number of allocable PRBs remains
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@ -158,7 +169,7 @@ private:
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}
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uint32_t nof_prb;
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float target_snr_dB;
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float target_pucch_snr_dB, target_pusch_snr_dB;
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bool phr_handling_flag;
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// PHR-related variables
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@ -62,7 +62,9 @@ cell_list =
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//ul_earfcn = 21400;
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ho_active = false;
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//meas_gap_period = 0; // 0 (inactive), 40 or 80
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//allowed_meas_bw = 6;
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// target_pusch_sinr = -1;
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// target_pucch_sinr = -1;
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// allowed_meas_bw = 6;
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// CA cells
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scell_list = (
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@ -749,7 +749,8 @@ static int parse_cell_list(all_args_t* args, rrc_cfg_t* rrc_cfg, Setting& root)
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cell_cfg.root_seq_idx, cellroot, "root_seq_idx", rrc_cfg->sibs[1].sib2().rr_cfg_common.prach_cfg.root_seq_idx);
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parse_default_field(cell_cfg.initial_dl_cqi, cellroot, "initial_dl_cqi", 5u);
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parse_default_field(cell_cfg.meas_cfg.meas_gap_period, cellroot, "meas_gap_period", 0u);
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HANDLEPARSERCODE(parse_default_field(cell_cfg.target_ul_sinr_db, cellroot, "target_ul_sinr", -1));
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HANDLEPARSERCODE(parse_default_field(cell_cfg.target_pusch_sinr_db, cellroot, "target_pusch_sinr", -1));
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HANDLEPARSERCODE(parse_default_field(cell_cfg.target_pucch_sinr_db, cellroot, "target_pucch_sinr", -1));
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HANDLEPARSERCODE(parse_default_field(cell_cfg.enable_phr_handling, cellroot, "enable_phr_handling", false));
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parse_default_field(cell_cfg.meas_cfg.allowed_meas_bw, cellroot, "allowed_meas_bw", 6u);
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srsran_assert(srsran::is_lte_cell_nof_prb(cell_cfg.meas_cfg.allowed_meas_bw), "Invalid measurement Bandwidth");
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@ -27,7 +27,10 @@ sched_ue_cell::sched_ue_cell(uint16_t rnti_, const sched_cell_params_t& cell_cfg
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cell_cfg(&cell_cfg_),
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dci_locations(generate_cce_location_table(rnti_, cell_cfg_)),
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harq_ent(SCHED_MAX_HARQ_PROC, SCHED_MAX_HARQ_PROC),
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tpc_fsm(cell_cfg->nof_prb(), cell_cfg->cfg.target_ul_sinr, cell_cfg->cfg.enable_phr_handling),
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tpc_fsm(cell_cfg->nof_prb(),
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cell_cfg->cfg.target_pucch_ul_sinr,
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cell_cfg->cfg.target_pusch_ul_sinr,
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cell_cfg->cfg.enable_phr_handling),
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fixed_mcs_dl(cell_cfg_.sched_cfg->pdsch_mcs),
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fixed_mcs_ul(cell_cfg_.sched_cfg->pusch_mcs),
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current_tti(current_tti_),
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@ -724,16 +724,17 @@ void rrc::config_mac()
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item.si_window_ms = cfg.sib1.si_win_len.to_number();
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item.prach_rar_window =
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cfg.sibs[1].sib2().rr_cfg_common.rach_cfg_common.ra_supervision_info.ra_resp_win_size.to_number();
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item.prach_freq_offset = cfg.sibs[1].sib2().rr_cfg_common.prach_cfg.prach_cfg_info.prach_freq_offset;
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item.maxharq_msg3tx = cfg.sibs[1].sib2().rr_cfg_common.rach_cfg_common.max_harq_msg3_tx;
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item.enable_64qam = cfg.sibs[1].sib2().rr_cfg_common.pusch_cfg_common.pusch_cfg_basic.enable64_qam;
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item.initial_dl_cqi = cfg.cell_list[ccidx].initial_dl_cqi;
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item.target_ul_sinr = cfg.cell_list[ccidx].target_ul_sinr_db;
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item.enable_phr_handling = cfg.cell_list[ccidx].enable_phr_handling;
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item.delta_pucch_shift = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.delta_pucch_shift.to_number();
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item.ncs_an = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.ncs_an;
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item.n1pucch_an = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.n1_pucch_an;
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item.nrb_cqi = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.nrb_cqi;
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item.prach_freq_offset = cfg.sibs[1].sib2().rr_cfg_common.prach_cfg.prach_cfg_info.prach_freq_offset;
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item.maxharq_msg3tx = cfg.sibs[1].sib2().rr_cfg_common.rach_cfg_common.max_harq_msg3_tx;
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item.enable_64qam = cfg.sibs[1].sib2().rr_cfg_common.pusch_cfg_common.pusch_cfg_basic.enable64_qam;
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item.initial_dl_cqi = cfg.cell_list[ccidx].initial_dl_cqi;
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item.target_pucch_ul_sinr = cfg.cell_list[ccidx].target_pucch_sinr_db;
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item.target_pusch_ul_sinr = cfg.cell_list[ccidx].target_pusch_sinr_db;
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item.enable_phr_handling = cfg.cell_list[ccidx].enable_phr_handling;
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item.delta_pucch_shift = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.delta_pucch_shift.to_number();
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item.ncs_an = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.ncs_an;
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item.n1pucch_an = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.n1_pucch_an;
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item.nrb_cqi = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.nrb_cqi;
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item.nrb_pucch = SRSRAN_MAX(cfg.sr_cfg.nof_prb, cfg.cqi_cfg.nof_prb);
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logger.info("Allocating %d PRBs for PUCCH", item.nrb_pucch);
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@ -271,7 +271,8 @@ sched_sim_events rand_sim_params(uint32_t nof_ttis)
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sched_sim_event_generator generator;
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sim_gen.sim_args.cell_cfg = {generate_default_cell_cfg(nof_prb)};
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sim_gen.sim_args.cell_cfg[0].target_ul_sinr = pick_random_uniform({10, 15, 20, -1});
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sim_gen.sim_args.cell_cfg[0].target_pucch_ul_sinr = pick_random_uniform({10, 15, 20, -1});
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sim_gen.sim_args.cell_cfg[0].target_pusch_ul_sinr = pick_random_uniform({10, 15, 20, -1});
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sim_gen.sim_args.cell_cfg[0].enable_phr_handling = false;
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sim_gen.sim_args.default_ue_sim_cfg.ue_cfg = generate_default_ue_cfg();
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sim_gen.sim_args.default_ue_sim_cfg.periodic_cqi = true;
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@ -40,21 +40,22 @@ inline srsenb::sched_interface::cell_cfg_t generate_default_cell_cfg(uint32_t no
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cell_cfg_phy.phich_length = SRSRAN_PHICH_NORM;
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cell_cfg_phy.phich_resources = SRSRAN_PHICH_R_1;
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cell_cfg.sibs[0].len = 18;
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cell_cfg.sibs[0].period_rf = 8;
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cell_cfg.sibs[1].len = 41;
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cell_cfg.sibs[1].period_rf = 16;
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cell_cfg.si_window_ms = 40;
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cell_cfg.nrb_pucch = (cell_cfg_phy.nof_prb == 6) ? 1 : 2;
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cell_cfg.prach_freq_offset = (cell_cfg_phy.nof_prb == 6) ? 0 : 4;
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cell_cfg.prach_rar_window = 3;
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cell_cfg.maxharq_msg3tx = 3;
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cell_cfg.initial_dl_cqi = 6;
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cell_cfg.target_ul_sinr = -1;
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cell_cfg.nrb_cqi = 1;
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cell_cfg.n1pucch_an = 12;
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cell_cfg.delta_pucch_shift = 1;
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cell_cfg.ncs_an = 0;
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cell_cfg.sibs[0].len = 18;
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cell_cfg.sibs[0].period_rf = 8;
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cell_cfg.sibs[1].len = 41;
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cell_cfg.sibs[1].period_rf = 16;
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cell_cfg.si_window_ms = 40;
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cell_cfg.nrb_pucch = (cell_cfg_phy.nof_prb == 6) ? 1 : 2;
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cell_cfg.prach_freq_offset = (cell_cfg_phy.nof_prb == 6) ? 0 : 4;
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cell_cfg.prach_rar_window = 3;
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cell_cfg.maxharq_msg3tx = 3;
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cell_cfg.initial_dl_cqi = 6;
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cell_cfg.target_pusch_ul_sinr = -1;
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cell_cfg.target_pucch_ul_sinr = -1;
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cell_cfg.nrb_cqi = 1;
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cell_cfg.n1pucch_an = 12;
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cell_cfg.delta_pucch_shift = 1;
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cell_cfg.ncs_an = 0;
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return cell_cfg;
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}
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@ -26,7 +26,7 @@ int test_finite_target_snr()
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const uint32_t nof_prbs = 50;
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const int target_snr = 15;
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tpc tpcfsm(nof_prbs, 15, true);
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tpc tpcfsm(nof_prbs, 15, 15, true);
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// TEST: While no SNR info is provided, no TPC commands are sent
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for (uint32_t i = 0; i < 100; ++i) {
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@ -73,7 +73,7 @@ int test_undefined_target_snr()
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{
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const uint32_t nof_prbs = 50;
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tpc tpcfsm(nof_prbs, -1, true);
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tpc tpcfsm(nof_prbs, -1, -1, true);
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TESTASSERT(tpcfsm.max_ul_prbs() == 50);
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// TEST: While the PHR is not updated, a limited number of TPC commands should be sent
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