mirror of https://github.com/PentHertz/srsLTE.git
nr,gnb,phy: ensure coreset0_bw of the DCI is set when CORESET#0 and format1_0 are used
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@ -58,6 +58,7 @@ bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params_t& bwp
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{
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uint32_t cs_id = bwp_cfg.cfg.pdcch.ra_search_space.coreset_id;
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// Fill DCI context
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dci.ctx.format = srsran_dci_format_nr_1_0;
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dci.ctx.ss_type = srsran_search_space_type_common_1;
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dci.ctx.rnti_type = srsran_rnti_type_ra;
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@ -66,7 +67,7 @@ bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params_t& bwp
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dci.ctx.coreset_start_rb = srsran_coreset_start_rb(&bwp_cfg.cfg.pdcch.coreset[cs_id]);
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dci.mcs = 5;
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if (bwp_cfg.cfg.pdcch.coreset_present[0] and cs_id == 0) {
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if (cs_id == 0) {
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dci.coreset0_bw = srsran_coreset_get_bw(&bwp_cfg.cfg.pdcch.coreset[cs_id]);
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}
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dci.freq_domain_assigment = srsran_ra_nr_type1_riv(bwp_cfg.cfg.rb_width, interv.start(), interv.length());
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@ -81,6 +82,7 @@ bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params_t& bwp
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bool fill_dci_msg3(const slot_ue& ue, const bwp_params_t& bwp_cfg, srsran_dci_ul_nr_t& msg3_dci)
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{
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// Fill DCI context
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msg3_dci.ctx.coreset_id = ue->phy().pdcch.ra_search_space.coreset_id;
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msg3_dci.ctx.rnti_type = srsran_rnti_type_tc;
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msg3_dci.ctx.rnti = ue->rnti;
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@ -90,6 +92,8 @@ bool fill_dci_msg3(const slot_ue& ue, const bwp_params_t& bwp_cfg, srsran_dci_ul
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} else {
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msg3_dci.ctx.format = srsran_dci_format_nr_0_0;
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}
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// Fill DCI content
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fill_dci_common(ue, bwp_cfg, msg3_dci.ctx, msg3_dci);
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return true;
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@ -112,6 +116,9 @@ void fill_dl_dci_ue_fields(const slot_ue& ue,
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} else {
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dci.harq_feedback = ue.pdsch_slot.slot_idx();
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}
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if (dci.ctx.coreset_id == 0 and dci.ctx.format == srsran_dci_format_nr_1_0) {
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dci.coreset0_bw = srsran_coreset_get_bw(&bwp_cfg.cfg.pdcch.coreset[0]);
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}
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}
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void fill_ul_dci_ue_fields(const slot_ue& ue,
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