Commit Graph

1051 Commits

Author SHA1 Message Date
faluco 1860006203 - Fixed leaks in prach module spotted by asan. 2020-09-08 17:26:50 +02:00
yagoda 24574caf44 cleaning up the PRACH time offset calculation 2020-09-07 14:56:12 +01:00
yagoda b5a8d82058 -adding more prach tests to make test, removing some variables from stack
-PRACH time offset to TA unit conversion
2020-09-07 14:56:12 +01:00
yagoda 59082770d3 moving some arrays to the heap, fixing formatting, setting dft norm 2020-09-07 14:56:12 +01:00
yagoda f6ea431555 -adopting new PRACH equalization approach for successive cancellation
-adding frequency domain time offset detection
-adding to testing of PRACH
2020-09-07 14:56:12 +01:00
yagoda ec7873e7cc refactoring PRACH, adding phase correction to successive cancellation 2020-09-07 14:56:12 +01:00
yagoda 4d8888aae6 - adding simple successive cancellation to PRACH detection
- adding testing for same and for offset detection
2020-09-07 14:56:12 +01:00
Ismael Gomez c4080e35cc Set different timestamp behaviour for X300 and B200 2020-09-07 15:10:22 +02:00
Ismael Gomez 54eed11e1d Refactor decision for extended CSI/SRS 2020-09-03 10:45:06 +02:00
Ismael Gomez c9daf1f61a Make const args 2020-09-03 10:45:06 +02:00
Ismael Gomez e2154d2213 Renamed constants to SRSLTE and use SRSLTE_CFI macros 2020-09-03 10:45:06 +02:00
Ismael Gomez 38e2ffe414 Use Format1A when using CA and 15 PRB due to DCI size ambiguity 2020-09-03 10:45:06 +02:00
Ismael Gomez 51521ad8e4 Improved PDCCH blind search and fixed a few issues with ambiguous DCI size with Release 10 2020-09-03 10:45:06 +02:00
faluco db03275337 - Fix compiler errors when trying to build the project without SIMD support. 2020-09-02 12:35:18 +02:00
Xavier Arteaga 1f18e8a054 SIMD: frequency estimate optimization 2020-08-31 16:44:19 +02:00
Xavier Arteaga bf1b7b8527 SIMD: fix NEON compilation 2020-08-31 16:44:19 +02:00
Ismael Gomez 0afcea9d61
Do not allow empty TBS PUSCH. Account for CQI from inactive cells before activated. (#1667) 2020-08-31 12:53:18 +02:00
Xavier Arteaga 080543815f Solved compilation warnings and enb_phy_test stop 2020-08-28 11:36:44 +02:00
Xavier Arteaga b8f4d03979 Fix in SIMD frequency estimation 2020-08-28 11:36:44 +02:00
Xavier Arteaga 611dd67364 SRSENB: PUCCH TA measurement only available with detected PUCCH 2020-08-28 11:36:44 +02:00
Xavier Arteaga 87edafeddb Reduced SRS test cases to SF index 0 2020-08-28 11:36:44 +02:00
Xavier Arteaga ee6f24befe Optimize vector frequency estimation 2020-08-28 11:36:44 +02:00
Xavier Arteaga bc0aba0d8a SRSENB: calculate TA from PUCCH messages 2020-08-28 11:36:44 +02:00
Xavier Arteaga 1843c9efbc SRSENB: PUCCH TA measurement only available with detected PUCCH 2020-08-27 09:31:05 +02:00
Xavier Arteaga 3aec23f7d8 SRSENB: calculate TA from PUCCH messages 2020-08-27 09:31:05 +02:00
Xavier Arteaga 04d7267734 UHD: Force LO frequency option 2020-08-27 09:31:05 +02:00
Andre Puschmann 3f02e56a1e uhd: do not stop rx_stream when setting rx_rate for the B210
with the B210 and 2 RF ports, i.e. MIMO mode, we have stopped the
Rx stream after changing the rx_samp_rate but didn't start it again.

Either the issue doesn't exist in SISO mode or we never saw it but for MIMO
it can be reproduced easily with rate changes during streaming, i.e.:

$ ./lib/src/radio/test/benchmark_radio -p 2 -t 10 -x -y -s 23.04e6
Instantiating objects and allocating memory...
Initialising instances...
Opening 2 channels in RF device= with args=default
[INFO] [UHD] linux; GNU C++ version 9.2.1 20200304; Boost_107100; UHD_3.15.0.0-2build5
[INFO] [LOGGING] Fastpath logging disabled at runtime.
Opening USRP channels=2, args: type=b200,master_clock_rate=23.04e6
[INFO] [B200] Detected Device: B210
[INFO] [B200] Operating over USB 3.
[INFO] [B200] Initialize CODEC control...
[INFO] [B200] Initialize Radio control...
[INFO] [B200] Performing register loopback test...
[INFO] [B200] Register loopback test passed
[INFO] [B200] Performing register loopback test...
[INFO] [B200] Register loopback test passed
[INFO] [B200] Asking for clock rate 23.040000 MHz...
[INFO] [B200] Actually got clock rate 23.040000 MHz.
[INFO] [MULTI_USRP]     1) catch time transition at pps edge
[INFO] [MULTI_USRP]     2) set times next pps (synchronously)

Warning: TX gain was not set. Using open-loop power control (not working properly)

Setting manual TX/RX offset to 0 samples
Start capturing 10000 frames of 23040 samples...
Changing sampling rate to 23.04 Msamps/s
Setting manual TX/RX offset to 0 samples
Changing sampling rate to 1.92 Msamps/s
Setting manual TX/RX offset to 0 samples
/home/anpu/src/srsLTE/lib/src/phy/rf/rf_uhd_imp.cc.1211: Error timed out while receiving samples from UHD.

/home/anpu/src/srsLTE/lib/src/phy/rf/rf_uhd_imp.cc.1211: Error timed out while receiving samples from UHD.

/home/anpu/src/srsLTE/lib/src/phy/rf/rf_uhd_imp.cc.1211: Error timed out while receiving samples from UHD.

/home/anpu/src/srsLTE/lib/src/phy/rf/rf_uhd_imp.cc.1211: Error timed out while receiving samples from UHD.

/home/anpu/src/srsLTE/lib/src/phy/rf/rf_uhd_imp.cc.1211: Error timed out while receiving samples from UHD.
2020-08-26 17:22:35 +02:00
Andre Puschmann 7253efe17e rf_blade: fix memleak when device wasn't found 2020-08-26 17:22:35 +02:00
Andre Puschmann 9684b2a63a uhd: fix memleak when USRP wasn't found 2020-08-26 17:22:35 +02:00
Ismael Gomez 59b9125d4e
Do not send time_spec in between the burst. X300 does not like it (#1583) 2020-08-26 11:21:29 +02:00
Ismael Gomez a4835dd2c8
More accurate MCS reduction when PUSCH carries UCI (#1630) 2020-08-25 22:30:35 +02:00
Xavier Arteaga bd46c40650 srsLTE: fix minor aesthetics 2020-08-25 16:19:52 +02:00
Xavier Arteaga 029f36b449 srsLTE: added efficient integer resampler and srsue/srsenb integration 2020-08-25 16:19:52 +02:00
Xavier Arteaga 0e96ef3df0 Channel emulator takes SNR as input parameter 2020-08-24 10:46:11 +02:00
Andre Puschmann 9149cf852d rf_uhd: fix rx timeout error after late with B210
it fixes #1623.

this happens more often with MIMO since lates are more likely here.

after a late, the Rx stream must not be stopped on the B2xx either.

<log>
RF status: O=3, U=0, L=1
/home/anpu/src/srsLTE/lib/src/phy/rf/rf_uhd_imp.cc.1209: Error timed out while receiving samples from UHD.

stop rx stream
./home/anpu/src/srsLTE/lib/src/phy/rf/rf_uhd_imp.cc.1209: Error timed out while receiving samples from UHD.

stop rx stream
/home/anpu/src/srsLTE/lib/src/phy/ue/ue_sync.c.775: Error receiving samples

/home/anpu/src/srsLTE/lib/src/phy/ue/ue_cell_search.c.312: Error calling srslte_ue_sync_work()

/home/anpu/src/srsLTE/lib/src/phy/ue/ue_cell_search.c.272: Error searching cell
</log>
2020-08-21 15:28:08 +02:00
Xavier Arteaga 710700d0eb SRSUE: Fix synch error correction for multiple channels 2020-08-19 15:39:13 +02:00
Andre Puschmann cb2d7f4c16 rf_uhd_generic: add explicit ctor and dtor
clang 6 complained about a missing virtual dtor and thus
failed compilation. this patch adds both, an explicit ctor and dtor.
2020-08-10 10:42:54 +02:00
Andre Puschmann 498af989bf rf_uhd: add missing endl to UHD log macros 2020-08-06 22:42:48 +02:00
Xavier Arteaga 46ab07123d UHD: fix compatibility with 3.9.7 LTS 2020-08-06 22:42:48 +02:00
Andre Puschmann 5867668c0c rf_uhd_rfnoc: fix compilation for UHD before 3.15
the enable_rx_timestamps() for the radio_ctrl object has only been
introduced in Nov 2019 for UHD 3.15 and therefore needs
to be excluded when compiling for 3.14 and below.

Note: According to the original UHD commit in
67dbaa41f2 (diff-60a9387c0fc8406fd5b39fa995dd8c14)
it looks like the Rx timestamps are disabled by default
for UHD versions before 3.15

This commit fixes #1602
2020-08-05 13:05:29 +02:00
Xavier Arteaga 0cd61145ca RFNOC: added optional FPGA FIFO 2020-07-31 13:11:10 +02:00
Xavier Arteaga 237de07ab3 UHD: disable AD936x based device reset 2020-07-31 13:11:10 +02:00
Xavier Arteaga ff8925b6ec UHD: use same timeout policy than previous release 2020-07-31 13:11:10 +02:00
Xavier Arteaga ac76a398fe UHD: Minor stability improvement 2020-07-31 13:11:10 +02:00
Xavier Arteaga d2abaaf719 UHD: add initial test for AD936x based devices during initialization 2020-07-31 13:11:10 +02:00
Xavier Arteaga f80c779d88 RFNOC: added DUC/DDC internal loopback option and test 2020-07-31 13:11:10 +02:00
Xavier Arteaga dcf05f7a53 UHD: Improved RFNOC 2020-07-31 13:11:10 +02:00
Xavier Arteaga 38d9545e99 UHD: API improvement 2020-07-31 13:11:10 +02:00
Xavier Arteaga 405e0c8195 UHD: Check if tree exist before requesting access 2020-07-31 13:11:10 +02:00
Xavier Arteaga 5d43fc903e UHD: fix SPP equal 0 2020-07-31 13:11:10 +02:00