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471 Commits

Author SHA1 Message Date
Xavier Arteaga 8de2870788 Added NR ue_dl, enb_dl and test 2020-12-12 15:58:34 +01:00
Xavier Arteaga c6a2e4578e Refactored PHY object arguments 2020-12-12 15:58:34 +01:00
Xavier Arteaga e621a1cde3 EVM buffer takes number of bits 2020-12-12 15:58:34 +01:00
Xavier Arteaga a278a49e42 Limit PDSCH-NR unit test 2020-12-12 15:58:34 +01:00
Xavier Arteaga bff71761a9 PDSCH-NR: Added single layer channel equalization 2020-12-12 15:58:34 +01:00
Xavier Arteaga 0138c3b856 PDSCH-NR fixed with unit test 2020-12-12 15:58:34 +01:00
Xavier Arteaga fb64c2a460 Initial NR PDSCH encode/decode 2020-12-12 15:58:34 +01:00
Xavier Arteaga 644758416e DL-SCH-NR adjust unit test 2020-12-12 15:58:33 +01:00
Xavier Arteaga d27f0819a8 Fix DL-SCH for NR 2020-12-12 15:58:33 +01:00
Xavier Arteaga 53282bdfbf Dl-SCH-NR: updated unit test 2020-12-12 15:58:33 +01:00
Xavier Arteaga 4e5edb5168 DL-SCH NR added traces and fixes 2020-12-12 15:58:33 +01:00
Xavier Arteaga 2aa7e43771 Implemented NR DL SCH decoder and unit test 2020-12-12 15:58:33 +01:00
Xavier Arteaga 27a3e87fb7 Initial DL-SCH encoding 2020-12-12 15:58:33 +01:00
Xavier Arteaga 9a320baf37 extended resource allocation for NR 2020-12-12 15:58:33 +01:00
Xavier Arteaga a6ac80cfbf Initial NR DL DCI Packing/Unpacking 2020-12-12 15:58:33 +01:00
Xavier Arteaga cf55eb4c4f Improved comments 2020-12-12 15:58:33 +01:00
Xavier Arteaga e8f94c40b8 Added LDPC codeblock segmentation 2020-12-12 15:58:33 +01:00
Xavier Arteaga 736e6db616 Initial resource allocation for NR 2020-12-12 15:58:33 +01:00
Xavier Arteaga f21590735d refactored FEC directories 2020-11-02 16:32:26 +01:00
Xavier Arteaga 9487d27ef9 Renamed NR constants and comments 2020-10-29 09:23:09 +01:00
Xavier Arteaga e8f168b20c PDSCH NR: Added files 2020-10-29 09:23:09 +01:00
Xavier Arteaga c8477483d9 PDSCH NR: Added files 2020-10-29 09:23:09 +01:00
Xavier Arteaga 775692f461 Rearanged PDCCH NR functions structures 2020-10-29 09:23:09 +01:00
Xavier Arteaga be400503b9 Add pass criteria to PRACH USRP test 2020-10-27 21:12:21 +01:00
Xavier Arteaga 28bb4709ff Solved possible high impact PHY out-of-bounds issues 2020-10-27 20:33:48 +01:00
Andre Puschmann 723ca2dd48 ra_dl: fix TDD reference symbol extraction 
reported/provided by user softdev86 in https://github.com/srsLTE/srsLTE/issues/566

author tested with local 4 port cell. I am not able to verify locally but
it looks ok, we'll revise later if needed.
 2020-10-25 14:42:30 +01:00
Francisco Paisana 4cb6ed27eb updated scheduler ue mcs computation to account for new 256QAM tables 2020-10-22 19:55:46 +02:00
Xavier Arteaga fac6d40a45 SRSENB: fix PUSCH max number of iterations 2020-10-22 09:24:40 +02:00
Xavier Arteaga caf37b8e62 Added serving cell index in UCI/CSI report trace 2020-10-20 11:53:28 +02:00
Xavier Arteaga ca6566ad46 Fix PUCCH format1b false detection 2020-10-14 16:42:33 +02:00
yagoda 615af5cc4d setting seed to constant in prach test 2020-10-05 22:04:07 +01:00
Ismael Gomez 4e88daae21
Set DCI unpacking errors to info (#1781) 2020-09-30 10:04:08 +02:00
Xavier Arteaga 8566cbb079 Added device name to prach_test_usrp 2020-09-23 09:06:03 +02:00
faluco b892da0294 - Calculate the FFT of the PRACH on demand. 
- Fixed a PRACH test that was failing with ASAN.
 2020-09-21 09:50:20 +02:00
Xavier Arteaga 8cb3945886 SRSUE: fix RV assertion for PUSCH 2020-09-17 22:39:56 +02:00
Xavier Arteaga 44c2412be2 SRSUE: silent PUSCH encoding error by dropping invalid grant 2020-09-17 22:39:56 +02:00
Xavier Arteaga 1d71cf8557 Avoid zero division 2020-09-10 11:11:46 +02:00
faluco 1860006203 - Fixed leaks in prach module spotted by asan. 2020-09-08 17:26:50 +02:00
yagoda 24574caf44 cleaning up the PRACH time offset calculation 2020-09-07 14:56:12 +01:00
yagoda b5a8d82058 -adding more prach tests to make test, removing some variables from stack 
-PRACH time offset to TA unit conversion
 2020-09-07 14:56:12 +01:00
yagoda 59082770d3 moving some arrays to the heap, fixing formatting, setting dft norm 2020-09-07 14:56:12 +01:00
yagoda f6ea431555 -adopting new PRACH equalization approach for successive cancellation 
-adding frequency domain time offset detection
-adding to testing of PRACH
 2020-09-07 14:56:12 +01:00
yagoda ec7873e7cc refactoring PRACH, adding phase correction to successive cancellation 2020-09-07 14:56:12 +01:00
yagoda 4d8888aae6 - adding simple successive cancellation to PRACH detection 
- adding testing for same and for offset detection
 2020-09-07 14:56:12 +01:00
Ismael Gomez 54eed11e1d Refactor decision for extended CSI/SRS 2020-09-03 10:45:06 +02:00
Ismael Gomez c9daf1f61a Make const args 2020-09-03 10:45:06 +02:00
Ismael Gomez e2154d2213 Renamed constants to SRSLTE and use SRSLTE_CFI macros 2020-09-03 10:45:06 +02:00
Ismael Gomez 51521ad8e4 Improved PDCCH blind search and fixed a few issues with ambiguous DCI size with Release 10 2020-09-03 10:45:06 +02:00
Xavier Arteaga 3aec23f7d8 SRSENB: calculate TA from PUCCH messages 2020-08-27 09:31:05 +02:00
Ismael Gomez a4835dd2c8
More accurate MCS reduction when PUSCH carries UCI (#1630) 2020-08-25 22:30:35 +02:00
Xavier Arteaga 5258f27490 Fix start-of_burst for PRACH Test USRP 2020-07-28 09:31:34 +02:00
Xavier Arteaga fda1d040e7 SRSENB: implement PUSCH threshold for UCI bits 2020-07-27 16:44:15 +02:00
Ismael Gomez 1eaf7efab0 Fix UL adaptive retx rv index 2020-07-15 18:24:23 +02:00
Xavier Arteaga 729986f259 srsLTE: Added PUCCH format 3 valid correlation 2020-07-15 07:34:14 +02:00
Andre Puschmann 9f98bb3f54 disable prach_test_usrp compilation if no RF is selected 2020-06-11 11:07:06 +02:00
Xavier Arteaga 258f7a180c Improved PRACH test USRP 2020-06-10 11:44:44 +02:00
Xavier Arteaga 9d5c2d70df SRSENB: Fix PHY reconfiguration for HO 
Minimal aesthetic change
 2020-05-19 16:38:55 +02:00
faluco 340ec61e8e Code review. 2020-05-07 18:53:40 +02:00
faluco e28d9bb473 Fix for 1492950. 2020-05-07 18:53:40 +02:00
Andre Puschmann a0665b721e prach: fix illegal mem access when wrong configs are passed 
this fixes Coverity issue 1480095
 2020-05-07 13:25:02 +02:00
faluco d9529a3a8f Fix for 1480071. 2020-05-07 10:12:29 +02:00
faluco 7ff251f112 - Fixed warnings caught by Clang 9.0.0 2020-05-07 10:10:24 +02:00
Andre Puschmann f5d55847c2 nbiot: add r14 parameter to NPDSCH eNB and file test and make it the default 
also add skip SIB2 option to UE example
 2020-05-04 17:52:21 +02:00
Andre Puschmann 92fb6a94f4 npdsch: use r14 bcch sequence when encoding SIB 2020-05-04 17:52:21 +02:00
Xavier Arteaga d94078d543 Minor changes 
Fix UE sequence generation

minor change
 2020-05-01 21:07:33 +02:00
Xavier Arteaga 2d39c7261c renamed vector copy prefix from to 2020-04-30 13:43:17 +02:00
Andre Puschmann 6a764ae87c psbch: change memcpy() to srs_vec alternative 2020-04-29 15:31:29 +02:00
Xavier Arteaga 9d0a3268e8 Added DL channel estimator algorithm options 2020-04-28 17:26:01 +02:00
yagoda 1f6d5fd23a small fixed to limiting prach search 2020-04-28 14:40:20 +02:00
yagoda faf1cf6975 limiting prach search space to number of prachs set in sib2 2020-04-28 14:40:20 +02:00
Xavier Arteaga b9583d4182 Fix Extended CSI request bits in DCI 2020-04-27 21:03:44 +02:00
Andre Puschmann 8d52343c72 pssch: address review comments 2020-04-27 21:01:46 +02:00
Andre Puschmann d6e0153b40 sci: add SCI format 1 transmission format flag 2020-04-27 21:01:46 +02:00
Andre Puschmann 7109379d83 pssch_test: fix memleak 2020-04-27 21:01:46 +02:00
Andre Puschmann edcf6d1e51 pssch_test: zero sample vectors after alloc 2020-04-27 21:01:46 +02:00
Andre Puschmann 723503fded pssch_test: disable PSSCH tests that currently fail decoding TB 2020-04-27 21:01:46 +02:00
Andre Puschmann 28de7a9c93 pssch_test: expose start SF index as parameter and use helper to calc PRB 2020-04-27 21:01:46 +02:00
Andre Puschmann 955960f22d write decoded PSSCH symbols to file with PHY debug enabled 2020-04-27 21:01:46 +02:00
luis_pereira87 baf0ad5bf4 PSSCH implementation 2020-04-27 21:01:46 +02:00
Andre Puschmann 13b59b42c7 npdcch: replace fixme with todo 2020-04-24 12:21:17 +02:00
Xavier Arteaga 89dcd6339f More LGTM fixes 2020-04-22 18:01:43 +02:00
Xavier Arteaga 77d5dedddc Fix LGTM warnings and recommendations 2020-04-22 18:01:43 +02:00
Xavier Arteaga 562590e595 Fix LGTM warnings 2020-04-22 18:01:43 +02:00
Xavier Arteaga a7525d3e12 Fix somememory leaks 2020-04-20 16:10:27 +02:00
Xavier Arteaga e6792cf9b7 Refactored OFDM and added half CP window offset in UL Demodulator 2020-04-20 16:10:27 +02:00
Andre Puschmann c145d80547 nbiot: address review comments 2020-04-17 23:12:11 +02:00
Andre Puschmann e76e31e652 adding NB-IoT DL shared channel, UE DL object and PHY examples 2020-04-17 23:12:11 +02:00
luis_pereira87 653a1e0619 Added PSBCH Extended CP 2020-04-15 21:59:14 +02:00
Andre Puschmann 8e7b49b949 pscch: fix PSCCH memory allocation and failing tests 
the missing mem zero'ing caused the unit test to fail on some
machines where the memory wasn't initialized by default.

for d and d16 allocate the maximum number of bits, not
only the max length of a DCI
 2020-04-15 13:42:26 +02:00
Xavier Arteaga 11a8db202a Removed PDSCH traces 2020-04-15 11:39:57 +02:00
Xavier Arteaga 210ce0ac48 Fix modulation table 2020-04-15 11:39:57 +02:00
Xavier Arteaga 93771126ed More clear PDSCH CP function 2020-04-15 11:39:57 +02:00
Xavier Arteaga a0fb150e58 Fix memory issues in PSCCH decoder 2020-04-13 20:39:15 +02:00
Xavier Arteaga 5b7493cab5 Added 256QAM modulation tables to scheduler 2020-04-10 17:48:53 +02:00
Xavier Arteaga 784bf81a1a Multiple fixes HARQ ACK/NACK feedback and CSI reporting for MIMO and CA 2020-04-10 15:58:25 +02:00
Tiago Alves 47145c18b7 sidelink: refactor channel estimation 2020-04-10 14:58:18 +02:00
Xavier Arteaga 9a2b0b7cc7 Standard vector allocation uses vector library 2020-04-02 20:49:58 +02:00
Xavier Arteaga 2c93f6d20a Fix PUCCH DMRS correlation 2020-03-22 08:49:12 +01:00
Xavier Arteaga f3f03ad12d SRSUE PHY: Add extra debugging information to errors 2020-03-18 16:12:51 +01:00
Xavier Arteaga 0408d357a7 Minor fixes 2020-03-16 15:07:12 +01:00
Xavier Arteaga e832769ae6 Updated copyright 2020-03-16 11:26:06 +01:00
Xavier Arteaga 834a081c09 Add EPRE measurement to PUSCH decoder 2020-03-13 14:01:58 +01:00
Francisco Paisana fad897cb35 DL scheduler metric now takes into account the min and max of RBGs possible. This is to forbid segmentation of SRB0 allocations 2020-03-10 22:06:07 +00:00
Xavier Arteaga 002a68e183 SRSENB: hard-coded parametrized PUCCH DMRS correlation threshold 2020-03-10 09:19:54 +01:00
Xavier Arteaga 64caa4321b Fix UL control decoding. Some minor aesthetic changes. 2020-03-10 09:19:54 +01:00
Xavier Arteaga 5aff042c6e Avoid repeated PDCCH locations 2020-03-06 13:58:49 +01:00
Xavier Arteaga 02dd5bd8c4 Fix PUSCH segfault 2020-03-06 13:58:49 +01:00
Xavier Arteaga da701cd82b SRSENB: Added PUSCH TA and EVM measurement. Some more PHY cleanup. 2020-03-06 13:58:49 +01:00
Xavier Arteaga 47cbbcbd57 Improve PUSCH UCI decoder 2020-03-06 13:58:49 +01:00
Andre Puschmann 4553ce7ff1 temporarily disable SCI checks for PSCCH file tests 2020-03-06 11:20:11 +01:00
Francisco Paisana a6320f93b8 remove remaining const_casts 2020-03-05 20:23:07 +00:00
Francisco Paisana ec1f1cc677 remove const_casts from scheduler. Fix ODR issue 2020-03-05 20:23:07 +00:00
Andre Puschmann 3adfbcadbc disbable three Sidelink tests that are currently failing on AVX2 2020-03-03 16:22:51 +01:00
Andre Puschmann e4b5fa122f add set_cell() call to PSCCH and allocate for max PRB in pscch_init() 2020-03-03 16:22:51 +01:00
Andre Puschmann 151ce10a96 remove SL specific CFO correction method 2020-03-03 16:22:51 +01:00
Andre Puschmann 09f7355870 use srslte_cell_sl_t in PSCCH 2020-03-03 16:22:51 +01:00
Andre Puschmann 14000f7ae7 adding phy_common_sl.{c,h} 2020-03-03 16:22:51 +01:00
Andre Puschmann d85339187a pass offset parameter to CMW capture to compensate SFO 2020-03-03 16:22:51 +01:00
Tiago Alves cabd9ae742 baseline implementation of pscch 2020-03-03 16:22:51 +01:00
Xavier Arteaga a4135e41a5 Added PUCCH collision checker 2020-03-02 12:19:09 +01:00
Xavier Arteaga 2fc0832f05 Addition of DL HARQ-ACK generation procedure for eNb DL and minor aesthetic changes 2020-03-02 12:19:09 +01:00
Xavier Arteaga e621853566 Minor aesthetics changes 2020-02-28 12:10:32 +01:00
Xavier Arteaga f261365c91 Initial EVM calculation commit and other easthetic changes 2020-02-28 12:10:32 +01:00
Ismael Gomez 72e6fa40fc Fix multiple issues with DCI sizes when using CA. 2020-02-17 11:21:34 +01:00
Ismael Gomez d8d10daebe
Fix bug in SRS using the previous grant to compute collision with PUSCH (#958) 2020-02-16 21:30:04 +01:00
Xavier Arteaga 6c960da808 Fix UE's SR transmission 2020-02-13 16:10:26 +01:00
Xavier Arteaga 385102fa2d SRSENB: minor format, renaming and interface changes 2020-02-13 10:29:00 +01:00
Xavier Arteaga 67c07dfb56 Moved UL/DL PUCCH procedures into pucch_proc 2020-02-13 10:29:00 +01:00
Xavier Arteaga bc10943a2b Added get max TB from DCI format 2020-02-13 10:29:00 +01:00
Xavier Arteaga 231431f569 SRSENB: enabled CA PUCCH decode in eNb 2020-02-13 10:29:00 +01:00
Xavier Arteaga f6cf7780e8 Minor aesthetic corrections 2020-02-13 10:29:00 +01:00
Xavier Arteaga d66fdefbb3 Added more docs to PUCCH 1b CS resource selection 2020-02-13 10:29:00 +01:00
Xavier Arteaga b4d1f737f3 Minor PUCCH 1b CS resouce selection fix 2020-02-13 10:29:00 +01:00
Xavier Arteaga cd12307c91 SRSLTE: fix PUCCH 1b Channel selection resource 2020-02-13 10:29:00 +01:00
Xavier Arteaga 86a62c3584 removed unreachable code 2020-02-13 10:29:00 +01:00
Xavier Arteaga 1f762844ee Initial PUCCH format 3 decoder 2020-02-13 10:29:00 +01:00
Xavier Arteaga 35f4e5d69a Initial PUCCH 1B with channel selection 2020-02-13 10:29:00 +01:00
Xavier Arteaga f8294fb9df SRSUE: RRC measurements refactor and more fixes 2020-02-03 12:51:46 +01:00
Andre Puschmann 81b46723f6 adding NPDCCH 2020-01-28 17:46:54 +01:00
Andre Puschmann 073c57dc3d add NB-IoT DCI formats and move define to phy_common 2020-01-28 17:46:54 +01:00
Ismael Gomez 171e26ee68 Add checks more checks for UL grants 2020-01-24 10:40:39 +01:00
Xavier Arteaga dcb3bc0135 srsLTE: apply CLang Format in sch.c 2020-01-24 10:40:39 +01:00
Xavier Arteaga 905273b36a srsLTE: more memory corruption counter measures in ul_sch_encode 2020-01-24 10:40:39 +01:00
Xavier Arteaga 3b138b25c6 srsLTE: UL SCH Beta offset access fortification 2020-01-24 10:40:39 +01:00
Andre Puschmann b43c531c15 adding CMW500 SLSS capture and enable PSBCH test 2020-01-14 21:23:43 +01:00
Andre Puschmann d98bc71057 fix PSBCH and use UL-SCH interleaver 2020-01-14 21:23:43 +01:00
Andre Puschmann 9012ca5faa fix PSBCH tests 2020-01-14 21:23:43 +01:00
Andre Puschmann 2e7a357226 expose UL-SCH interleaver to use in Sidelink 2020-01-14 21:23:43 +01:00
Andre Puschmann 0554064bf0 refactor NPBCH init, fix memset with zero length 2020-01-07 11:12:34 +01:00
Xavier Arteaga 0912701cb0 srsLTE: sidelink minor corrections 2019-12-23 23:08:32 +01:00