srsLTE/lib/test/phy
Xavier Arteaga cfe2b305a1 Fix CORESET0 related PDSCH resource allocation procedure 2021-08-26 09:34:43 +02:00
..
CMakeLists.txt Add PDCCH interleaved mapping in phy_dl_nr_test and iterate all possible 15kHz SCS bandwidths 2021-08-26 09:34:43 +02:00
phy_dl_nr_test.c Fix CORESET0 related PDSCH resource allocation procedure 2021-08-26 09:34:43 +02:00
phy_dl_test.c Optimised random bit (unpacked) and byte (packed) generator 2021-06-15 12:44:21 +02:00
pucch_ca_test.c rename srsLTE to srsRAN 2021-03-21 21:47:01 +01:00