Xavier Arteaga 1dcd75a6c7 Ignore CRC for RV!=0 in phy_dl_nr_test		2021-04-07 13:56:06 +02:00
..
adt	Reimplement batch-based background object/memory pool	2021-04-07 12:02:22 +01:00
asn1	Adding NR phy config RRC parsing	2021-03-25 11:34:53 +01:00
common	fix network utils test	2021-04-02 11:42:50 +01:00
mac	rename srsLTE to srsRAN	2021-03-21 21:47:01 +01:00
phy	Ignore CRC for RV!=0 in phy_dl_nr_test	2021-04-07 13:56:06 +02:00
srslog	- Introduce a new tracer scoped object that only records if the event duration exceeds the programmed threshold.	2021-03-26 10:31:26 +01:00
upper	rlc_stress_test: add RLC UM NR 12bit stresstest	2021-03-25 08:06:49 +01:00
CMakeLists.txt	rename srsLTE to srsRAN	2021-03-21 21:47:01 +01:00