mirror of https://github.com/PentHertz/srsLTE.git
249 lines
6.7 KiB
C++
249 lines
6.7 KiB
C++
/**
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*
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* \section COPYRIGHT
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*
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* Copyright 2013-2017 Software Radio Systems Limited
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*
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* \section LICENSE
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*
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* This file is part of srsLTE.
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*
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* srsUE is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Affero General Public License as
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* published by the Free Software Foundation, either version 3 of
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* the License, or (at your option) any later version.
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*
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* srsUE is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Affero General Public License for more details.
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*
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* A copy of the GNU Affero General Public License can be found in
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* the LICENSE file in the top-level directory of this distribution
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* and at http://www.gnu.org/licenses/.
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*
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*/
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#include "srslte/srslte.h"
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#ifndef SCHED_INTERFACE_H
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#define SCHED_INTERFACE_H
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namespace srsenb {
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class sched_interface
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{
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public:
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const static int MAX_SIB_PAYLOAD_LEN = 2048;
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const static int MAX_SIBS = 16;
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const static int MAX_LC = 6;
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const static int MAX_DATA_LIST = 32;
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const static int MAX_RAR_LIST = 8;
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const static int MAX_BC_LIST = 8;
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const static int MAX_RLC_PDU_LIST = 8;
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const static int MAX_PHICH_LIST = 8;
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typedef struct {
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uint32_t len;
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uint32_t period_rf;
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} cell_cfg_sib_t;
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typedef struct {
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int pdsch_mcs;
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int pdsch_max_mcs;
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int pusch_mcs;
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int pusch_max_mcs;
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int nof_ctrl_symbols;
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} sched_args_t;
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typedef struct {
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// Main cell configuration (used to calculate DCI locations in scheduler)
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srslte_cell_t cell;
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/* SIB configuration */
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cell_cfg_sib_t sibs[MAX_SIBS];
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uint32_t si_window_ms;
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/* pusch configuration */
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srslte_pusch_hopping_cfg_t pusch_hopping_cfg;
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/* prach configuration */
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uint32_t prach_config;
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uint32_t prach_freq_offset;
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uint32_t prach_rar_window;
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uint32_t prach_contention_resolution_timer;
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uint32_t maxharq_msg3tx;
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uint32_t n1pucch_an;
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uint32_t delta_pucch_shift;
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uint32_t nrb_cqi;
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uint32_t ncs_an;
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uint32_t srs_subframe_config;
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uint32_t srs_subframe_offset;
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uint32_t srs_bw_config;
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} cell_cfg_t;
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typedef struct {
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int priority;
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int bsd;
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int pbr;
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int group;
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enum {IDLE = 0, UL, DL, BOTH} direction;
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} ue_bearer_cfg_t;
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typedef struct {
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bool continuous_pusch;
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/* ue capabilities, etc */
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uint32_t maxharq_tx;
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uint32_t aperiodic_cqi_period; // if 0 is periodic CQI
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uint32_t beta_ack_index;
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uint32_t beta_ri_index;
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uint32_t beta_cqi_index;
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srslte_pucch_cfg_t pucch_cfg;
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uint32_t n_pucch_cqi;
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uint32_t sr_I;
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uint32_t sr_N_pucch;
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bool sr_enabled;
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uint32_t cqi_pucch;
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uint32_t cqi_idx;
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bool cqi_enabled;
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ue_bearer_cfg_t ue_bearers[MAX_LC];
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} ue_cfg_t;
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typedef struct {
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uint32_t lcid;
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uint32_t nbytes;
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} dl_sched_pdu_t;
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typedef struct {
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uint32_t rnti;
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srslte_ra_dl_dci_t dci;
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srslte_dci_location_t dci_location;
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uint32_t tbs;
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bool mac_ce_ta;
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bool mac_ce_rnti;
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uint32_t nof_pdu_elems;
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dl_sched_pdu_t pdu[MAX_RLC_PDU_LIST];
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} dl_sched_data_t;
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typedef struct {
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uint32_t rnti;
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bool needs_pdcch;
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uint32_t current_tx_nb;
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uint32_t tbs;
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srslte_ra_ul_dci_t dci;
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srslte_dci_location_t dci_location;
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} ul_sched_data_t;
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typedef struct {
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uint32_t ra_id;
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srslte_dci_rar_grant_t grant;
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} dl_sched_rar_grant_t;
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typedef struct {
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uint32_t rarnti;
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uint32_t tbs;
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srslte_ra_dl_dci_t dci;
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srslte_dci_location_t dci_location;
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uint32_t nof_grants;
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dl_sched_rar_grant_t grants[MAX_RAR_LIST];
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} dl_sched_rar_t;
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typedef struct {
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srslte_ra_dl_dci_t dci;
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srslte_dci_location_t dci_location;
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enum bc_type {
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BCCH, PCCH
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} type;
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uint32_t index;
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uint32_t tbs;
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} dl_sched_bc_t;
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typedef struct {
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uint32_t cfi;
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uint32_t nof_data_elems;
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uint32_t nof_rar_elems;
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uint32_t nof_bc_elems;
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dl_sched_data_t data[MAX_DATA_LIST];
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dl_sched_rar_t rar[MAX_RAR_LIST];
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dl_sched_bc_t bc[MAX_BC_LIST];
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} dl_sched_res_t;
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typedef struct {
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uint16_t rnti;
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enum phich_elem {
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ACK, NACK
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} phich;
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} ul_sched_phich_t;
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typedef struct {
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uint32_t nof_dci_elems;
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uint32_t nof_phich_elems;
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ul_sched_data_t pusch[MAX_DATA_LIST];
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ul_sched_phich_t phich[MAX_PHICH_LIST];
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} ul_sched_res_t;
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/******************* Scheduler Control ****************************/
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/* Provides cell configuration including SIB periodicity, etc. */
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virtual int cell_cfg(cell_cfg_t *cell_cfg) = 0;
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virtual int reset() = 0;
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/* Manages UE scheduling context */
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virtual int ue_cfg(uint16_t rnti, ue_cfg_t *cfg) = 0;
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virtual int ue_rem(uint16_t rnti) = 0;
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virtual bool ue_exists(uint16_t rnti) = 0;
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/* Manages UE bearers and associated configuration */
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virtual int bearer_ue_cfg(uint16_t rnti, uint32_t lc_id, ue_bearer_cfg_t *cfg) = 0;
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virtual int bearer_ue_rem(uint16_t rnti, uint32_t lc_id) = 0;
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virtual uint32_t get_ul_buffer(uint16_t rnti) = 0;
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virtual uint32_t get_dl_buffer(uint16_t rnti) = 0;
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/******************* Scheduling Interface ***********************/
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/* DL buffer status report */
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virtual int dl_rlc_buffer_state(uint16_t rnti, uint32_t lc_id, uint32_t tx_queue, uint32_t retx_queue) = 0;
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virtual int dl_mac_buffer_state(uint16_t rnti, uint32_t ce_code) = 0;
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/* DL information */
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virtual int dl_ack_info(uint32_t tti, uint16_t rnti, bool ack) = 0;
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virtual int dl_rach_info(uint32_t tti, uint32_t ra_id, uint16_t rnti, uint32_t estimated_size) = 0;
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virtual int dl_cqi_info(uint32_t tti, uint16_t rnti, uint32_t cqi_value) = 0;
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/* UL information */
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virtual int ul_crc_info(uint32_t tti, uint16_t rnti, bool crc) = 0;
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virtual int ul_sr_info(uint32_t tti, uint16_t rnti) = 0;
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virtual int ul_bsr(uint16_t rnti, uint32_t lcid, uint32_t bsr, bool set_value = true) = 0;
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virtual int ul_recv_len(uint16_t rnti, uint32_t lcid, uint32_t len) = 0;
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virtual int ul_phr(uint16_t rnti, int phr) = 0;
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virtual int ul_cqi_info(uint32_t tti, uint16_t rnti, uint32_t cqi, uint32_t ul_ch_code) = 0;
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/* Run Scheduler for this tti */
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virtual int dl_sched(uint32_t tti, dl_sched_res_t *sched_result) = 0;
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virtual int ul_sched(uint32_t tti, ul_sched_res_t *sched_result) = 0;
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};
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}
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#endif
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