Xavier Arteaga dd26c6a90e Added more comments for better understanding in NR PDCCH DMRS		2021-04-12 17:05:53 +02:00
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examples	rename srsLTE to srsRAN	2021-03-21 21:47:01 +01:00
include	Fix NR TDD pattern configuration	2021-04-12 17:05:53 +02:00
src	Added more comments for better understanding in NR PDCCH DMRS	2021-04-12 17:05:53 +02:00
test	NR PDSCH zeroes RE around the DC. Added delay and CFO emulation to phy_dl_nr_test	2021-04-12 17:05:53 +02:00
CMakeLists.txt	rename srsLTE to srsRAN	2021-03-21 21:47:01 +01:00