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Clear interrupt flag before enabling schedule timers on T4.1

This commit is contained in:
Josh Stewart 2024-05-09 19:31:12 +10:00
parent 8138651740
commit 3390808606
1 changed files with 24 additions and 24 deletions
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48
speeduino/board_teensy41.h
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@ -82,14 +82,14 @@
#define IGN7_COMPARE TMR4_COMP12
#define IGN8_COMPARE TMR4_COMP13
static inline void FUEL1_TIMER_ENABLE(void) {TMR1_CSCTRL0 |= TMR_CSCTRL_TCF1EN;} //Write 1 to the TCFIEN (Channel Interrupt Enable) bit of channel 0 Status/Control
static inline void FUEL2_TIMER_ENABLE(void) {TMR1_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
static inline void FUEL3_TIMER_ENABLE(void) {TMR1_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
static inline void FUEL4_TIMER_ENABLE(void) {TMR1_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
static inline void FUEL5_TIMER_ENABLE(void) {TMR3_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
static inline void FUEL6_TIMER_ENABLE(void) {TMR3_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
static inline void FUEL7_TIMER_ENABLE(void) {TMR3_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
static inline void FUEL8_TIMER_ENABLE(void) {TMR3_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
static inline void FUEL1_TIMER_ENABLE(void) {TMR1_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL0 |= TMR_CSCTRL_TCF1EN;} //Write 1 to the TCFIEN (Channel Interrupt Enable) bit of channel 0 Status/Control
static inline void FUEL2_TIMER_ENABLE(void) {TMR1_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
static inline void FUEL3_TIMER_ENABLE(void) {TMR1_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
static inline void FUEL4_TIMER_ENABLE(void) {TMR1_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
static inline void FUEL5_TIMER_ENABLE(void) {TMR3_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
static inline void FUEL6_TIMER_ENABLE(void) {TMR3_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
static inline void FUEL7_TIMER_ENABLE(void) {TMR3_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
static inline void FUEL8_TIMER_ENABLE(void) {TMR3_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
static inline void FUEL1_TIMER_DISABLE(void) {TMR1_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;} //Write 0 to the TCFIEN (Channel Interrupt Enable) bit of channel 0 Status/Control
static inline void FUEL2_TIMER_DISABLE(void) {TMR1_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
@ -100,23 +100,23 @@
static inline void FUEL7_TIMER_DISABLE(void) {TMR3_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
static inline void FUEL8_TIMER_DISABLE(void) {TMR3_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN1_TIMER_ENABLE(void) {TMR2_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN2_TIMER_ENABLE(void) {TMR2_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN3_TIMER_ENABLE(void) {TMR2_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN4_TIMER_ENABLE(void) {TMR2_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN5_TIMER_ENABLE(void) {TMR4_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN6_TIMER_ENABLE(void) {TMR4_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN7_TIMER_ENABLE(void) {TMR4_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN8_TIMER_ENABLE(void) {TMR4_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN1_TIMER_ENABLE(void) {TMR2_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN2_TIMER_ENABLE(void) {TMR2_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN3_TIMER_ENABLE(void) {TMR2_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN4_TIMER_ENABLE(void) {TMR2_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN5_TIMER_ENABLE(void) {TMR4_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN6_TIMER_ENABLE(void) {TMR4_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN7_TIMER_ENABLE(void) {TMR4_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN8_TIMER_ENABLE(void) {TMR4_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
static inline void IGN1_TIMER_DISABLE(void) {TMR2_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN2_TIMER_DISABLE(void) {TMR2_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN3_TIMER_DISABLE(void) {TMR2_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN4_TIMER_DISABLE(void) {TMR2_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN5_TIMER_DISABLE(void) {TMR4_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN6_TIMER_DISABLE(void) {TMR4_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN7_TIMER_DISABLE(void) {TMR4_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN8_TIMER_DISABLE(void) {TMR4_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN1_TIMER_DISABLE(void) {TMR2_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN2_TIMER_DISABLE(void) {TMR2_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN3_TIMER_DISABLE(void) {TMR2_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN4_TIMER_DISABLE(void) {TMR2_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN5_TIMER_DISABLE(void) {TMR4_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN6_TIMER_DISABLE(void) {TMR4_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN7_TIMER_DISABLE(void) {TMR4_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
static inline void IGN8_TIMER_DISABLE(void) {TMR4_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
//Bus Clock is 150Mhz @ 600 Mhz CPU. Need to handle this dynamically in the future for other frequencies
//#define TMR_PRESCALE 128