415 lines
18 KiB
C++
415 lines
18 KiB
C++
#if defined(CORE_TEENSY) && defined(CORE_TEENSY35)
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#include "board_teensy35.h"
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#include "globals.h"
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#include "auxiliaries.h"
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#include "idle.h"
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#include "scheduler.h"
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#if defined(__MK64FX512__) // use for Teensy 3.5 only
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FlexCAN_T4<CAN0, RX_SIZE_256, TX_SIZE_16> Can0;
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#elif defined(__MK66FX1M0__) // use for Teensy 3.6 only
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FlexCAN_T4<CAN0, RX_SIZE_256, TX_SIZE_16> Can0;
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FlexCAN_T4<CAN1, RX_SIZE_256, TX_SIZE_16> Can1;
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#endif
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void initBoard()
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{
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/*
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***********************************************************************************************************
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* General
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*/
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/*
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***********************************************************************************************************
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* Idle
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*/
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if ((configPage6.iacAlgorithm == IAC_ALGORITHM_PWM_OL) || (configPage6.iacAlgorithm == IAC_ALGORITHM_PWM_CL) || (configPage6.iacAlgorithm == IAC_ALGORITHM_PWM_OLCL))
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{
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//FlexTimer 2, compare channel 0 is used for idle
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FTM2_MODE |= FTM_MODE_WPDIS; // Write Protection Disable
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FTM2_MODE |= FTM_MODE_FTMEN; //Flex Timer module enable
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FTM2_MODE |= FTM_MODE_INIT;
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FTM2_SC = 0x00; // Set this to zero before changing the modulus
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FTM2_CNTIN = 0x0000; //Shouldn't be needed, but just in case
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FTM2_CNT = 0x0000; // Reset the count to zero
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FTM2_MOD = 0xFFFF; // max modulus = 65535
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/*
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* Enable the clock for FTM0/1
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* 00 No clock selected. Disables the FTM counter.
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* 01 System clock
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* 10 Fixed frequency clock (32kHz)
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* 11 External clock
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*/
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FTM2_SC |= FTM_SC_CLKS(0b10);
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/*
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* Trim the slow clock from 32kHz down to 31.25kHz (The slowest it will go)
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* This is somewhat imprecise and documentation is not good.
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* I poked the chip until I figured out the values associated with 31.25kHz
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*/
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MCG_C3 = 0x9B;
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/*
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* Set Prescaler
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* This is the slowest that the timer can be clocked . It results in ticks of 32uS on the teensy 3.5:
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* 31250 Hz = Slow_clock
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* 1 * 1000000uS / Slow_clock = 32uS
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*
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* 000 = Divide by 1
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* 001 Divide by 2
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* 010 Divide by 4
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* 011 Divide by 8
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* 100 Divide by 16
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* 101 Divide by 32
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* 110 Divide by 64
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* 111 Divide by 128
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*/
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FTM2_SC |= FTM_SC_PS(0b0); //No prescaler
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//Setup the channels (See Pg 1014 of K64 DS).
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FTM2_C0SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM2_C0SC |= FTM_CSC_MSA; //Enable Compare mode
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//The below enables channel compare interrupt, but this is done in idleControl()
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//FTM2_C0SC |= FTM_CSC_CHIE;
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FTM2_C1SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM2_C1SC |= FTM_CSC_MSA; //Enable Compare mode
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//Enable channel compare interrupt (This is currently disabled as not in use)
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//FTM2_C1SC |= FTM_CSC_CHIE;
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//Enable IRQ Interrupt
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NVIC_ENABLE_IRQ(IRQ_FTM2);
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}
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/*
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***********************************************************************************************************
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* Auxiliaries
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*/
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/*
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***********************************************************************************************************
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* BOOST and VVT
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*/
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if (configPage6.boostEnabled == 1 || configPage6.vvtEnabled == 1)
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{
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//FlexTimer 2, compare channel 0 is used for idle
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FTM1_MODE |= FTM_MODE_WPDIS; // Write Protection Disable
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FTM1_MODE |= FTM_MODE_FTMEN; //Flex Timer module enable
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FTM1_MODE |= FTM_MODE_INIT;
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FTM1_SC = 0x00; // Set this to zero before changing the modulus
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FTM1_CNTIN = 0x0000; //Shouldn't be needed, but just in case
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FTM1_CNT = 0x0000; // Reset the count to zero
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FTM1_MOD = 0xFFFF; // max modulus = 65535
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/*
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* Enable the clock for FTM0/1
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* 00 No clock selected. Disables the FTM counter.
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* 01 System clock
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* 10 Fixed frequency clock (32kHz)
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* 11 External clock
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*/
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FTM1_SC |= FTM_SC_CLKS(0b10);
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/*
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* Trim the slow clock from 32kHz down to 31.25kHz (The slowest it will go)
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* This is somewhat imprecise and documentation is not good.
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* I poked the chip until I figured out the values associated with 31.25kHz
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*/
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MCG_C3 = 0x9B;
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/*
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* Set Prescaler
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* This is the slowest that the timer can be clocked . It results in ticks of 32uS on the teensy 3.5:
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* 31250 Hz = Slow_clock
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* 1 * 1000000uS / Slow_clock = 32uS
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*
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* 000 = Divide by 1
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* 001 Divide by 2
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* 010 Divide by 4
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* 011 Divide by 8
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* 100 Divide by 16
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* 101 Divide by 32
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* 110 Divide by 64
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* 111 Divide by 128
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*/
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FTM1_SC |= FTM_SC_PS(0b0); //No prescaler
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//Setup the channels (See Pg 1014 of K64 DS).
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FTM1_C0SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM1_C0SC |= FTM_CSC_MSA; //Enable Compare mode
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//The below enables channel compare interrupt, but this is done in idleControl()
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//FTM1_C0SC |= FTM_CSC_CHIE;
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FTM1_C1SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM1_C1SC |= FTM_CSC_MSA; //Enable Compare mode
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//Enable channel compare interrupt (This is currently disabled as not in use)
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//FTM1_C1SC |= FTM_CSC_CHIE;
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FTM2_C1SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM2_C1SC |= FTM_CSC_MSA; //Enable Compare mode
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//Enable channel compare interrupt (This is currently disabled as not in use)
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//FTM1_C2SC |= FTM_CSC_CHIE;
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//Enable IRQ Interrupt
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NVIC_ENABLE_IRQ(IRQ_FTM1);
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boost_pwm_max_count = 1000000L / (32 * configPage6.boostFreq * 2); //Converts the frequency in Hz to the number of ticks (at 16uS) it takes to complete 1 cycle. Note that the frequency is divided by 2 coming from TS to allow for up to 512hz
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vvt_pwm_max_count = 1000000L / (32 * configPage6.vvtFreq * 2); //Converts the frequency in Hz to the number of ticks (at 16uS) it takes to complete 1 cycle. Note that the frequency is divided by 2 coming from TS to allow for up to 512hz
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fan_pwm_max_count = 1000000L / (32 * configPage6.fanFreq * 2); //Converts the frequency in Hz to the number of ticks (at 16uS) it takes to complete 1 cycle. Note that the frequency is divided by 2 coming from TS to allow for up to 512hz
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}
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/*
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***********************************************************************************************************
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* Timers
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*/
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//Uses the PIT timer on Teensy.
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lowResTimer.begin(oneMSInterval, 1000);
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/*
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***********************************************************************************************************
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* Schedules
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*/
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//FlexTimer 0 is used for 4 ignition and 4 injection schedules. There are 8 channels on this module, so no other timers are needed
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FTM0_MODE |= FTM_MODE_WPDIS; //Write Protection Disable
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FTM0_MODE |= FTM_MODE_FTMEN; //Flex Timer module enable
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FTM0_MODE |= FTM_MODE_INIT;
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FTM0_SC = 0x00; // Set this to zero before changing the modulus
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FTM0_CNTIN = 0x0000; //Shouldn't be needed, but just in case
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FTM0_CNT = 0x0000; //Reset the count to zero
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FTM0_MOD = 0xFFFF; //max modulus = 65535
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//FlexTimer 3 is used for schedules on channel 5+. Currently only channel 5 is used, but will likely be expanded later
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FTM3_MODE |= FTM_MODE_WPDIS; //Write Protection Disable
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FTM3_MODE |= FTM_MODE_FTMEN; //Flex Timer module enable
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FTM3_MODE |= FTM_MODE_INIT;
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FTM3_SC = 0x00; // Set this to zero before changing the modulus
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FTM3_CNTIN = 0x0000; //Shouldn't be needed, but just in case
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FTM3_CNT = 0x0000; //Reset the count to zero
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FTM3_MOD = 0xFFFF; //max modulus = 65535
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/*
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* Enable the clock for FTM0/1
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* 00 No clock selected. Disables the FTM counter.
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* 01 System clock
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* 10 Fixed frequency clock
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* 11 External clock
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*/
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FTM0_SC |= FTM_SC_CLKS(0b1);
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FTM3_SC |= FTM_SC_CLKS(0b1);
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/*
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* Set Prescaler
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* This is the slowest that the timer can be clocked (Without used the slow timer, which is too slow). It results in ticks of 2.13333uS on the teensy 3.5:
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* 60000000 Hz = F_BUS
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* 128 * 1000000uS / F_BUS = 2.133uS
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*
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* 000 = Divide by 1
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* 001 Divide by 2
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* 010 Divide by 4
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* 011 Divide by 8
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* 100 Divide by 16
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* 101 Divide by 32
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* 110 Divide by 64
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* 111 Divide by 128
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*/
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FTM0_SC |= FTM_SC_PS(0b111);
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FTM3_SC |= FTM_SC_PS(0b111);
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//Setup the channels (See Pg 1014 of K64 DS).
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//The are probably not needed as power on state should be 0
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//FTM0_C0SC &= ~FTM_CSC_ELSB;
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//FTM0_C0SC &= ~FTM_CSC_ELSA;
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//FTM0_C0SC &= ~FTM_CSC_DMA;
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FTM0_C0SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM0_C0SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM0_C0SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM0_C1SC &= ~FTM_CSC_MSB; //According to Pg 965 of the datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM0_C1SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM0_C1SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM0_C2SC &= ~FTM_CSC_MSB; //According to Pg 965 of the datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM0_C2SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM0_C2SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM0_C3SC &= ~FTM_CSC_MSB; //According to Pg 965 of the datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM0_C3SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM0_C3SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM0_C4SC &= ~FTM_CSC_MSB; //According to Pg 965 of the datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM0_C4SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM0_C4SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM0_C5SC &= ~FTM_CSC_MSB; //According to Pg 965 of the datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM0_C5SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM0_C5SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM0_C6SC &= ~FTM_CSC_MSB; //According to Pg 965 of the datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM0_C6SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM0_C6SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM0_C7SC &= ~FTM_CSC_MSB; //According to Pg 965 of the datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM0_C7SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM0_C7SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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//Do the same, but on flex timer 3 (Used for channels 5-8)
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FTM3_C0SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM3_C0SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM3_C0SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM3_C1SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM3_C1SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM3_C1SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM3_C2SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM3_C2SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM3_C2SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM3_C3SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM3_C3SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM3_C3SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM3_C4SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM3_C4SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM3_C4SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM3_C5SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM3_C5SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM3_C5SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM3_C6SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM3_C6SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM3_C6SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM3_C7SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM3_C7SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM3_C7SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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// enable IRQ Interrupt
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NVIC_ENABLE_IRQ(IRQ_FTM0);
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NVIC_ENABLE_IRQ(IRQ_FTM3);
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}
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void ftm0_isr(void)
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{
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//Use separate variables for each test to ensure conversion to bool
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bool interrupt1 = (FTM0_C0SC & FTM_CSC_CHF);
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bool interrupt2 = (FTM0_C1SC & FTM_CSC_CHF);
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bool interrupt3 = (FTM0_C2SC & FTM_CSC_CHF);
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bool interrupt4 = (FTM0_C3SC & FTM_CSC_CHF);
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bool interrupt5 = (FTM0_C4SC & FTM_CSC_CHF);
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bool interrupt6 = (FTM0_C5SC & FTM_CSC_CHF);
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bool interrupt7 = (FTM0_C6SC & FTM_CSC_CHF);
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bool interrupt8 = (FTM0_C7SC & FTM_CSC_CHF);
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if(interrupt1) { FTM0_C0SC &= ~FTM_CSC_CHF; fuelSchedule1Interrupt(); }
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else if(interrupt2) { FTM0_C1SC &= ~FTM_CSC_CHF; fuelSchedule2Interrupt(); }
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else if(interrupt3) { FTM0_C2SC &= ~FTM_CSC_CHF; fuelSchedule3Interrupt(); }
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else if(interrupt4) { FTM0_C3SC &= ~FTM_CSC_CHF; fuelSchedule4Interrupt(); }
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else if(interrupt5) { FTM0_C4SC &= ~FTM_CSC_CHF; ignitionSchedule1Interrupt(); }
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else if(interrupt6) { FTM0_C5SC &= ~FTM_CSC_CHF; ignitionSchedule2Interrupt(); }
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else if(interrupt7) { FTM0_C6SC &= ~FTM_CSC_CHF; ignitionSchedule3Interrupt(); }
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else if(interrupt8) { FTM0_C7SC &= ~FTM_CSC_CHF; ignitionSchedule4Interrupt(); }
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}
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void ftm3_isr(void)
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{
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#if (INJ_CHANNELS >= 5)
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bool interrupt1 = (FTM3_C0SC & FTM_CSC_CHF);
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if(interrupt1) { FTM3_C0SC &= ~FTM_CSC_CHF; fuelSchedule5Interrupt(); }
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#endif
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#if (INJ_CHANNELS >= 6)
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bool interrupt2 = (FTM3_C1SC & FTM_CSC_CHF);
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if(interrupt2) { FTM3_C1SC &= ~FTM_CSC_CHF; fuelSchedule6Interrupt(); }
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#endif
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#if (INJ_CHANNELS >= 7)
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bool interrupt3 = (FTM3_C2SC & FTM_CSC_CHF);
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if(interrupt3) { FTM3_C2SC &= ~FTM_CSC_CHF; fuelSchedule7Interrupt(); }
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#endif
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#if (INJ_CHANNELS >= 8)
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bool interrupt4 = (FTM3_C3SC & FTM_CSC_CHF);
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if(interrupt4) { FTM3_C3SC &= ~FTM_CSC_CHF; fuelSchedule8Interrupt(); }
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#endif
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#if (IGN_CHANNELS >= 5)
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bool interrupt5 = (FTM3_C4SC & FTM_CSC_CHF);
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if(interrupt5) { FTM3_C4SC &= ~FTM_CSC_CHF; ignitionSchedule5Interrupt(); }
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#endif
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#if (IGN_CHANNELS >= 6)
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bool interrupt6 = (FTM3_C5SC & FTM_CSC_CHF);
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if(interrupt6) { FTM3_C5SC &= ~FTM_CSC_CHF; ignitionSchedule6Interrupt(); }
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#endif
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#if (IGN_CHANNELS >= 7)
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bool interrupt7 = (FTM3_C6SC & FTM_CSC_CHF);
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if(interrupt7) { FTM3_C6SC &= ~FTM_CSC_CHF; ignitionSchedule7Interrupt(); }
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#endif
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#if (IGN_CHANNELS >= 8)
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bool interrupt8 = (FTM3_C7SC & FTM_CSC_CHF);
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if(interrupt8) { FTM3_C7SC &= ~FTM_CSC_CHF; ignitionSchedule8Interrupt(); }
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#endif
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}
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//Boost and VVT handler
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void ftm1_isr(void)
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{
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//FTM1 only has 2 compare channels (Is this correct?)
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//Use separate variables for each test to ensure conversion to bool
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bool interrupt1 = (FTM1_C0SC & FTM_CSC_CHF);
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bool interrupt2 = (FTM1_C1SC & FTM_CSC_CHF);
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if(interrupt1) { FTM1_C0SC &= ~FTM_CSC_CHF; boostInterrupt(); }
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else if(interrupt2) { FTM1_C1SC &= ~FTM_CSC_CHF; vvtInterrupt(); }
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|
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}
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|
|
|
//Idle and spare handler
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|
void ftm2_isr(void)
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|
{
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|
//FTM2 only has 2 compare channels
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|
//Use separate variables for each test to ensure conversion to bool
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|
bool interrupt1 = (FTM2_C0SC & FTM_CSC_CHF);
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|
bool interrupt2 = (FTM2_C1SC & FTM_CSC_CHF); //For PWM Fan
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|
|
|
if(interrupt1) { FTM2_C0SC &= ~FTM_CSC_CHF; idleInterrupt(); }
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|
else if(interrupt2) { FTM2_C1SC &= ~FTM_CSC_CHF; fanInterrupt(); } //For PWM Fan
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|
}
|
|
|
|
uint16_t freeRam()
|
|
{
|
|
uint32_t freeRam;
|
|
uint32_t stackTop;
|
|
uint32_t heapTop;
|
|
|
|
// current position of the stack.
|
|
stackTop = (uint32_t)&stackTop;
|
|
|
|
// current position of heap.
|
|
void *hTop = malloc(1);
|
|
heapTop = (uint32_t)hTop;
|
|
free(hTop);
|
|
freeRam = stackTop - heapTop;
|
|
|
|
if(freeRam>0xFFFF){return 0xFFFF;}
|
|
else{return freeRam;}
|
|
}
|
|
|
|
//This function is used for attempting to set the RTC time during compile
|
|
time_t getTeensy3Time()
|
|
{
|
|
return Teensy3Clock.get();
|
|
}
|
|
|
|
void doSystemReset() { return; }
|
|
void jumpToBootloader() { return; }
|
|
|
|
#endif
|