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AT32F435_437_Firmware_Library
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update version to v2.0.4

This commit is contained in:
Artery-MCU 2022-01-21 16:05:17 +08:00
parent 6f186821a2
commit e26ade8ad4
3081 changed files with 50301 additions and 44634 deletions
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AT32F435_437_periph_lib_V2.0.2.chm → AT32F435_437_periph_lib_V2.0.4.chm
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document/ReleaseNotes_AT32F435_437_Firmware_Library.pdf
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15
libraries/cmsis/cm4/device_support/at32f435_437.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 header file
**************************************************************************
* Copyright notice & Disclaimer
@ -62,7 +62,7 @@ extern "C" {
!defined (AT32F437VCT7) && !defined (AT32F437VGT7) && !defined (AT32F437VMT7) && \
!defined (AT32F437ZCT7) && !defined (AT32F437ZGT7) && !defined (AT32F437ZMT7)
#error "Please select first the target at32f4xx device used in your application (in at32f4xx.h file)"
#error "Please select first the target device used in your application (in at32f435_437.h file)"
#endif
#if defined (AT32F435CCU7) || defined (AT32F435CGU7) || defined (AT32F435CMU7) || \
@ -100,7 +100,7 @@ extern "C" {
*/
#define __AT32F435_437_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F435_437_LIBRARY_VERSION_MIDDLE (0x00) /*!< [23:16] middle version */
#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x02) /*!< [15:8] minor version */
#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x04) /*!< [15:8] minor version */
#define __AT32F435_437_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F435_437_LIBRARY_VERSION ((__AT32F435_437_LIBRARY_VERSION_MAJOR << 24) | \
(__AT32F435_437_LIBRARY_VERSION_MIDDLE << 16) | \
@ -411,12 +411,10 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
#define QSPI1_REG_BASE ((uint32_t)0xA0001000)
#define XMC_REG_BASE ((uint32_t)0xA0000000)
#define XMC_BANK1_REG_BASE (XMC_REG_BASE + 0x0000)
#define XMC_BANK1E_REG_BASE (XMC_REG_BASE + 0x0104)
#define XMC_BANK1E_H_BASE (XMC_REG_BASE + 0x0220)
#define XMC_BANK2_REG_BASE (XMC_REG_BASE + 0x0060)
#define XMC_BANK3_REG_BASE (XMC_REG_BASE + 0x0080)
#define XMC_BANK4_REG_BASE (XMC_REG_BASE + 0x00A0)
#define XMC_BANK5_6_REG_BASE (XMC_REG_BASE + 0x0140)
#define XMC_SDRAM_REG_BASE (XMC_REG_BASE + 0x0140)
#define QSPI1_MEM_BASE ((uint32_t)0x90000000)
#define XMC_MEM_BASE ((uint32_t)0x60000000)
#define PERIPH_BASE ((uint32_t)0x40000000)
@ -770,7 +768,8 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
/**
* @}
*/
#include "at32f435_437_def.h"
#include "at32f435_437_conf.h"
#ifdef __cplusplus

4
libraries/cmsis/cm4/device_support/at32f435_437_conf_template.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_conf.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 config header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/cmsis/cm4/device_support/startup/gcc/startup_at32f435_437.s
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@ -1,8 +1,8 @@
/**
******************************************************************************
* @file startup_at32f435_437.s
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 devices vector table for gcc toolchain.
* this module performs:
* - set the initial sp

4
libraries/cmsis/cm4/device_support/startup/iar/startup_at32f435_437.s
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@ -1,7 +1,7 @@
;**************************************************************************
;* @file startup_at32f435_437.s
;* @version v2.0.2
;* @date 2021-11-26
;* @version v2.0.4
;* @date 2021-12-31
;* @brief at32f435_437 startup file for IAR Systems
;**************************************************************************
;

4
libraries/cmsis/cm4/device_support/startup/mdk/startup_at32f435_437.s
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@ -1,7 +1,7 @@
;**************************************************************************
;* @file startup_at32f435_437.s
;* @version v2.0.2
;* @date 2021-11-26
;* @version v2.0.4
;* @date 2021-12-31
;* @brief at32f435_437 startup file for keil
;**************************************************************************
;

4
libraries/cmsis/cm4/device_support/system_at32f435_437.c
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file system_at32f435_437.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for cmsis cortex-m4 system source file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/cmsis/cm4/device_support/system_at32f435_437.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file system_at32f435_437.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief cmsis cortex-m4 system header file.
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_acc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_acc.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 acc header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_adc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_adc.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 adc header file
**************************************************************************
* Copyright notice & Disclaimer

29
libraries/drivers/inc/at32f435_437_can.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_can.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 can header file
**************************************************************************
* Copyright notice & Disclaimer
@ -110,16 +110,21 @@ extern "C" {
/**
* @brief can flag clear operation macro definition val
*/
#define CAN_MSTS_EOIF_VAL ((uint32_t)0x00000004) /*!< eoif bit w1 */
#define CAN_MSTS_QDZIF_VAL ((uint32_t)0x00000008) /*!< qdzif bit w1 */
#define CAN_MSTS_EDZIF_VAL ((uint32_t)0x00000010) /*!< edzif bit w1 */
#define CAN_TSTS_TM0TCF_VAL ((uint32_t)0x00000001) /*!< tm0tcf bit w1 */
#define CAN_TSTS_TM1TCF_VAL ((uint32_t)0x00000100) /*!< tm1tcf bit w1 */
#define CAN_TSTS_TM2TCF_VAL ((uint32_t)0x00010000) /*!< tm2tcf bit w1 */
#define CAN_RF0_RF0FF_VAL ((uint32_t)0x00000008) /*!< rf0ff bit w1 */
#define CAN_RF0_RF0OF_VAL ((uint32_t)0x00000010) /*!< rf0of bit w1 */
#define CAN_RF1_RF1FF_VAL ((uint32_t)0x00000008) /*!< rf1ff bit w1 */
#define CAN_RF1_RF1OF_VAL ((uint32_t)0x00000010) /*!< rf1of bit w1 */
#define CAN_MSTS_EOIF_VAL ((uint32_t)0x00000004) /*!< eoif bit value, it clear by writing 1 */
#define CAN_MSTS_QDZIF_VAL ((uint32_t)0x00000008) /*!< qdzif bit value, it clear by writing 1 */
#define CAN_MSTS_EDZIF_VAL ((uint32_t)0x00000010) /*!< edzif bit value, it clear by writing 1 */
#define CAN_TSTS_TM0TCF_VAL ((uint32_t)0x00000001) /*!< tm0tcf bit value, it clear by writing 1 */
#define CAN_TSTS_TM1TCF_VAL ((uint32_t)0x00000100) /*!< tm1tcf bit value, it clear by writing 1 */
#define CAN_TSTS_TM2TCF_VAL ((uint32_t)0x00010000) /*!< tm2tcf bit value, it clear by writing 1 */
#define CAN_TSTS_TM0CT_VAL ((uint32_t)0x00000080) /*!< tm0ct bit value, it clear by writing 1 */
#define CAN_TSTS_TM1CT_VAL ((uint32_t)0x00008000) /*!< tm1ct bit value, it clear by writing 1 */
#define CAN_TSTS_TM2CT_VAL ((uint32_t)0x00800000) /*!< tm2ct bit value, it clear by writing 1 */
#define CAN_RF0_RF0FF_VAL ((uint32_t)0x00000008) /*!< rf0ff bit value, it clear by writing 1 */
#define CAN_RF0_RF0OF_VAL ((uint32_t)0x00000010) /*!< rf0of bit value, it clear by writing 1 */
#define CAN_RF0_RF0R_VAL ((uint32_t)0x00000020) /*!< rf0r bit value, it clear by writing 1 */
#define CAN_RF1_RF1FF_VAL ((uint32_t)0x00000008) /*!< rf1ff bit value, it clear by writing 1 */
#define CAN_RF1_RF1OF_VAL ((uint32_t)0x00000010) /*!< rf1of bit value, it clear by writing 1 */
#define CAN_RF1_RF1R_VAL ((uint32_t)0x00000020) /*!< rf1r bit value, it clear by writing 1 */
/** @defgroup CAN_exported_types
* @{

4
libraries/drivers/inc/at32f435_437_crc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_crc.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 crc header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_crm.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_crm.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 crm header file
**************************************************************************
* Copyright notice & Disclaimer

7
libraries/drivers/inc/at32f435_437_dac.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dac.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 dac header file
**************************************************************************
* Copyright notice & Disclaimer
@ -44,6 +44,9 @@ extern "C" {
* @{
*/
#define DAC1_D1DMAUDRF ((uint32_t)(0x00002000))
#define DAC2_D2DMAUDRF ((uint32_t)(0x20000000))
/** @defgroup DAC_exported_types
* @{
*/

6
libraries/drivers/inc/at32f435_437_debug.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_mcudbg.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 mcudbg header file
**************************************************************************
* Copyright notice & Disclaimer
@ -178,7 +178,7 @@ typedef struct
* @}
*/
#define DEBUG ((debug_type *) DEBUG_BASE)
#define DEBUGMCU ((debug_type *) DEBUG_BASE)
/** @defgroup DEBUG_exported_functions
* @{

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libraries/drivers/inc/at32f435_437_def.h Normal file
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@ -0,0 +1,69 @@
/**
**************************************************************************
* @file at32f435_437_def.h
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 macros header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_DEF_H
#define __AT32F435_437_DEF_H
#ifdef __cplusplus
extern "C" {
#endif
/* gnu compiler */
#if defined (__GNUC__)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL __attribute__ ((aligned (4)))
#endif
#endif
/* arm compiler */
#if defined (__CC_ARM)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD __align(4)
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL
#endif
#endif
/* iar compiler */
#if defined (__ICCARM__)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

4
libraries/drivers/inc/at32f435_437_dma.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dma.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 dma header file
**************************************************************************
* Copyright notice & Disclaimer

10
libraries/drivers/inc/at32f435_437_dvp.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dvp.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 dvp header file
**************************************************************************
* Copyright notice & Disclaimer
@ -372,11 +372,11 @@ typedef struct
};
/**
* @brief dvp icr register, offset:0x14
* @brief dvp iclr register, offset:0x14
*/
union
{
__IO uint32_t icr;
__IO uint32_t iclr;
struct
{
__IO uint32_t cfdic : 1; /* [0] */
@ -385,7 +385,7 @@ typedef struct
__IO uint32_t vsic : 1; /* [3] */
__IO uint32_t hsic : 1; /* [4] */
__IO uint32_t reserved1 : 27;/* [31:5] */
} icr_bit;
} iclr_bit;
};
/**

4
libraries/drivers/inc/at32f435_437_edma.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_edma.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 edma header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_emac.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_emac.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 eth header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_ertc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_ertc.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 ertc header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_exint.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_exint.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 exint header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_flash.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_flash.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 flash header file
**************************************************************************
* Copyright notice & Disclaimer

6
libraries/drivers/inc/at32f435_437_gpio.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_gpio.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 gpio header file
**************************************************************************
* Copyright notice & Disclaimer
@ -452,7 +452,7 @@ typedef struct
};
/**
* @brief gpio iocb register, offset:0x28
* @brief gpio clr register, offset:0x28
*/
union
{

4
libraries/drivers/inc/at32f435_437_i2c.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_i2c.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 i2c header file
**************************************************************************
* Copyright notice & Disclaimer

14
libraries/drivers/inc/at32f435_437_misc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_misc.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 misc header file
**************************************************************************
* Copyright notice & Disclaimer
@ -64,11 +64,11 @@ extern "C" {
*/
typedef enum
{
NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x700), /*!< 0 bits for preemption priority, 4 bits for subpriority */
NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x600), /*!< 1 bits for preemption priority, 3 bits for subpriority */
NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x500), /*!< 2 bits for preemption priority, 2 bits for subpriority */
NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x400), /*!< 3 bits for preemption priority, 1 bits for subpriority */
NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x300) /*!< 4 bits for preemption priority, 0 bits for subpriority */
NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
} nvic_priority_group_type;
/**

4
libraries/drivers/inc/at32f435_437_pwc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_pwc.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 pwr header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_qspi.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_qspi.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 qspi header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_scfg.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_scfg.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 system config header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_sdio.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_sdio.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 sdio header file
**************************************************************************
* Copyright notice & Disclaimer

8
libraries/drivers/inc/at32f435_437_spi.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_spi.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 spi header file
**************************************************************************
* Copyright notice & Disclaimer
@ -123,8 +123,8 @@ typedef enum
*/
typedef enum
{
SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is software mode */
SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is hardware mode */
SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is hardware mode */
SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is software mode */
} spi_cs_mode_type;
/**

4
libraries/drivers/inc/at32f435_437_tmr.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_tmr.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 tmr header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_usart.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_usart.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 usart header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_usb.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_usb.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 usb header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_wdt.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_wdt.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 wdt header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_wwdt.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_wwdt.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 wwdt header file
**************************************************************************
* Copyright notice & Disclaimer

272
libraries/drivers/inc/at32f435_437_xmc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_xmc.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 xmc header file
**************************************************************************
* Copyright notice & Disclaimer
@ -139,37 +139,26 @@ typedef enum
} xmc_ecc_enable_type;
/**
* @brief xmc nor/sram bank type
* @brief xmc nor/sram subbank type
*/
typedef enum
{
XMC_BANK1_NOR_SRAM1 = 0x00000000, /*!< xmc nor/sram bank1 */
XMC_BANK1_NOR_SRAM2 = 0x00000002, /*!< xmc nor/sram bank2 */
XMC_BANK1_NOR_SRAM3 = 0x00000004, /*!< xmc nor/sram bank3 */
XMC_BANK1_NOR_SRAM4 = 0x00000006 /*!< xmc nor/sram bank4 */
} xmc_nor_sram_bank_type;
XMC_BANK1_NOR_SRAM1 = 0x00000000, /*!< xmc nor/sram subbank1 */
XMC_BANK1_NOR_SRAM2 = 0x00000001, /*!< xmc nor/sram subbank2 */
XMC_BANK1_NOR_SRAM3 = 0x00000002, /*!< xmc nor/sram subbank3 */
XMC_BANK1_NOR_SRAM4 = 0x00000003 /*!< xmc nor/sram subbank4 */
} xmc_nor_sram_subbank_type;
/**
* @brief xmc subbank1 nor/sram type
* @brief xmc class bank type
*/
typedef enum
{
XMC_SUBBANK1_NOR_SRAM1 = 0x00000000, /*!< xmc nor/sram subbank1 */
XMC_SUBBANK1_NOR_SRAM2 = 0x00000001, /*!< xmc nor/sram subbank2 */
XMC_SUBBANK1_NOR_SRAM3 = 0x00000002, /*!< xmc nor/sram subbank3 */
XMC_SUBBANK1_NOR_SRAM4 = 0x00000003 /*!< xmc nor/sram subbank4 */
} xmc_subbank1_nor_sram_type;
/**
* @brief xmc nand bank type
*/
typedef enum
{
XMC_BANK2_NAND = 0x00000010, /*!< xmc nand flash bank2 */
XMC_BANK3_NAND = 0x00000100, /*!< xmc nand flash bank3 */
XMC_BANK4_PCCARD = 0x00001000, /*!< xmc pc card bank4 */
XMC_BANK5_6_SDRAM = 0x00010000 /*!< xmc sdram bank5/6 */
} xmc_nand_bank_type;
XMC_BANK2_NAND = 0x00000000, /*!< xmc nand flash bank2 */
XMC_BANK3_NAND = 0x00000001, /*!< xmc nand flash bank3 */
XMC_BANK4_PCCARD = 0x00000002, /*!< xmc pc card bank4 */
XMC_BANK5_6_SDRAM = 0x00000003 /*!< xmc sdram bank5/6 */
} xmc_class_bank_type;
/**
* @brief xmc memory type
@ -187,7 +176,7 @@ typedef enum
typedef enum
{
XMC_BUSTYPE_8_BITS = 0x00000000, /*!< xmc databuss width 8bits */
XMC_BUSTYPE_16_BITS = 0x00000010 /*!< xmc databuss width 16bits */
XMC_BUSTYPE_16_BITS = 0x00000010 /*!< xmc databuss width 16bits */
} xmc_data_width_type;
/**
@ -205,8 +194,8 @@ typedef enum
typedef enum
{
XMC_WAIT_SIGNAL_SYN_BEFORE = 0x00000000, /*!< xmc nwait signal is active one data cycle before wait state */
XMC_WAIT_SIGNAL_SYN_DURING = 0x00000800 /*!< xmc nwait signal is active during wait state */
} xmc_wait_timing_type;
XMC_WAIT_SIGNAL_SYN_DURING = 0x00000800 /*!< xmc nwait signal is active during wait state */
} xmc_wait_timing_type;
/**
* @brief xmc access mode type
@ -321,9 +310,9 @@ typedef enum
*/
typedef enum
{
XMC_READ_DELAY_0 = 0x00000000, /*!< xmc sdram no delay */
XMC_READ_DELAY_1 = 0x00000001, /*!< xmc sdram delay 1 clock*/
XMC_READ_DELAY_2 = 0x00000002, /*!< xmc sdram delay 2 clock */
XMC_READ_DELAY_0 = 0x00000000, /*!< xmc sdram no delay */
XMC_READ_DELAY_1 = 0x00000001, /*!< xmc sdram delay 1 clock*/
XMC_READ_DELAY_2 = 0x00000002, /*!< xmc sdram delay 2 clock */
}xmc_sdram_rd_delay_type;
/**
@ -402,7 +391,7 @@ typedef enum
*/
typedef struct
{
xmc_nor_sram_bank_type bank; /*!< xmc nor/sram bank */
xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram write timing enable */
uint32_t addr_setup_time; /*!< xmc nor/sram address setup time */
uint32_t addr_hold_time; /*!< xmc nor/sram address hold time */
@ -418,7 +407,7 @@ typedef struct
*/
typedef struct
{
xmc_nor_sram_bank_type bank; /*!< xmc nor/sram bank */
xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
xmc_data_addr_mux_type data_addr_multiplex; /*!< xmc nor/sram address/data multiplexing enable */
xmc_memory_type device; /*!< xmc nor/sram memory device */
xmc_data_width_type bus_type; /*!< xmc nor/sram data bus width */
@ -439,7 +428,7 @@ typedef struct
typedef struct
{
xmc_nand_bank_type nand_bank; /*!< xmc nand/pccard bank */
xmc_class_bank_type class_bank; /*!< xmc nand/pccard bank */
uint32_t mem_setup_time; /*!< xmc nand/pccard memory setup time */
uint32_t mem_waite_time; /*!< xmc nand/pccard memory wait time */
uint32_t mem_hold_time; /*!< xmc nand/pccard memory hold time */
@ -452,7 +441,7 @@ typedef struct
typedef struct
{
xmc_nand_bank_type nand_bank; /*!< xmc nand bank */
xmc_class_bank_type nand_bank; /*!< xmc nand bank */
xmc_nand_pccard_wait_type wait_enable; /*!< xmc wait feature enable */
xmc_data_width_type bus_type; /*!< xmc nand bus width */
xmc_ecc_enable_type ecc_enable; /*!< xmc nand ecc enable */
@ -478,7 +467,7 @@ typedef struct
typedef struct
{
xmc_sdram_bank_type bank; /*!< xmc sdram bank bype */
xmc_sdram_bank_type sdram_bank; /*!< xmc sdram bank bype */
xmc_sdram_inbk_type internel_banks; /*!< xmc sdram internal banks */
xmc_sdram_clkdiv_type clkdiv; /*!< xmc sdram clock div */
uint8_t write_protection; /*!< xmc sdram write protection */
@ -517,17 +506,14 @@ typedef struct
uint32_t data; /*!< mode register data */
} xmc_sdram_cmd_type;
/**
* @brief xmc controller
*/
typedef struct
{
/**
* @brief xmc bk1ctrl register, offset:0x00+0x08*(x-1) x= 1...4
* @brief xmc bank1 bk1ctrl register, offset:0x00+0x08*(x-1) x= 1...4
*/
union
{
__IO uint32_t bk1ctrl[8];
__IO uint32_t bk1ctrl;
struct
{
__IO uint32_t en : 1; /* [0] */
@ -547,21 +533,15 @@ typedef struct
__IO uint32_t crpgs : 3; /* [18:16] */
__IO uint32_t mwmc : 1; /* [19] */
__IO uint32_t reserved2 : 12;/* [31:20] */
} bk1ctrl_bit[8];
} bk1ctrl_bit;
};
} xmc_bank1_type;
/**
* @brief xmc bank1e
*/
typedef struct
{
/**
* @brief xmc bk1tmgwr register, offset:0x104+0x08*(x-1) x= 1...4
* @brief xmc bank1 bk1tmg register, offset:0x04+0x08*(x-1) x= 1...4
*/
union
{
__IO uint32_t bk1tmgwr[7];
__IO uint32_t bk1tmg;
struct
{
__IO uint32_t addrst : 4; /* [3:0] */
@ -572,37 +552,86 @@ typedef struct
__IO uint32_t dtlat : 4; /* [27:24] */
__IO uint32_t asyncm : 2; /* [29:28] */
__IO uint32_t reserved1 : 2; /* [31:30] */
} bk1tmgwr_bit[7];
} bk1tmg_bit;
};
} xmc_bank1_ext_type;
/**
* @brief xmc bank1h
*/
} xmc_bank1_ctrl_tmg_reg_type;
typedef struct
{
/**
* @brief xmc bk1ext register, offset:0x220+0x08*(x-1) x= 1...4
/**
* @brief xmc bank1 bk1tmgwr register, offset:0x104+0x08*(x-1) x= 1...4
*/
union
{
__IO uint32_t bk1ext[4];
__IO uint32_t bk1tmgwr;
struct
{
__IO uint32_t addrst : 4; /* [3:0] */
__IO uint32_t addrht : 4; /* [7:4] */
__IO uint32_t dtst : 8; /* [15:8] */
__IO uint32_t buslat : 4; /* [19:16] */
__IO uint32_t reserved1 : 8; /* [27:20] */
__IO uint32_t asyncm : 2; /* [29:28] */
__IO uint32_t reserved2 : 2; /* [31:30] */
} bk1tmgwr_bit;
};
/**
* @brief xmc bank1 reserved register
*/
__IO uint32_t reserved1;
} xmc_bank1_tmgwr_reg_type;
/**
* @brief xmc bank1 registers
*/
typedef struct
{
/**
* @brief xmc bank1 ctrl and tmg register, offset:0x00~0x1C
*/
xmc_bank1_ctrl_tmg_reg_type ctrl_tmg_group[4];
/**
* @brief xmc bank1 reserved register, offset:0x20~0x100
*/
__IO uint32_t reserved1[57];
/**
* @brief xmc bank1 tmgwr register, offset:0x104~0x11C
*/
xmc_bank1_tmgwr_reg_type tmgwr_group[4];
/**
* @brief xmc bank1 reserved register, offset:0x120~0x21C
*/
__IO uint32_t reserved2[64];
/**
* @brief xmc bank1 ext register, offset:0x220~0x22C
*/
union
{
__IO uint32_t ext[4];
struct
{
__IO uint32_t buslatw2w : 8; /* [7:0] */
__IO uint32_t buslatr2r : 8; /* [15:8] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} bk1ext_bit[4];
} ext_bit[4];
};
} xmc_bank1_hide_type;
} xmc_bank1_type;
/**
* @brief xmc bank2
* @brief xmc bank2 registers
*/
typedef struct
{
/**
* @brief xmc bk2ctrl register, offset:0x40+0x20*(x-1) x=2
* @brief xmc bk2ctrl register, offset:0x60
*/
union
{
@ -624,11 +653,11 @@ typedef struct
};
/**
* @brief xmc bk2sts register, offset:0x44+0x20*(x-1) x=2
* @brief xmc bk2is register, offset:0x64
*/
union
{
__IO uint32_t bk2sts;
__IO uint32_t bk2is;
struct
{
__IO uint32_t res : 1; /* [0] */
@ -639,11 +668,11 @@ typedef struct
__IO uint32_t feien : 1; /* [5] */
__IO uint32_t fifoe : 1; /* [6] */
__IO uint32_t reserved1 : 25;/* [31:7] */
} bk2sts_bit;
} bk2is_bit;
};
/**
* @brief xmc bk2tmgmem register, offset:0x48+0x20*(x-1) x=2
* @brief xmc bk2tmgmem register, offset:0x68
*/
union
{
@ -658,7 +687,7 @@ typedef struct
};
/**
* @brief xmc bk2tmgatt register, offset:0x4C+0x20*(x-1) x=2
* @brief xmc bk2tmgatt register, offset:0x6C
*/
union
{
@ -673,12 +702,12 @@ typedef struct
};
/**
* @brief xmc reserved register
* @brief xmc reserved register, offset:0x70
*/
uint32_t reserved;
__IO uint32_t reserved1;
/**
* @brief xmc bk2ecc register, offset:0x54+0x20*(x-1) x=2
* @brief xmc bk2ecc register, offset:0x74
*/
union
{
@ -692,12 +721,12 @@ typedef struct
} xmc_bank2_type;
/**
* @brief xmc bank3
* @brief xmc bank3 registers
*/
typedef struct
{
/**
* @brief xmc bk3ctrl register, offset:0x40+0x20*(x-1) x=3
* @brief xmc bk3ctrl register, offset:0x80
*/
union
{
@ -719,11 +748,11 @@ typedef struct
};
/**
* @brief xmc bk3sts register, offset:0x44+0x20*(x-1) x=3
* @brief xmc bk3is register, offset:0x84
*/
union
{
__IO uint32_t bk3sts;
__IO uint32_t bk3is;
struct
{
__IO uint32_t res : 1; /* [0] */
@ -734,11 +763,11 @@ typedef struct
__IO uint32_t feien : 1; /* [5] */
__IO uint32_t fifoe : 1; /* [6] */
__IO uint32_t reserved1 : 25;/* [31:7] */
} bk3sts_bit;
} bk3is_bit;
};
/**
* @brief xmc bk3tmgmem register, offset:0x48+0x20*(x-1) x=3
* @brief xmc bk3tmgmem register, offset:0x88
*/
union
{
@ -753,7 +782,7 @@ typedef struct
};
/**
* @brief xmc bk3tmgatt register, offset:0x4C+0x20*(x-1) x=3
* @brief xmc bk3tmgatt register, offset:0x8C
*/
union
{
@ -768,12 +797,12 @@ typedef struct
};
/**
* @brief xmc reserved register
* @brief xmc reserved register, offset:0x90
*/
uint32_t reserved;
__IO uint32_t reserved1;
/**
* @brief xmc bk3ecc register, offset:0x54+0x20*(x-1) x=3
* @brief xmc bk3ecc register, offset:0x94
*/
union
{
@ -786,13 +815,13 @@ typedef struct
} xmc_bank3_type;
/**
* @brief xmc bank4
* @brief xmc bank4 registers
*/
typedef struct
{
/**
* @brief xmc bk4ctrl register, offset:0x40+0x20*(x-1) x=4
* @brief xmc bk4ctrl register, offset:0xA0
*/
union
{
@ -814,11 +843,11 @@ typedef struct
};
/**
* @brief xmc bk4sts register, offset:0x44+0x20*(x-1) x=4
* @brief xmc bk4is register, offset:0xA4
*/
union
{
__IO uint32_t bk4sts;
__IO uint32_t bk4is;
struct
{
__IO uint32_t res : 1; /* [0] */
@ -829,11 +858,11 @@ typedef struct
__IO uint32_t feien : 1; /* [5] */
__IO uint32_t fifoe : 1; /* [6] */
__IO uint32_t reserved1 : 25;/* [31:7] */
} bk4sts_bit;
} bk4is_bit;
};
/**
* @brief xmc bk4tmgmem register, offset:0x48+0x20*(x-1) x=4
* @brief xmc bk4tmgmem register, offset:0xA8
*/
union
{
@ -848,7 +877,7 @@ typedef struct
};
/**
* @brief xmc bk4tmgatt register, offset:0x4C+0x20*(x-1) x=4
* @brief xmc bk4tmgatt register, offset:0xAC
*/
union
{
@ -879,16 +908,16 @@ typedef struct
} xmc_bank4_type;
/**
* @brief xmc sdram bank5-6 type
* @brief xmc sdram type
*/
typedef struct
{
/**
* @brief xmc sdctrl register, offset:0x140+4*(x-1) x=1,2
* @brief xmc sdram ctrl register, offset:0x140~0x144
*/
union
{
__IO uint32_t sdctrl[2];
__IO uint32_t ctrl[2];
struct
{
__IO uint32_t ca : 2; /* [1:0] */
@ -901,15 +930,15 @@ typedef struct
__IO uint32_t bstr : 1; /* [12] */
__IO uint32_t rd : 2; /* [14:13] */
__IO uint32_t reserved1 : 17;/* [31:15] */
} sdctrl_bit[2];
} ctrl_bit[2];
};
/**
* @brief xmc sdtm register, offset:0x148+4*(x-1) x=1,2
* @brief xmc sdram tm register, offset:0x148~0x14C
*/
union
{
__IO uint32_t sdtm[2];
__IO uint32_t tm[2];
struct
{
__IO uint32_t tmrd : 4; /* [3:0] */
@ -920,97 +949,95 @@ typedef struct
__IO uint32_t trp : 4; /* [23:20] */
__IO uint32_t trcd : 4; /* [27:24] */
__IO uint32_t reserved1 : 4; /* [31:28] */
} sdtm_bit[2];
} tm_bit[2];
};
/**
* @brief xmc sdcmd register, offset:0x150
* @brief xmc sdram cmd register, offset:0x150
*/
union
{
__IO uint32_t sdcmd;
__IO uint32_t cmd;
struct
{
__IO uint32_t cmd : 3; /* [2:0] */
__IO uint32_t bk2 : 1; /* [3] */
__IO uint32_t bk1 : 1; /* [4] */
__IO uint32_t art : 4; /* [8:5] */
__IO uint32_t mrd : 13; /* [21:9] */
__IO uint32_t reserved1 : 10; /* [31:22] */
} sdcmd_bit;
__IO uint32_t mrd : 13;/* [21:9] */
__IO uint32_t reserved1 : 10;/* [31:22] */
} cmd_bit;
};
/**
* @brief xmc sdrcnt register, offset:0x154
* @brief xmc sdram rcnt register, offset:0x154
*/
union
{
__IO uint32_t sdrcnt;
__IO uint32_t rcnt;
struct
{
__IO uint32_t errc : 1; /* [0] */
__IO uint32_t rc : 13; /* [13:1] */
__IO uint32_t rc : 13;/* [13:1] */
__IO uint32_t erien : 1; /* [14] */
__IO uint32_t reserved1 : 17; /* [31:15] */
} sdrcnt_bit;
__IO uint32_t reserved1 : 17;/* [31:15] */
} rcnt_bit;
};
/**
* @brief xmc sdsts register, offset:0x158
* @brief xmc sdram sts register, offset:0x158
*/
union
{
__IO uint32_t sdsts;
__IO uint32_t sts;
struct
{
__IO uint32_t err : 1; /* [0] */
__IO uint32_t bk1sts : 2; /* [2:1] */
__IO uint32_t bk2sts : 2; /* [4:3] */
__IO uint32_t busy : 1; /* [5] */
__IO uint32_t reserved1 : 26; /* [31:6] */
} sdsts_bit;
__IO uint32_t reserved1 : 26;/* [31:6] */
} sts_bit;
};
}xmc_bank5_6_type;
}xmc_sdram_type;
/**
* @}
*/
#define XMC_BANK1 ((xmc_bank1_type *) XMC_BANK1_REG_BASE)
#define XMC_BANK1E ((xmc_bank1_ext_type *) XMC_BANK1E_REG_BASE)
#define XMC_BANK1H ((xmc_bank1_hide_type *) XMC_BANK1E_H_BASE)
#define XMC_BANK2 ((xmc_bank2_type *) XMC_BANK2_REG_BASE)
#define XMC_BANK3 ((xmc_bank3_type *) XMC_BANK3_REG_BASE)
#define XMC_BANK4 ((xmc_bank4_type *) XMC_BANK4_REG_BASE)
#define XMC_BANK5_6 ((xmc_bank5_6_type *) XMC_BANK5_6_REG_BASE)
#define XMC_SDRAM ((xmc_sdram_type *) XMC_SDRAM_REG_BASE)
/** @defgroup XMC_exported_functions
* @{
*/
void xmc_nor_sram_reset(xmc_nor_sram_bank_type xmc_bank);
void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank);
void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct);
void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
xmc_norsram_timing_init_type* xmc_w_timing_struct);
void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct);
void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
xmc_norsram_timing_init_type* xmc_w_timing_struct);
void xmc_nor_sram_enable(xmc_nor_sram_bank_type xmc_bank, confirm_state new_state);
void xmc_ext_timing_config(xmc_subbank1_nor_sram_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
void xmc_nand_reset(xmc_nand_bank_type xmc_bank);
void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state);
void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
void xmc_nand_reset(xmc_class_bank_type xmc_bank);
void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct);
void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct);
void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct);
void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct);
void xmc_nand_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state);
void xmc_nand_ecc_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state);
uint32_t xmc_ecc_get(xmc_nand_bank_type xmc_bank);
void xmc_interrupt_enable(xmc_nand_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state);
flag_status xmc_flag_status_get(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
void xmc_flag_clear(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank);
void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state);
flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
void xmc_pccard_reset(void);
void xmc_pccard_init(xmc_pccard_init_type* xmc_pccard_init_struct);
void xmc_pccard_timing_config(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
@ -1021,7 +1048,6 @@ void xmc_pccard_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_co
xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct);
void xmc_pccard_enable(confirm_state new_state);
void xmc_sdram_reset(xmc_sdram_bank_type xmc_bank);
void xmc_sdram_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct);
void xmc_sdram_default_para_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct);

4
libraries/drivers/src/at32f435_437_acc.c
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_acc.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the acc firmware library
**************************************************************************
* Copyright notice & Disclaimer

6
libraries/drivers/src/at32f435_437_adc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_adc.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the adc firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -1105,7 +1105,7 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag)
*/
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag)
{
adc_x->sts &= ~adc_flag;
adc_x->sts = ~adc_flag;
}
/**

14
libraries/drivers/src/at32f435_437_can.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_can.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the can firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -591,13 +591,13 @@ void can_transmit_cancel(can_type* can_x, can_tx_mailbox_num_type transmit_mailb
switch (transmit_mailbox)
{
case CAN_TX_MAILBOX0:
can_x->tsts_bit.tm0ct = TRUE;
can_x->tsts = CAN_TSTS_TM0CT_VAL;
break;
case CAN_TX_MAILBOX1:
can_x->tsts_bit.tm1ct = TRUE;
can_x->tsts = CAN_TSTS_TM1CT_VAL;
break;
case CAN_TX_MAILBOX2:
can_x->tsts_bit.tm2ct = TRUE;
can_x->tsts = CAN_TSTS_TM2CT_VAL;
break;
default:
break;
@ -668,10 +668,10 @@ void can_receive_fifo_release(can_type* can_x, can_rx_fifo_num_type fifo_number)
switch (fifo_number)
{
case CAN_RX_FIFO0:
can_x->rf0_bit.rf0r = TRUE;
can_x->rf0 = CAN_RF0_RF0R_VAL;
break;
case CAN_RX_FIFO1:
can_x->rf1_bit.rf1r = TRUE;
can_x->rf1 = CAN_RF1_RF1R_VAL;
break;
default:
break;

4
libraries/drivers/src/at32f435_437_crc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_crc.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the crc firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_crm.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_crm.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the crm firmware library
**************************************************************************
* Copyright notice & Disclaimer

8
libraries/drivers/src/at32f435_437_dac.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dac.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the dac firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -429,10 +429,10 @@ void dac_udr_flag_clear(dac_select_type dac_select)
switch(dac_select)
{
case DAC1_SELECT:
DAC->sts = (uint32_t)(0x1 << 13);
DAC->sts = DAC1_D1DMAUDRF;
break;
case DAC2_SELECT:
DAC->sts = (uint32_t)(0x1 << 29);
DAC->sts = DAC2_D2DMAUDRF;
break;
default:
break;

18
libraries/drivers/src/at32f435_437_debug.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_mcudbg.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the mcudbg firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -48,7 +48,7 @@
*/
uint32_t debug_device_id_get(void)
{
return DEBUG->pid;
return DEBUGMCU->pid;
}
/**
* @brief set periph debug mode
@ -64,11 +64,11 @@ void debug_low_power_mode_set(uint32_t low_power_mode, confirm_state new_state)
{
if(new_state != FALSE)
{
DEBUG->ctrl |= low_power_mode;
DEBUGMCU->ctrl |= low_power_mode;
}
else
{
DEBUG->ctrl &= ~low_power_mode;
DEBUGMCU->ctrl &= ~low_power_mode;
}
}
/**
@ -91,11 +91,11 @@ void debug_apb1_periph_mode_set(uint32_t apb1_periph, confirm_state new_state)
{
if(new_state != FALSE)
{
DEBUG->apb1_frz |= apb1_periph;
DEBUGMCU->apb1_frz |= apb1_periph;
}
else
{
DEBUG->apb1_frz &= ~apb1_periph;
DEBUGMCU->apb1_frz &= ~apb1_periph;
}
}
/**
@ -112,11 +112,11 @@ void debug_apb2_periph_mode_set(uint32_t apb2_periph, confirm_state new_state)
{
if(new_state != FALSE)
{
DEBUG->apb2_frz |= apb2_periph;
DEBUGMCU->apb2_frz |= apb2_periph;
}
else
{
DEBUG->apb2_frz &= ~apb2_periph;
DEBUGMCU->apb2_frz &= ~apb2_periph;
}
}

10
libraries/drivers/src/at32f435_437_dma.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dma.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the dma firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -263,13 +263,13 @@ flag_status dma_flag_get(uint32_t dmax_flag)
*/
void dma_flag_clear(uint32_t dmax_flag)
{
if(dmax_flag > 0x10000000)
if(dmax_flag > ((uint32_t)0x10000000))
{
DMA2->clr = dmax_flag;
DMA2->clr = (uint32_t)(dmax_flag & 0x0FFFFFFF);
}
else
{
DMA1->clr = dmax_flag;
DMA1->clr = dmax_flag;
}
}

6
libraries/drivers/src/at32f435_437_dvp.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dvp.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the dvp firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -375,7 +375,7 @@ flag_status dvp_flag_get(uint32_t flag)
void dvp_flag_clear(uint32_t flag)
{
flag &= ~0x80000000;
DVP->icr = flag;
DVP->iclr = flag;
}
/**

6
libraries/drivers/src/at32f435_437_edma.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_edma.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the edma firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -550,7 +550,7 @@ void edma_flag_clear(uint32_t edma_flag)
{
if(edma_flag > ((uint32_t)0x20000000))
{
EDMA->clr2 = edma_flag;
EDMA->clr2 = (uint32_t)(edma_flag & 0x0FFFFFFF);
}
else
{

4
libraries/drivers/src/at32f435_437_emac.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_emac.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the emac firmware library
**************************************************************************
* Copyright notice & Disclaimer

14
libraries/drivers/src/at32f435_437_ertc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_ertc.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the ertc firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -102,7 +102,7 @@ error_status ertc_wait_update(void)
ertc_write_protect_disable();
/* clear updf flag */
ERTC->sts_bit.updf = 0;
ERTC->sts = ~(ERTC_UPDF_FLAG | 0x00000080) | (ERTC->sts_bit.imen << 7);
/* enable write protection */
ertc_write_protect_enable();
@ -170,7 +170,7 @@ error_status ertc_init_mode_enter(void)
if(ERTC->sts_bit.imf == 0)
{
/* enter init mode */
ERTC->sts_bit.imen = 1;
ERTC->sts = 0xFFFFFFFF;
while(ERTC->sts_bit.imf == 0)
{
@ -196,7 +196,7 @@ error_status ertc_init_mode_enter(void)
*/
void ertc_init_mode_exit(void)
{
ERTC->sts_bit.imen = FALSE;
ERTC->sts = 0xFFFFFF7F;
}
/**
@ -1374,7 +1374,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat
/**
* @brief enable or disable interrupt.
* @param source: interrupts sources
* this parameter can be one of the following values:
* this parameter can be any combination of the following values:
* - ERTC_TP_INT: tamper interrupt.
* - ERTC_ALA_INT: alarm a interrupt.
* - ERTC_ALB_INT: alarm b interrupt.
@ -1509,7 +1509,7 @@ void ertc_flag_clear(uint32_t flag)
/* disable write protection */
ertc_write_protect_disable();
ERTC->sts &= ~flag;
ERTC->sts = ~(flag | 0x00000080) | (ERTC->sts_bit.imen << 7);
/* enable write protection */
ertc_write_protect_enable();

4
libraries/drivers/src/at32f435_437_exint.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_exint.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the exint firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_flash.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_flash.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the flash firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_gpio.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_gpio.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the gpio firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_i2c.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_i2c.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the i2c firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_misc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_misc.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the misc firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_pwc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_pwc.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the pwc firmware library
**************************************************************************
* Copyright notice & Disclaimer

9
libraries/drivers/src/at32f435_437_qspi.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_qspi.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contain all the functions for qspi firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -167,10 +167,7 @@ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag)
*/
void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag)
{
if(flag == QSPI_CMDSTS_FLAG)
{
qspi_x->cmdsts_bit.cmdsts = TRUE;
}
qspi_x->cmdsts = QSPI_CMDSTS_FLAG;
}
/**

4
libraries/drivers/src/at32f435_437_scfg.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_scfg.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the system config firmware library
**************************************************************************
* Copyright notice & Disclaimer

6
libraries/drivers/src/at32f435_437_sdio.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_sdio.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the sdio firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -325,7 +325,7 @@ flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag)
*/
void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag)
{
sdio_x->intclr |= flag;
sdio_x->intclr = flag;
}
/**

8
libraries/drivers/src/at32f435_437_spi.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_spi.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the spi firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -616,9 +616,9 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag)
{
volatile uint32_t temp = 0;
temp = temp;
if(spi_i2s_flag == SPI_CCERR_FLAG)
spi_x->sts_bit.ccerr = FALSE;
spi_x->sts = ~SPI_CCERR_FLAG;
else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG)
temp = REG32(&spi_x->dt);
else if(spi_i2s_flag == I2S_TUERR_FLAG)

6
libraries/drivers/src/at32f435_437_tmr.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_tmr.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the tmr firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -1460,7 +1460,7 @@ flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag)
*/
void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag)
{
tmr_x->ists &= ~tmr_flag;
tmr_x->ists = ~tmr_flag;
}
/**

4
libraries/drivers/src/at32f435_437_usart.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_usart.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the usart firmware library
**************************************************************************
* Copyright notice & Disclaimer

18
libraries/drivers/src/at32f435_437_usb.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_usb.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the usb firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -314,8 +314,7 @@ void usb_set_tx_fifo(otg_global_type *usbx, uint8_t txfifo, uint16_t size)
offset = usbx->grxfsiz;
if(txfifo == 0)
{
usbx->gnptxfsiz_ept0tx_bit.nptxfstaddr = offset;
usbx->gnptxfsiz_ept0tx_bit.nptxfdep = size;
usbx->gnptxfsiz_ept0tx = offset | (size << 16);
}
else
{
@ -324,8 +323,7 @@ void usb_set_tx_fifo(otg_global_type *usbx, uint8_t txfifo, uint16_t size)
{
offset += usbx->dieptxfn_bit[i_index].ineptxfdep;
}
usbx->dieptxfn_bit[txfifo-1].ineptxfstaddr = offset;
usbx->dieptxfn_bit[txfifo-1].ineptxfdep = size;
usbx->dieptxfn[txfifo - 1] = offset | (size << 16);
}
}
@ -428,7 +426,11 @@ void usb_write_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, ui
uint32_t *pbuf = (uint32_t *)pusr_buf;
for(n_index = 0; n_index < nhbytes; n_index ++)
{
#if defined (__ICCARM__) && (__VER__ < 7000000)
USB_FIFO(usbx, num) = *(__packed uint32_t *)pbuf;
#else
USB_FIFO(usbx, num) = __UNALIGNED_UINT32_READ(pbuf);
#endif
pbuf ++;
}
}
@ -447,7 +449,11 @@ void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uin
uint32_t *pbuf = (uint32_t *)pusr_buf;
for(n_index = 0; n_index < nhbytes; n_index ++)
{
#if defined (__ICCARM__) && (__VER__ < 7000000)
*(__packed uint32_t *)pbuf = USB_FIFO(usbx, 0);
#else
__UNALIGNED_UINT32_WRITE(pbuf, (USB_FIFO(usbx, 0)));
#endif
pbuf ++;
}
}

4
libraries/drivers/src/at32f435_437_wdt.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_wdt.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the wdt firmware library
**************************************************************************
* Copyright notice & Disclaimer

6
libraries/drivers/src/at32f435_437_wwdt.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_wwdt.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the wwdt firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -73,7 +73,7 @@ void wwdt_divider_set(wwdt_division_type division)
*/
void wwdt_flag_clear(void)
{
WWDT->sts_bit.rldf = FALSE;
WWDT->sts = 0;
}
/**

223
libraries/drivers/src/at32f435_437_xmc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_xmc.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for the xmc firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -43,7 +43,7 @@
/**
* @brief xmc nor or sram registers reset
* @param xmc_bank
* @param xmc_subbank
* this parameter can be one of the following values:
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM2
@ -51,20 +51,20 @@
* - XMC_BANK1_NOR_SRAM4
* @retval none
*/
void xmc_nor_sram_reset(xmc_nor_sram_bank_type xmc_bank)
void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank)
{
/* XMC_BANK1_NORSRAM1 */
if(xmc_bank == XMC_BANK1_NOR_SRAM1)
if(xmc_subbank == XMC_BANK1_NOR_SRAM1)
{
XMC_BANK1->bk1ctrl[xmc_bank] = 0x000030DB;
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030DB;
}
/* XMC_BANK1_NORSRAM2, XMC_BANK1_NORSRAM3 or XMC_BANK1_NORSRAM4 */
else
{
XMC_BANK1->bk1ctrl[xmc_bank] = 0x000030D2;
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030D2;
}
XMC_BANK1->bk1ctrl[xmc_bank + 1] = 0x0FFFFFFF;
XMC_BANK1E->bk1tmgwr[xmc_bank] = 0x0FFFFFFF;
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1tmg = 0x0FFFFFFF;
XMC_BANK1->tmgwr_group[xmc_subbank].bk1tmgwr = 0x0FFFFFFF;
}
/**
@ -78,7 +78,7 @@ void xmc_nor_sram_reset(xmc_nor_sram_bank_type xmc_bank)
void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct)
{
/* bank1 nor/sram control register configuration */
XMC_BANK1->bk1ctrl[xmc_norsram_init_struct->bank] =
XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl =
(uint32_t)xmc_norsram_init_struct->data_addr_multiplex |
xmc_norsram_init_struct->device |
xmc_norsram_init_struct->bus_type |
@ -95,7 +95,7 @@ void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct)
/* if nor flash device */
if(xmc_norsram_init_struct->device == XMC_DEVICE_NOR)
{
XMC_BANK1->bk1ctrl_bit[xmc_norsram_init_struct->bank].noren = 0x1;
XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl_bit.noren = 0x1;
}
}
@ -114,7 +114,7 @@ void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_stru
xmc_norsram_timing_init_type* xmc_w_timing_struct)
{
/* bank1 nor/sram timing register configuration */
XMC_BANK1->bk1ctrl[xmc_rw_timing_struct->bank + 1] =
XMC_BANK1->ctrl_tmg_group[xmc_rw_timing_struct->subbank].bk1tmg =
(uint32_t)xmc_rw_timing_struct->addr_setup_time |
(xmc_rw_timing_struct->addr_hold_time << 4) |
(xmc_rw_timing_struct->data_setup_time << 8) |
@ -126,7 +126,7 @@ void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_stru
/* bank1 nor/sram timing register for write configuration, if extended mode is used */
if(xmc_rw_timing_struct->write_timing_enable == XMC_WRITE_TIMING_ENABLE)
{
XMC_BANK1E->bk1tmgwr[xmc_w_timing_struct->bank] =
XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr =
(uint32_t)xmc_w_timing_struct->addr_setup_time |
(xmc_w_timing_struct->addr_hold_time << 4) |
(xmc_w_timing_struct->data_setup_time << 8) |
@ -137,7 +137,7 @@ void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_stru
}
else
{
XMC_BANK1E->bk1tmgwr[xmc_w_timing_struct->bank] = 0x0FFFFFFF;
XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr = 0x0FFFFFFF;
}
}
@ -150,7 +150,7 @@ void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_stru
void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct)
{
/* reset nor/sram init structure parameters values */
xmc_nor_sram_init_struct->bank = XMC_BANK1_NOR_SRAM1;
xmc_nor_sram_init_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_nor_sram_init_struct->data_addr_multiplex = XMC_DATA_ADDR_MUX_ENABLE;
xmc_nor_sram_init_struct->device = XMC_DEVICE_SRAM;
xmc_nor_sram_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
@ -176,7 +176,7 @@ void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_stru
void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
xmc_norsram_timing_init_type* xmc_w_timing_struct)
{
xmc_rw_timing_struct->bank = XMC_BANK1_NOR_SRAM1;
xmc_rw_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_rw_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
xmc_rw_timing_struct->addr_setup_time = 0xF;
xmc_rw_timing_struct->addr_hold_time = 0xF;
@ -185,7 +185,7 @@ void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_t
xmc_rw_timing_struct->clk_psc = 0xF;
xmc_rw_timing_struct->data_latency_time = 0xF;
xmc_rw_timing_struct->mode = XMC_ACCESS_MODE_A;
xmc_w_timing_struct->bank = XMC_BANK1_NOR_SRAM1;
xmc_w_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_w_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
xmc_w_timing_struct->addr_setup_time = 0xF;
xmc_w_timing_struct->addr_hold_time = 0xF;
@ -198,7 +198,7 @@ void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_t
/**
* @brief enable or disable the specified nor/sram memory bank.
* @param xmc_bank
* @param xmc_subbank
* this parameter can be one of the following values:
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM2
@ -207,27 +207,27 @@ void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_t
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nor_sram_enable(xmc_nor_sram_bank_type xmc_bank, confirm_state new_state)
void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state)
{
XMC_BANK1->bk1ctrl_bit[xmc_bank].en = new_state;
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl_bit.en = new_state;
}
/**
* @brief config the bus turnaround phase.
* @param xmc_sub_bank
* this parameter can be one of the following values:
* - XMC_SUBBANK1_NOR_SRAM1
* - XMC_SUBBANK1_NOR_SRAM2
* - XMC_SUBBANK1_NOR_SRAM3
* - XMC_SUBBANK1_NOR_SRAM4
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM2
* - XMC_BANK1_NOR_SRAM3
* - XMC_BANK1_NOR_SRAM4
* @param w2w_timing :write timing
* @param r2r_timing :read timing
* @retval none
*/
void xmc_ext_timing_config(xmc_subbank1_nor_sram_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
{
XMC_BANK1H->bk1ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8;
XMC_BANK1H->bk1ext_bit[xmc_sub_bank].buslatw2w = w2w_timing;
XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8;
XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing;
}
/**
@ -238,21 +238,21 @@ void xmc_ext_timing_config(xmc_subbank1_nor_sram_type xmc_sub_bank, uint16_t w2w
* - XMC_BANK3_NAND
* @retval none
*/
void xmc_nand_reset(xmc_nand_bank_type xmc_bank)
void xmc_nand_reset(xmc_class_bank_type xmc_bank)
{
/* set the XMC_BANK2_NAND registers to their reset values */
/* set the xmc_bank2_nand registers to their reset values */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl = 0x00000018;
XMC_BANK2->bk2sts = 0x00000040;
XMC_BANK2->bk2is = 0x00000040;
XMC_BANK2->bk2tmgatt = 0xFCFCFCFC;
XMC_BANK2->bk2tmgmem = 0xFCFCFCFC;
}
/* set the XMC_BANK3_NAND registers to their reset values */
/* set the xmc_bank3_nand registers to their reset values */
else
{
XMC_BANK3->bk3ctrl = 0x00000018;
XMC_BANK3->bk3sts = 0x00000040;
XMC_BANK3->bk3is = 0x00000040;
XMC_BANK3->bk3tmgatt = 0xFCFCFCFC;
XMC_BANK3->bk3tmgmem = 0xFCFCFCFC;
}
@ -319,7 +319,7 @@ void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spaceti
(xmc_special_spacetiming_struct->mem_hold_time << 16) |
(xmc_special_spacetiming_struct->mem_hiz_time << 24);
/* xmc_bank2_nand registers configuration */
if(xmc_regular_spacetiming_struct->nand_bank == XMC_BANK2_NAND)
if(xmc_regular_spacetiming_struct->class_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2tmgatt = tempatt;
XMC_BANK2->bk2tmgmem = tempmem;
@ -360,12 +360,12 @@ void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct)
void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct)
{
xmc_regular_spacetiming_struct->nand_bank = XMC_BANK2_NAND;
xmc_regular_spacetiming_struct->class_bank = XMC_BANK2_NAND;
xmc_regular_spacetiming_struct->mem_hold_time = 0xFC;
xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
xmc_special_spacetiming_struct->nand_bank = XMC_BANK2_NAND;
xmc_special_spacetiming_struct->class_bank = XMC_BANK2_NAND;
xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
@ -381,7 +381,7 @@ void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regu
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nand_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state)
void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
{
/* enable or disable the nand bank2 by setting the en bit in the bk2ctrl register */
if(xmc_bank == XMC_BANK2_NAND)
@ -404,7 +404,7 @@ void xmc_nand_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state)
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nand_ecc_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state)
void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
{
/* enable the selected nand bank2 ecc function by setting the eccen bit in the bk2ctrl register */
if(xmc_bank == XMC_BANK2_NAND)
@ -426,7 +426,7 @@ void xmc_nand_ecc_enable(xmc_nand_bank_type xmc_bank, confirm_state new_state)
* - XMC_BANK3_NAND
* @retval the error correction code (ecc) value.
*/
uint32_t xmc_ecc_get(xmc_nand_bank_type xmc_bank)
uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank)
{
uint32_t eccvaule = 0x0;
@ -454,11 +454,11 @@ uint32_t xmc_ecc_get(xmc_nand_bank_type xmc_bank)
*/
void xmc_sdram_reset(xmc_sdram_bank_type xmc_bank)
{
XMC_BANK5_6->sdctrl[xmc_bank] = 0x000002D0;
XMC_BANK5_6->sdtm[xmc_bank] = 0x0FFFFFFF;
XMC_BANK5_6->sdcmd = 0x00000000;
XMC_BANK5_6->sdrcnt = 0x00000000;
XMC_BANK5_6->sdsts = 0x00000000;
XMC_SDRAM->ctrl[xmc_bank] = 0x000002D0;
XMC_SDRAM->tm[xmc_bank] = 0x0FFFFFFF;
XMC_SDRAM->cmd = 0x00000000;
XMC_SDRAM->rcnt = 0x00000000;
XMC_SDRAM->sts = 0x00000000;
}
/**
@ -474,50 +474,50 @@ void xmc_sdram_reset(xmc_sdram_bank_type xmc_bank)
*/
void xmc_sdram_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct)
{
if(xmc_sdram_init_struct->bank == XMC_SDRAM_BANK1)
if(xmc_sdram_init_struct->sdram_bank == XMC_SDRAM_BANK1)
{
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK1].ca = xmc_sdram_init_struct->column_address;
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK1].ra = xmc_sdram_init_struct->row_address;
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK1].db = xmc_sdram_init_struct->width;
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK1].inbk = xmc_sdram_init_struct->internel_banks;
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK1].cas = xmc_sdram_init_struct->cas;
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK1].wrp = xmc_sdram_init_struct->write_protection;
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK1].bstr = xmc_sdram_init_struct->burst_read;
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK1].rd = xmc_sdram_init_struct->read_delay;
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK1].clkdiv = xmc_sdram_init_struct->clkdiv;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].ca = xmc_sdram_init_struct->column_address;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].ra = xmc_sdram_init_struct->row_address;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].db = xmc_sdram_init_struct->width;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].inbk = xmc_sdram_init_struct->internel_banks;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].cas = xmc_sdram_init_struct->cas;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].wrp = xmc_sdram_init_struct->write_protection;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].bstr = xmc_sdram_init_struct->burst_read;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].rd = xmc_sdram_init_struct->read_delay;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].clkdiv = xmc_sdram_init_struct->clkdiv;
XMC_BANK5_6->sdtm_bit[XMC_SDRAM_BANK1].tmrd = xmc_sdram_timing_struct->tmrd;
XMC_BANK5_6->sdtm_bit[XMC_SDRAM_BANK1].txsr = xmc_sdram_timing_struct->txsr;
XMC_BANK5_6->sdtm_bit[XMC_SDRAM_BANK1].tras = xmc_sdram_timing_struct->tras;
XMC_BANK5_6->sdtm_bit[XMC_SDRAM_BANK1].trc = xmc_sdram_timing_struct->trc;
XMC_BANK5_6->sdtm_bit[XMC_SDRAM_BANK1].twr = xmc_sdram_timing_struct->twr;
XMC_BANK5_6->sdtm_bit[XMC_SDRAM_BANK1].trp = xmc_sdram_timing_struct->trp;
XMC_BANK5_6->sdtm_bit[XMC_SDRAM_BANK1].trcd = xmc_sdram_timing_struct->trcd;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].tmrd = xmc_sdram_timing_struct->tmrd;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].txsr = xmc_sdram_timing_struct->txsr;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].tras = xmc_sdram_timing_struct->tras;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trc = xmc_sdram_timing_struct->trc;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].twr = xmc_sdram_timing_struct->twr;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trp = xmc_sdram_timing_struct->trp;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trcd = xmc_sdram_timing_struct->trcd;
}
if(xmc_sdram_init_struct->bank == XMC_SDRAM_BANK2)
if(xmc_sdram_init_struct->sdram_bank == XMC_SDRAM_BANK2)
{
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK2].ca = xmc_sdram_init_struct->column_address;
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK2].ra = xmc_sdram_init_struct->row_address;
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK2].db = xmc_sdram_init_struct->width;
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK2].inbk = xmc_sdram_init_struct->internel_banks;
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK2].cas = xmc_sdram_init_struct->cas;
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK2].wrp = xmc_sdram_init_struct->write_protection;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].ca = xmc_sdram_init_struct->column_address;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].ra = xmc_sdram_init_struct->row_address;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].db = xmc_sdram_init_struct->width;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].inbk = xmc_sdram_init_struct->internel_banks;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].cas = xmc_sdram_init_struct->cas;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].wrp = xmc_sdram_init_struct->write_protection;
/* sdctrl2 bstr is not care */
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK1].bstr = xmc_sdram_init_struct->burst_read;
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK2].rd = xmc_sdram_init_struct->read_delay;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].bstr = xmc_sdram_init_struct->burst_read;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].rd = xmc_sdram_init_struct->read_delay;
/* sdctrl2 clkdiv is not care */
XMC_BANK5_6->sdctrl_bit[XMC_SDRAM_BANK1].clkdiv = xmc_sdram_init_struct->clkdiv;
XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].clkdiv = xmc_sdram_init_struct->clkdiv;
XMC_BANK5_6->sdtm_bit[XMC_SDRAM_BANK2].tmrd = xmc_sdram_timing_struct->tmrd;
XMC_BANK5_6->sdtm_bit[XMC_SDRAM_BANK2].txsr = xmc_sdram_timing_struct->txsr;
XMC_BANK5_6->sdtm_bit[XMC_SDRAM_BANK2].tras = xmc_sdram_timing_struct->tras;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].tmrd = xmc_sdram_timing_struct->tmrd;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].txsr = xmc_sdram_timing_struct->txsr;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].tras = xmc_sdram_timing_struct->tras;
/* sdtm2 trc is not care */
XMC_BANK5_6->sdtm_bit[XMC_SDRAM_BANK1].trc = xmc_sdram_timing_struct->trc;
XMC_BANK5_6->sdtm_bit[XMC_SDRAM_BANK2].twr = xmc_sdram_timing_struct->twr;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trc = xmc_sdram_timing_struct->trc;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].twr = xmc_sdram_timing_struct->twr;
/* sdtm2 trp is not care */
XMC_BANK5_6->sdtm_bit[XMC_SDRAM_BANK1].trp = xmc_sdram_timing_struct->trp;
XMC_BANK5_6->sdtm_bit[XMC_SDRAM_BANK2].trcd = xmc_sdram_timing_struct->trcd;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trp = xmc_sdram_timing_struct->trp;
XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].trcd = xmc_sdram_timing_struct->trcd;
}
}
@ -532,7 +532,7 @@ void xmc_sdram_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing
void xmc_sdram_default_para_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct)
{
/* reset sdram init structure parameters values */
xmc_sdram_init_struct->bank = XMC_SDRAM_BANK1;
xmc_sdram_init_struct->sdram_bank = XMC_SDRAM_BANK1;
xmc_sdram_init_struct->internel_banks = XMC_INBK_4;
xmc_sdram_init_struct->clkdiv = XMC_NO_CLK;
xmc_sdram_init_struct->write_protection = FALSE;
@ -560,7 +560,7 @@ void xmc_sdram_default_para_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc
*/
void xmc_sdram_cmd(xmc_sdram_cmd_type *xmc_sdram_cmd_struct)
{
XMC_BANK5_6->sdcmd = (xmc_sdram_cmd_struct->auto_refresh << 5) |
XMC_SDRAM->cmd = (xmc_sdram_cmd_struct->auto_refresh << 5) |
(xmc_sdram_cmd_struct->data << 9) |
xmc_sdram_cmd_struct->cmd |
xmc_sdram_cmd_struct->cmd_banks;
@ -579,11 +579,11 @@ uint32_t xmc_sdram_status_get(xmc_sdram_bank_type xmc_bank)
{
if(xmc_bank == XMC_SDRAM_BANK1)
{
return ((XMC_BANK5_6->sdsts >> 1) & XMC_STATUS_MASK);
return ((XMC_SDRAM->sts >> 1) & XMC_STATUS_MASK);
}
else
{
return ((XMC_BANK5_6->sdsts >> 3) & XMC_STATUS_MASK);
return ((XMC_SDRAM->sts >> 3) & XMC_STATUS_MASK);
}
}
@ -594,7 +594,7 @@ uint32_t xmc_sdram_status_get(xmc_sdram_bank_type xmc_bank)
*/
void xmc_sdram_refresh_counter_set(uint32_t counter)
{
XMC_BANK5_6->sdrcnt_bit.rc = counter;
XMC_SDRAM->rcnt_bit.rc = counter;
}
/**
@ -604,7 +604,7 @@ void xmc_sdram_refresh_counter_set(uint32_t counter)
*/
void xmc_sdram_auto_refresh_set(uint32_t number)
{
XMC_BANK5_6->sdcmd_bit.art = number;
XMC_SDRAM->cmd_bit.art = number;
}
/**
@ -624,29 +624,29 @@ void xmc_sdram_auto_refresh_set(uint32_t number)
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_interrupt_enable(xmc_nand_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state)
void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state)
{
if(new_state != FALSE)
{
/* enable the selected xmc_bank2 interrupts */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2sts |= xmc_int;
XMC_BANK2->bk2is |= xmc_int;
}
/* enable the selected xmc_bank3 interrupts */
else if(xmc_bank == XMC_BANK3_NAND)
{
XMC_BANK3->bk3sts |= xmc_int;
XMC_BANK3->bk3is |= xmc_int;
}
/* enable the selected xmc_bank4 interrupts */
else if(xmc_bank == XMC_BANK4_PCCARD)
{
XMC_BANK4->bk4sts |= xmc_int;
XMC_BANK4->bk4is |= xmc_int;
}
/* enable the selected xmc_bank5_6 interrupts */
/* enable the selected xmc_sdram interrupts */
else
{
XMC_BANK5_6->sdrcnt |= xmc_int;
XMC_SDRAM->rcnt |= xmc_int;
}
}
else
@ -654,22 +654,22 @@ void xmc_interrupt_enable(xmc_nand_bank_type xmc_bank, xmc_interrupt_sources_typ
/* disable the selected xmc_bank2 interrupts */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2sts &= ~xmc_int;
XMC_BANK2->bk2is &= ~xmc_int;
}
/* disable the selected xmc_bank3 interrupts */
else if(xmc_bank == XMC_BANK3_NAND)
{
XMC_BANK3->bk3sts &= ~xmc_int;
XMC_BANK3->bk3is &= ~xmc_int;
}
/* disable the selected xmc_bank4 interrupts */
else if(xmc_bank == XMC_BANK4_PCCARD)
{
XMC_BANK4->bk4sts &= ~xmc_int;
XMC_BANK4->bk4is &= ~xmc_int;
}
/* disable the selected xmc_bank5_6 interrupts */
/* disable the selected xmc_sdram interrupts */
else
{
XMC_BANK5_6->sdrcnt &= ~xmc_int;
XMC_SDRAM->rcnt &= ~xmc_int;
}
}
}
@ -692,26 +692,26 @@ void xmc_interrupt_enable(xmc_nand_bank_type xmc_bank, xmc_interrupt_sources_typ
* - XMC_ERR_FLAG
* @retval none
*/
flag_status xmc_flag_status_get(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
{
flag_status status = RESET;
uint32_t temp = 0;
if(xmc_bank == XMC_BANK2_NAND)
{
temp = XMC_BANK2->bk2sts;
temp = XMC_BANK2->bk2is;
}
else if(xmc_bank == XMC_BANK3_NAND)
{
temp = XMC_BANK3->bk3sts;
temp = XMC_BANK3->bk3is;
}
else if(xmc_bank == XMC_BANK4_PCCARD)
{
temp = XMC_BANK4->bk4sts;
temp = XMC_BANK4->bk4is;
}
else
{
temp = XMC_BANK5_6->sdsts;
temp = XMC_SDRAM->sts;
}
/* get the flag status */
if((temp & xmc_flag) == RESET)
@ -739,27 +739,30 @@ flag_status xmc_flag_status_get(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_
* - XMC_RISINGEDGE_FLAG
* - XMC_LEVEL_FLAG
* - XMC_FALLINGEDGE_FLAG
* - XMC_FEMPT_FLAG
* - XMC_REFRESH_FLAG
* - XMC_ERR_FLAG
* @retval none
*/
void xmc_flag_clear(xmc_nand_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
{
__IO uint32_t int_state;
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2sts &= ~xmc_flag;
int_state = XMC_BANK2->bk2is & 0x38; /* keep interrupt state */
XMC_BANK2->bk2is = (~(xmc_flag | 0x38) | int_state);
}
else if(xmc_bank == XMC_BANK3_NAND)
{
XMC_BANK3->bk3sts &= ~xmc_flag;
int_state = XMC_BANK3->bk3is & 0x38; /* keep interrupt state */
XMC_BANK3->bk3is = (~(xmc_flag | 0x38) | int_state);
}
else if(xmc_bank == XMC_BANK4_PCCARD)
{
XMC_BANK4->bk4sts &= ~xmc_flag;
int_state = XMC_BANK4->bk4is & 0x38; /* keep interrupt state */
XMC_BANK4->bk4is = (~(xmc_flag | 0x38) | int_state);
}
else
{
XMC_BANK5_6->sdrcnt |= xmc_flag;
XMC_SDRAM->rcnt |= xmc_flag;
}
}
@ -772,7 +775,7 @@ void xmc_pccard_reset(void)
{
/* Set the XMC_Bank4 registers to their reset values */
XMC_BANK4->bk4ctrl = 0x00000018;
XMC_BANK4->bk4sts = 0x00000000;
XMC_BANK4->bk4is = 0x00000000;
XMC_BANK4->bk4tmgatt = 0xFCFCFCFC;
XMC_BANK4->bk4tmgio = 0xFCFCFCFC;
XMC_BANK4->bk4tmgmem = 0xFCFCFCFC;
@ -864,17 +867,17 @@ void xmc_pccard_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_re
xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct,
xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct)
{
xmc_regular_spacetiming_struct->nand_bank = XMC_BANK4_PCCARD;
xmc_regular_spacetiming_struct->class_bank = XMC_BANK4_PCCARD;
xmc_regular_spacetiming_struct->mem_hold_time = 0xFC;
xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
xmc_special_spacetiming_struct->nand_bank = XMC_BANK4_PCCARD;
xmc_special_spacetiming_struct->class_bank = XMC_BANK4_PCCARD;
xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
xmc_special_spacetiming_struct->mem_hiz_time = 0xFC;
xmc_iospace_timing_struct->nand_bank = XMC_BANK4_PCCARD;
xmc_iospace_timing_struct->class_bank = XMC_BANK4_PCCARD;
xmc_iospace_timing_struct->mem_hold_time = 0xFC;
xmc_iospace_timing_struct->mem_waite_time = 0xFC;
xmc_iospace_timing_struct->mem_setup_time = 0xFC;

4
middlewares/i2c_application_library/i2c_application.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file i2c_application.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief the driver library of the i2c peripheral
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/i2c_application_library/i2c_application.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file i2c_application.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief i2c application libray header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usb_core.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usb_core.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb core header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usb_std.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usb_std.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb standard header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usbd_core.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_core.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb device core header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usbd_int.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_int.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb interrupt header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usbd_sdr.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usb_sdr.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb header file
**************************************************************************
* Copyright notice & Disclaimer

5
middlewares/usb_drivers/inc/usbh_core.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_core.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb host core header file
**************************************************************************
* Copyright notice & Disclaimer
@ -301,6 +301,7 @@ typedef struct
uint32_t conn_sts; /*!< connect status */
uint32_t port_enable; /*!< port enable status */
uint32_t timer; /*!< sof timer */
uint32_t err_cnt[USB_HOST_CHANNEL_NUM]; /*!< error counter */
uint32_t xfer_cnt[USB_HOST_CHANNEL_NUM]; /*!< xfer counter */

4
middlewares/usb_drivers/inc/usbh_ctrl.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_ctrl.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb header file
**************************************************************************
* Copyright notice & Disclaimer

5
middlewares/usb_drivers/inc/usbh_int.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_int.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb header file
**************************************************************************
* Copyright notice & Disclaimer
@ -55,6 +55,7 @@ void usbh_hch_in_handler(usbh_core_type *uhost, uint8_t chn);
void usbh_hch_out_handler(usbh_core_type *uhost, uint8_t chn);
void usbh_rx_qlvl_handler(usbh_core_type *uhost);
void usbh_wakeup_handler(usbh_core_type *uhost);
void usbh_sof_handler(usbh_core_type *uhost);
/**
* @}

4
middlewares/usb_drivers/src/usb_core.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usb_core.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb driver
**************************************************************************
* Copyright notice & Disclaimer

8
middlewares/usb_drivers/src/usbd_core.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_core.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb device driver
**************************************************************************
* Copyright notice & Disclaimer
@ -645,7 +645,7 @@ void usbd_enter_suspend(usbd_core_type *udev)
void usbd_flush_tx_fifo(usbd_core_type *udev, uint8_t ept_num)
{
/* flush endpoint tx fifo */
usb_flush_tx_fifo(udev->usb_reg, ept_num & 0xF);
usb_flush_tx_fifo(udev->usb_reg, ept_num & 0x1F);
}
/**
@ -759,6 +759,8 @@ usb_sts_type usbd_core_init(usbd_core_type *udev,
udev->device_addr = 0;
udev->class_handler = class_handler;
udev->desc_handler = desc_handler;
/* set device disconnect */
usbd_disconnect(udev);
/* set endpoint to default status */
usb_ept_default_init(udev);

8
middlewares/usb_drivers/src/usbd_int.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_int.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb interrupt request
**************************************************************************
* Copyright notice & Disclaimer
@ -425,8 +425,8 @@ void usbd_reset_handler(usbd_core_type *udev)
/* endpoint fifo alloc */
usbd_fifo_alloc(udev);
/* flush tx fifo 0 */
usb_flush_tx_fifo(usbx, 0);
/* flush all tx fifo */
usb_flush_tx_fifo(usbx, 0x10);
/* clear in and out endpoint interrupt flag */
for(i_index = 0; i_index < USB_EPT_MAX_NUM; i_index ++)

4
middlewares/usb_drivers/src/usbd_sdr.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_sdr.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb standard device request
**************************************************************************
* Copyright notice & Disclaimer

35
middlewares/usb_drivers/src/usbh_core.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_core.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb host driver
**************************************************************************
* Copyright notice & Disclaimer
@ -512,6 +512,8 @@ usb_sts_type usbh_core_init(usbh_core_type *uhost,
/* host user handler */
uhost->user_handler->user_init();
uhost->timer = 0;
/* usb host cfg default init */
usbh_cfg_default_init(uhost);
@ -542,9 +544,6 @@ usb_sts_type usbh_core_init(usbh_core_type *uhost,
/* clock select */
usbh_fsls_clksel(usbx, USB_HCFG_CLK_48M);
/* reset host port */
usbh_reset_port(uhost);
/* set support ls and fs device */
host->hcfg_bit.fslssupp = 0;
@ -950,11 +949,13 @@ void usbh_reset_port(usbh_core_type *uhost)
/* set port reset */
usb_host->hprt = hprt_val | USB_OTG_HPRT_PRTRST;
usb_delay_ms(10);
usb_delay_ms(100);
/* clear port reset */
usb_host->hprt = hprt_val & (~USB_OTG_HPRT_PRTRST);
usb_delay_ms(20);
}
/**
@ -968,9 +969,6 @@ static void usbh_attached(usbh_core_type *uhost)
uhost->ctrl.hch_in = usbh_alloc_channel(uhost, 0x80);
uhost->ctrl.hch_out = usbh_alloc_channel(uhost, 0x00);
/* reset port */
usbh_reset_port(uhost);
/* user reset callback handler */
uhost->user_handler->user_reset();
@ -991,6 +989,9 @@ static void usbh_attached(usbh_core_type *uhost)
uhost->ctrl.ept0_size,
uhost->dev.speed);
usb_flush_tx_fifo(uhost->usb_reg, 0x10);
usb_flush_rx_fifo(uhost->usb_reg);
/* user attached callback */
uhost->user_handler->user_attached();
}
@ -1027,7 +1028,7 @@ static void usbh_class_request(usbh_core_type *uhost)
{
uhost->global_state = USBH_CLASS;
}
else if(status == USB_ERROR)
else if(status == USB_ERROR || status == USB_FAIL)
{
uhost->global_state = USBH_ERROR_STATE;
}
@ -1133,7 +1134,13 @@ static void usbh_disconnect(usbh_core_type *uhost)
usb_sts_type usbh_loop_handler(usbh_core_type *uhost)
{
usb_sts_type status = USB_FAIL;
if(uhost->conn_sts == 0 &&
uhost->global_state != USBH_IDLE &&
uhost->global_state != USBH_DISCONNECT)
{
uhost->global_state = USBH_IDLE;
}
switch(uhost->global_state)
{
case USBH_IDLE:
@ -1141,6 +1148,9 @@ usb_sts_type usbh_loop_handler(usbh_core_type *uhost)
{
uhost->global_state = USBH_PORT_EN;
/* wait stable */
usb_delay_ms(200);
/* port reset */
usbh_reset_port(uhost);
@ -1153,9 +1163,6 @@ usb_sts_type usbh_loop_handler(usbh_core_type *uhost)
if(uhost->port_enable)
{
uhost->global_state = USBH_ATTACHED;
/* wait stable */
usb_delay_ms(50);
}
break;

9
middlewares/usb_drivers/src/usbh_ctrl.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_ctrl.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb host control request
**************************************************************************
* Copyright notice & Disclaimer
@ -365,7 +365,10 @@ usb_sts_type usbh_ctrl_error_handler(usbh_core_type *uhost)
else
{
uhost->ctrl.sts = CTRL_FAIL;
status = USB_FAIL;
uhost->global_state = USBH_DISCONNECT;
uhost->ctrl.err_cnt = 0;
USBH_DEBUG("control error: device not response");
status = USB_ERROR;
}
return status;
}

24
middlewares/usb_drivers/src/usbh_int.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_int.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb host interrupt request
**************************************************************************
* Copyright notice & Disclaimer
@ -59,6 +59,7 @@ void usbh_irq_handler(otg_core_type *otgdev)
}
if(intsts & USB_OTG_SOF_FLAG)
{
usbh_sof_handler(uhost);
usb_global_clear_interrupt(usbx, USB_OTG_SOF_FLAG);
}
if(intsts & USB_OTG_MODEMIS_FLAG)
@ -114,6 +115,16 @@ void usbh_wakeup_handler(usbh_core_type *uhost)
uhost->global_state = USBH_WAKEUP;
}
/**
* @brief usb host sof handler
* @param uhost: to the structure of usbh_core_type
* @retval none
*/
void usbh_sof_handler(usbh_core_type *uhost)
{
uhost->timer ++;
}
/**
* @brief usb host disconnect handler
* @param uhost: to the structure of usbh_core_type
@ -194,7 +205,11 @@ void usbh_hch_in_handler(usbh_core_type *uhost, uint8_t chn)
usb_chh->hcchar_bit.oddfrm = TRUE;
uhost->urb_state[chn] = URB_DONE;
}
uhost->hch[chn].toggle_in ^= 1;
else if(usb_chh->hcchar_bit.eptype == EPT_ISO_TYPE)
{
uhost->urb_state[chn] = URB_DONE;
}
uhost->hch[chn].toggle_in ^= 1;
}
else if(hcint_value & USB_OTG_HC_CHHLTD_FLAG)
{
@ -436,8 +451,6 @@ void usbh_port_handler(usbh_core_type *uhost)
{
if(prt & USB_OTG_HPRT_PRTCONSTS)
{
/* usb unmask disconnect */
usbx->gintmsk_bit.disconintmsk = 0;
/* connect callback */
uhost->conn_sts = 1;
}
@ -466,7 +479,6 @@ void usbh_port_handler(usbh_core_type *uhost)
/* clean up hprt */
usb_host->hprt &= ~(USB_OTG_HPRT_PRTENA | USB_OTG_HPRT_PRTENCHNG |
USB_OTG_HPRT_PRTOVRCACT | USB_OTG_HPRT_PRTCONDET);
usbx->gintmsk_bit.disconintmsk = 1;
}
}

81
middlewares/usbd_class/audio/audio_class.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_class.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb audio class type
**************************************************************************
* Copyright notice & Disclaimer
@ -62,6 +62,8 @@ void audio_set_interface(void *udev, usb_setup_type *setup);
usb_audio_type audio_struct = {0, 0, 0, 0, 0, 0x1400, 0, 0, 0, {0x0000, 0x1400, 0x33}, {0x0000, 0x1400, 0x33}};
static __IO uint16_t audio_feedback_state = 0;
static __IO uint8_t audio_spk_out_stage = 0;
/* usb device class handler */
usbd_class_handler audio_class_handler =
{
@ -114,8 +116,10 @@ usb_sts_type class_clear_handler(void *udev)
/* close in endpoint */
usbd_ept_close(pudev, USBD_AUDIO_MIC_IN_EPT);
#if AUDIO_SUPPORT_FEEDBACK
/* close in endpoint */
usbd_ept_close(pudev, USBD_AUDIO_FEEDBACK_EPT);
#endif
/* close out endpoint */
usbd_ept_close(pudev, USBD_AUDIO_SPK_OUT_EPT);
@ -294,7 +298,6 @@ usb_sts_type class_ept0_rx_handler(void *udev)
usb_sts_type class_in_handler(void *udev, uint8_t ept_num)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
uint32_t len = 0;
/* ...user code...
@ -303,15 +306,13 @@ usb_sts_type class_in_handler(void *udev, uint8_t ept_num)
if((ept_num & 0x7F) == (USBD_AUDIO_MIC_IN_EPT & 0x7F))
{
len = audio_codec_mic_get_data(audio_struct.audio_mic_data);
usb_flush_tx_fifo(pudev->usb_reg, USBD_AUDIO_MIC_IN_EPT & 0x7F);
usbd_ept_send(pudev, USBD_AUDIO_MIC_IN_EPT, audio_struct.audio_mic_data, len);
usbd_flush_tx_fifo(udev, USBD_AUDIO_MIC_IN_EPT);
usbd_ept_send(udev, USBD_AUDIO_MIC_IN_EPT, audio_struct.audio_mic_data, len);
}
else if((ept_num & 0x7F) == (USBD_AUDIO_FEEDBACK_EPT & 0x7F))
{
len = audio_codec_spk_feedback(audio_struct.audio_feed_back);
usb_flush_tx_fifo(pudev->usb_reg, USBD_AUDIO_FEEDBACK_EPT & 0x7F);
usbd_ept_send(pudev, USBD_AUDIO_FEEDBACK_EPT, audio_struct.audio_feed_back, len);
audio_feedback_state = 0;
}
return status;
@ -336,7 +337,7 @@ usb_sts_type class_out_handler(void *udev, uint8_t ept_num)
{
/* speaker data*/
audio_codec_spk_fifo_write(audio_struct.audio_spk_data, g_rxlen);
audio_spk_out_stage = 1;
/* get next data */
usbd_ept_recv(pudev, USBD_AUDIO_SPK_OUT_EPT, audio_struct.audio_spk_data, AUDIO_SPK_OUT_MAXPACKET_SIZE);
}
@ -352,7 +353,33 @@ usb_sts_type class_out_handler(void *udev, uint8_t ept_num)
usb_sts_type class_sof_handler(void *udev)
{
usb_sts_type status = USB_OK;
#if AUDIO_SUPPORT_FEEDBACK
if(audio_spk_out_stage & 2)
{
audio_spk_out_stage = 0;
}
else if( audio_spk_out_stage )
{
audio_spk_out_stage |= 2;
if( 0 == audio_feedback_state )
{
usbd_core_type *pudev = (usbd_core_type *)udev;
int len = audio_codec_spk_feedback(audio_struct.audio_feed_back);
usbd_ept_send(pudev, USBD_AUDIO_FEEDBACK_EPT, audio_struct.audio_feed_back, len);
audio_feedback_state = 1;
}
if( audio_feedback_state++ > (1<<FEEDBACK_REFRESH_TIME) ) //timeout
{
usbd_core_type *pudev = (usbd_core_type *)udev;
int len = audio_codec_spk_feedback(audio_struct.audio_feed_back);
usbd_flush_tx_fifo(pudev, USBD_AUDIO_FEEDBACK_EPT);
usbd_ept_send(pudev, USBD_AUDIO_FEEDBACK_EPT, audio_struct.audio_feed_back, len);
audio_feedback_state = 1;
}
}
#endif
/* ...user code... */
return status;
@ -403,6 +430,7 @@ usb_sts_type class_event_handler(void *udev, usbd_event_type event)
*/
void audio_inisoincom_event(void *udev)
{
#if 0
usbd_core_type *pudev = (usbd_core_type *)udev;
uint32_t fnsof = OTG_DEVICE(pudev->usb_reg)->dsts_bit.soffn;
uint32_t epctl_fb = USB_INEPT(pudev->usb_reg, (USBD_AUDIO_FEEDBACK_EPT&0x7F))->diepctl_bit.dpid;
@ -427,7 +455,7 @@ void audio_inisoincom_event(void *udev)
len = audio_codec_mic_get_data(audio_struct.audio_mic_data);
usbd_ept_send(pudev, USBD_AUDIO_MIC_IN_EPT, audio_struct.audio_mic_data, len);
}
#endif
}
/**
@ -443,22 +471,26 @@ void audio_req_get_cur(void *udev, usb_setup_type *setup)
{
if(HBYTE(setup->wValue) == AUDIO_MUTE_CONTROL)
{
usbd_ctrl_send(pudev, &audio_struct.spk_mute, setup->wLength);
audio_struct.g_audio_cur[0] = audio_struct.spk_mute;
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
else
{
usbd_ctrl_send(pudev, (uint8_t *)&audio_struct.spk_volume, setup->wLength);
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.spk_volume;
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
}
else
{
if(HBYTE(setup->wValue) == AUDIO_MUTE_CONTROL)
{
usbd_ctrl_send(pudev, &audio_struct.mic_mute, setup->wLength);
audio_struct.g_audio_cur[0] = audio_struct.mic_mute;
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
else
{
usbd_ctrl_send(pudev, (uint8_t *)&audio_struct.mic_volume, setup->wLength);
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.mic_volume;
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
}
@ -514,11 +546,13 @@ void audio_req_get_min(void *udev, usb_setup_type *setup)
usbd_core_type *pudev = (usbd_core_type *)udev;
if(HBYTE(setup->wIndex) == AUDIO_SPK_FEATURE_UNIT_ID)
{
usbd_ctrl_send(pudev, (uint8_t *)&audio_struct.spk_volume_limits[0], setup->wLength);
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.spk_volume_limits[0];
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
else
{
usbd_ctrl_send(pudev, (uint8_t *)&audio_struct.mic_volume_limits[0], setup->wLength);
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.mic_volume_limits[0];
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
}
@ -533,11 +567,13 @@ void audio_req_get_max(void *udev, usb_setup_type *setup)
usbd_core_type *pudev = (usbd_core_type *)udev;
if(HBYTE(setup->wIndex) == AUDIO_SPK_FEATURE_UNIT_ID)
{
usbd_ctrl_send(pudev, (uint8_t *)&audio_struct.spk_volume_limits[1], setup->wLength);
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.spk_volume_limits[1];
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
else
{
usbd_ctrl_send(pudev, (uint8_t *)&audio_struct.mic_volume_limits[1], setup->wLength);
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.mic_volume_limits[1];
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
}
@ -552,11 +588,13 @@ void audio_req_get_res(void *udev, usb_setup_type *setup)
usbd_core_type *pudev = (usbd_core_type *)udev;
if(HBYTE(setup->wIndex) == AUDIO_SPK_FEATURE_UNIT_ID)
{
usbd_ctrl_send(pudev, (uint8_t *)&audio_struct.spk_volume_limits[2], setup->wLength);
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.spk_volume_limits[2];
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
else
{
usbd_ctrl_send(pudev, (uint8_t *)&audio_struct.mic_volume_limits[2], setup->wLength);
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.mic_volume_limits[2];
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
}
@ -577,7 +615,6 @@ void audio_set_interface(void *udev, usb_setup_type *setup)
if(audio_struct.spk_alt_setting )
{
usbd_ept_recv(pudev, USBD_AUDIO_SPK_OUT_EPT, audio_struct.audio_spk_data, AUDIO_SPK_OUT_MAXPACKET_SIZE);
usbd_ept_send(pudev, USBD_AUDIO_FEEDBACK_EPT, audio_struct.audio_feed_back, 3);
}
}

8
middlewares/usbd_class/audio/audio_class.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_class.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb audio class file
**************************************************************************
* Copyright notice & Disclaimer
@ -58,11 +58,11 @@ extern "C" {
/**
* @brief endpoint support max size
*/
#define AUDIO_REMAIN_SIZE 8
#define AUDIO_REMAIN_SIZE 40
#define AUDIO_MIC_IN_MAXPACKET_SIZE (AUDIO_SUPPORT_MAX_FREQ * AUDIO_MIC_CHANEL_NUM * (AUDIO_MIC_DEFAULT_BITW / 8) + AUDIO_REMAIN_SIZE)
#define AUDIO_SPK_OUT_MAXPACKET_SIZE (AUDIO_SUPPORT_MAX_FREQ * AUDIO_SPK_CHANEL_NUM * (AUDIO_SPK_DEFAULT_BITW / 8) + AUDIO_REMAIN_SIZE)
#define AUDIO_FEEDBACK_MAXPACKET_SIZE 0x3
#define FEEDBACK_REFRESH_TIME 0x8
/**
* @brief request type define
*/

8
middlewares/usbd_class/audio/audio_conf.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_conf.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb audio config
**************************************************************************
* Copyright notice & Disclaimer
@ -46,9 +46,9 @@ extern "C" {
*/
#define AUDIO_SUPPORT_SPK 1
#define AUDIO_SUPPORT_MIC 1
#define AUDIO_SUPPORT_FEEDBACK 0
#define AUDIO_SUPPORT_FEEDBACK 1
#define AUDIO_SUPPORT_FREQ_16K 1
#define AUDIO_SUPPORT_FREQ_16K 0
#define AUDIO_SUPPORT_FREQ_48K 1

28
middlewares/usbd_class/audio/audio_desc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_desc.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb audio device descriptor
**************************************************************************
* Copyright notice & Disclaimer
@ -78,7 +78,10 @@ usbd_desc_handler audio_desc_handler =
/**
* @brief usb device standard descriptor
*/
uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN] =
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN] ALIGNED_TAIL =
{
USB_DEVICE_DESC_LEN, /* bLength */
USB_DESCIPTOR_TYPE_DEVICE, /* bDescriptorType */
@ -103,7 +106,10 @@ uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN] =
/**
* @brief usb configuration standard descriptor
*/
uint8_t g_usbd_configuration[USBD_CONFIG_DESC_SIZE] =
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_usbd_configuration[USBD_CONFIG_DESC_SIZE] ALIGNED_TAIL =
{
USB_DEVICE_CFG_DESC_LEN, /* bLength: configuration descriptor size */
USB_DESCIPTOR_TYPE_CONFIGURATION, /* bDescriptorType: configuration */
@ -361,8 +367,8 @@ uint8_t g_usbd_configuration[USBD_CONFIG_DESC_SIZE] =
0x11, /* bmAttributes: endpoint attributes */
LBYTE(AUDIO_FEEDBACK_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
HBYTE(AUDIO_FEEDBACK_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
HID_BINTERVAL_TIME, /* bInterval: interval for polling endpoint for data transfers */
0x08, /* bRefresh: this field indicates the rate at which an iso syncronization
1, /* bInterval: interval for polling endpoint for data transfers */
FEEDBACK_REFRESH_TIME, /* bRefresh: this field indicates the rate at which an iso syncronization
pipe provides new syncronization feedback data. this rate must be a power of
2, therefore only the power is reported back and the range of this field is from
1(2ms) to 9(512ms) */
@ -375,7 +381,10 @@ uint8_t g_usbd_configuration[USBD_CONFIG_DESC_SIZE] =
/**
* @brief usb string lang id
*/
uint8_t g_string_lang_id[USBD_SIZ_STRING_LANGID] =
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_string_lang_id[USBD_SIZ_STRING_LANGID] ALIGNED_TAIL =
{
USBD_SIZ_STRING_LANGID,
USB_DESCIPTOR_TYPE_STRING,
@ -386,7 +395,10 @@ uint8_t g_string_lang_id[USBD_SIZ_STRING_LANGID] =
/**
* @brief usb string serial
*/
uint8_t g_string_serial[USBD_SIZ_STRING_SERIAL] =
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_string_serial[USBD_SIZ_STRING_SERIAL] ALIGNED_TAIL =
{
USBD_SIZ_STRING_SERIAL,
USB_DESCIPTOR_TYPE_STRING,

4
middlewares/usbd_class/audio/audio_desc.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_desc.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb audio descriptor header file
**************************************************************************
* Copyright notice & Disclaimer

90
middlewares/usbd_class/audio_hid/audio_conf.h Normal file
View File

@ -0,0 +1,90 @@
/**
**************************************************************************
* @file audio_conf.h
* @version v2.0.4
* @date 2021-12-31
* @brief usb audio config
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AUDIO_CONF_H
#define __AUDIO_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @addtogroup USB_audio_hid_class
* @{
*/
/** @defgroup USB_device_audio_hid_config_definition
* @{
*/
#define AUDIO_SUPPORT_SPK 1
#define AUDIO_SUPPORT_MIC 1
#define AUDIO_SUPPORT_FEEDBACK 1
#define AUDIO_SUPPORT_FREQ_16K 0
#define AUDIO_SUPPORT_FREQ_48K 1
#define AUDIO_SUPPORT_FREQ (AUDIO_SUPPORT_FREQ_16K + \
AUDIO_SUPPORT_FREQ_48K \
)
#define AUDIO_FREQ_16K 16000
#define AUDIO_FREQ_48K 48000
#define AUDIO_BITW_16 16
#define AUDIO_MIC_CHANEL_NUM 2
#define AUDIO_MIC_DEFAULT_BITW AUDIO_BITW_16
#define AUDIO_SPK_CHANEL_NUM 2
#define AUDIO_SPK_DEFAULT_BITW AUDIO_BITW_16
#define AUDIO_SUPPORT_MAX_FREQ 48
#define AUDIO_DEFAULT_FREQ AUDIO_FREQ_48K
#define AUDIO_DEFAULT_BITW AUDIO_BITW_16
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

899
middlewares/usbd_class/audio_hid/audio_hid_class.c Normal file
View File

@ -0,0 +1,899 @@
/**
**************************************************************************
* @file audio_class.c
* @version v2.0.4
* @date 2021-12-31
* @brief usb audio class type
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "usbd_core.h"
#include "audio_hid_class.h"
#include "audio_hid_desc.h"
#include "audio_codec.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @defgroup USB_audio_hid_class
* @brief usb device class audio hid demo
* @{
*/
/** @defgroup USB_audio_hid_class_private_functions
* @{
*/
usb_sts_type class_init_handler(void *udev);
usb_sts_type class_clear_handler(void *udev);
usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup);
usb_sts_type class_ept0_tx_handler(void *udev);
usb_sts_type class_ept0_rx_handler(void *udev);
usb_sts_type class_in_handler(void *udev, uint8_t ept_num);
usb_sts_type class_out_handler(void *udev, uint8_t ept_num);
usb_sts_type class_sof_handler(void *udev);
usb_sts_type class_event_handler(void *udev, usbd_event_type event);
void audio_inisoincom_event(void *udev);
void audio_req_get_cur(void *udev, usb_setup_type *setup);
void audio_req_set_cur(void *udev, usb_setup_type *setup);
void audio_req_get_min(void *udev, usb_setup_type *setup);
void audio_req_get_max(void *udev, usb_setup_type *setup);
void audio_req_get_res(void *udev, usb_setup_type *setup);
void audio_get_interface(void *udev, usb_setup_type *setup);
void audio_set_interface(void *udev, usb_setup_type *setup);
void usb_hid_buf_process(void *udev, uint8_t *report, uint16_t len);
/* usb hid rx and tx buffer */
static uint8_t g_rxhid_buff[USBD_OUT_MAXPACKET_SIZE];
static uint8_t g_txhid_buff[USBD_IN_MAXPACKET_SIZE];
usb_audio_type audio_struct = {0, 0, 0, 0, 0, 0x1400, 0, 0, 0, {0x0000, 0x1400, 0x33}, {0x0000, 0x1400, 0x33}};
/* custom hid static variable */
static uint32_t hid_protocol = 0;
static uint32_t hid_set_idle = 0;
static uint32_t alt_setting = 0;
static uint8_t hid_state;
uint8_t hid_set_report[64];
static __IO uint16_t audio_feedback_state = 0;
static __IO uint8_t audio_spk_out_stage = 0;
/* usb device class handler */
usbd_class_handler audio_hid_class_handler =
{
class_init_handler,
class_clear_handler,
class_setup_handler,
class_ept0_tx_handler,
class_ept0_rx_handler,
class_in_handler,
class_out_handler,
class_sof_handler,
class_event_handler,
};
/**
* @brief initialize usb custom hid endpoint
* @param udev: usb device core handler type
* @retval status of usb_sts_type
*/
usb_sts_type class_init_handler(void *udev)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
/* open microphone in endpoint */
usbd_ept_open(pudev, USBD_AUDIO_MIC_IN_EPT, EPT_ISO_TYPE, AUDIO_MIC_IN_MAXPACKET_SIZE);
/* open speaker out endpoint */
usbd_ept_open(pudev, USBD_AUDIO_SPK_OUT_EPT, EPT_ISO_TYPE, AUDIO_SPK_OUT_MAXPACKET_SIZE);
#if AUDIO_SUPPORT_FEEDBACK
/* open speaker feedback endpoint */
usbd_ept_open(pudev, USBD_AUDIO_FEEDBACK_EPT, EPT_ISO_TYPE, AUDIO_FEEDBACK_MAXPACKET_SIZE);
#endif
/* start receive speaker out data */
usbd_ept_recv(pudev, USBD_AUDIO_SPK_OUT_EPT, audio_struct.audio_spk_data, AUDIO_SPK_OUT_MAXPACKET_SIZE);
/*open hid endpoint */
/* open custom hid in endpoint */
usbd_ept_open(pudev, USBD_HID_IN_EPT, EPT_INT_TYPE, USBD_IN_MAXPACKET_SIZE);
/* open custom hid out endpoint */
usbd_ept_open(pudev, USBD_HID_OUT_EPT, EPT_INT_TYPE, USBD_OUT_MAXPACKET_SIZE);
/* set out endpoint to receive status */
usbd_ept_recv(pudev, USBD_HID_OUT_EPT, g_rxhid_buff, USBD_OUT_MAXPACKET_SIZE);
return status;
}
/**
* @brief clear endpoint or other state
* @param udev: usb device core handler type
* @retval status of usb_sts_type
*/
usb_sts_type class_clear_handler(void *udev)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
/* close in endpoint */
usbd_ept_close(pudev, USBD_AUDIO_MIC_IN_EPT);
#if AUDIO_SUPPORT_FEEDBACK
/* close in endpoint */
usbd_ept_close(pudev, USBD_AUDIO_FEEDBACK_EPT);
#endif
/* close out endpoint */
usbd_ept_close(pudev, USBD_AUDIO_SPK_OUT_EPT);
/* close custom hid in endpoint */
usbd_ept_close(pudev, USBD_HID_IN_EPT);
/* close custom hid out endpoint */
usbd_ept_close(pudev, USBD_HID_OUT_EPT);
return status;
}
/**
* @brief usb device class setup request handler
* @param udev: usb device core handler type
* @param setup: setup packet
* @retval status of usb_sts_type
*/
usb_sts_type class_audio_setup_handler(void *udev, usb_setup_type *setup)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
uint16_t len;
switch(setup->bmRequestType & USB_REQ_TYPE_RESERVED)
{
/* class request */
case USB_REQ_TYPE_CLASS:
switch(setup->bRequest)
{
case AUDIO_REQ_GET_CUR:
audio_req_get_cur(pudev, setup);
break;
case AUDIO_REQ_SET_CUR:
audio_req_set_cur(pudev, setup);
break;
case AUDIO_REQ_GET_MIN:
audio_req_get_min(pudev, setup);
break;
case AUDIO_REQ_GET_MAX:
audio_req_get_max(pudev, setup);
break;
case AUDIO_REQ_GET_RES:
audio_req_get_res(pudev, setup);
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;
/* standard request */
case USB_REQ_TYPE_STANDARD:
switch(setup->bRequest)
{
case USB_STD_REQ_GET_DESCRIPTOR:
if((setup->wValue >> 8) == AUDIO_DESCRIPTOR_TYPE)
{
len = MIN(AUDIO_DESCRIPTOR_SIZE, setup->wLength);
usbd_ctrl_send(pudev, g_usbd_configuration+18, len);
}
else
{
usbd_ctrl_unsupport(pudev);
}
break;
case USB_STD_REQ_GET_INTERFACE:
audio_get_interface(udev, setup);
break;
case USB_STD_REQ_SET_INTERFACE:
audio_set_interface(udev, setup);
usbd_ctrl_send_status(pudev);
break;
default:
break;
}
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
return status;
}
/**
* @brief usb device class setup request handler
* @param udev: usb device core handler type
* @param setup: setup packet
* @retval status of usb_sts_type
*/
usb_sts_type class_hid_setup_handler(void *udev, usb_setup_type *setup)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
uint16_t len;
uint8_t *buf;
switch(setup->bmRequestType & USB_REQ_TYPE_RESERVED)
{
/* class request */
case USB_REQ_TYPE_CLASS:
switch(setup->bRequest)
{
case HID_REQ_SET_PROTOCOL:
hid_protocol = (uint8_t)setup->wValue;
break;
case HID_REQ_GET_PROTOCOL:
usbd_ctrl_send(pudev, (uint8_t *)&hid_protocol, 1);
break;
case HID_REQ_SET_IDLE:
hid_set_idle = (uint8_t)(setup->wValue >> 8);
break;
case HID_REQ_GET_IDLE:
usbd_ctrl_send(pudev, (uint8_t *)&hid_set_idle, 1);
break;
case HID_REQ_SET_REPORT:
hid_state = HID_REQ_SET_REPORT;
usbd_ctrl_recv(pudev, hid_set_report, setup->wLength);
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
break;
/* standard request */
case USB_REQ_TYPE_STANDARD:
switch(setup->bRequest)
{
case USB_STD_REQ_GET_DESCRIPTOR:
if(setup->wValue >> 8 == HID_REPORT_DESC)
{
len = MIN(USBD_HID_SIZ_REPORT_DESC, setup->wLength);
buf = (uint8_t *)g_usbd_hid_report;
}
else if(setup->wValue >> 8 == HID_DESCRIPTOR_TYPE)
{
len = MIN(9, setup->wLength);
buf = (uint8_t *)g_hid_usb_desc;
}
usbd_ctrl_send(pudev, (uint8_t *)buf, len);
break;
case USB_STD_REQ_GET_INTERFACE:
usbd_ctrl_send(pudev, (uint8_t *)&alt_setting, 1);
break;
case USB_STD_REQ_SET_INTERFACE:
alt_setting = setup->wValue;
break;
default:
break;
}
break;
default:
usbd_ctrl_unsupport(pudev);
break;
}
return status;
}
/**
* @brief usb device class setup request handler
* @param udev: usb device core handler type
* @param setup: setup packet
* @retval status of usb_sts_type
*/
usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
switch(setup->bmRequestType & USB_REQ_RECIPIENT_MASK)
{
case USB_REQ_RECIPIENT_INTERFACE:
if(setup->wIndex == HID_INTERFACE_NUMBER)
{
class_hid_setup_handler(udev, setup);
}
else
{
class_audio_setup_handler(pudev, setup);
}
break;
case USB_REQ_RECIPIENT_ENDPOINT:
class_audio_setup_handler(pudev, setup);
break;
}
return status;
}
/**
* @brief usb device endpoint 0 in status stage complete
* @param udev: usb device core handler type
* @retval status of usb_sts_type
*/
usb_sts_type class_ept0_tx_handler(void *udev)
{
usb_sts_type status = USB_OK;
/* ...user code... */
return status;
}
/**
* @brief usb device endpoint 0 out status stage complete
* @param udev: usb device core handler type
* @retval status of usb_sts_type
*/
usb_sts_type class_ept0_rx_handler(void *udev)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
usb_setup_type *setup = &pudev->setup;
uint32_t recv_len = usbd_get_recv_len(pudev, 0);
/* ...user code... */
if(setup->wIndex == HID_INTERFACE_NUMBER)
{
if( hid_state == HID_REQ_SET_REPORT)
{
/* hid buffer process */
usb_hid_buf_process(udev, hid_set_report, recv_len);
hid_state = 0;
}
}
else
{
/* ...user code... */
if( audio_struct.audio_cmd == AUDIO_REQ_SET_CUR)
{
/* class process */
switch(audio_struct.request_no)
{
case AUDIO_VOLUME_CONTROL:
if(audio_struct.interface == AUDIO_SPK_FEATURE_UNIT_ID)
{
audio_struct.spk_volume = (uint16_t)(audio_struct.g_audio_cur[0] |
(audio_struct.g_audio_cur[1] << 8));
/* set volume */
audio_codec_set_spk_volume(audio_struct.spk_volume*100/audio_struct.spk_volume_limits[1]);
}
else
{
audio_struct.mic_volume = (uint16_t)(audio_struct.g_audio_cur[0] |
(audio_struct.g_audio_cur[1] << 8));
audio_codec_set_mic_volume(audio_struct.mic_volume*256/audio_struct.mic_volume_limits[1]);
}
break;
case AUDIO_MUTE_CONTROL:
if(audio_struct.interface == AUDIO_SPK_FEATURE_UNIT_ID)
{
audio_struct.spk_mute = audio_struct.g_audio_cur[0];
audio_codec_set_spk_mute(audio_struct.spk_mute);
}
else
{
audio_struct.mic_mute = audio_struct.g_audio_cur[0];
audio_codec_set_mic_mute(audio_struct.mic_mute);
}
break;
case AUDIO_FREQ_SET_CONTROL:
if(audio_struct.enpd == USBD_AUDIO_MIC_IN_EPT)
{
audio_struct.mic_freq = (audio_struct.g_audio_cur[0] |
(audio_struct.g_audio_cur[1] << 8) |
(audio_struct.g_audio_cur[2] << 16));
audio_codec_set_mic_freq(audio_struct.mic_freq);
}
else
{
audio_struct.spk_freq = (audio_struct.g_audio_cur[0] |
(audio_struct.g_audio_cur[1] << 8) |
(audio_struct.g_audio_cur[2] << 16));
audio_codec_set_spk_freq(audio_struct.spk_freq);
}
break;
default:
break;
}
}
}
return status;
}
/**
* @brief usb device transmision complete handler
* @param udev: usb device core handler type
* @param ept_num: endpoint number
* @retval status of usb_sts_type
*/
usb_sts_type class_in_handler(void *udev, uint8_t ept_num)
{
usb_sts_type status = USB_OK;
uint32_t len = 0;
/* ...user code...
trans next packet data
*/
if((ept_num & 0x7F) == (USBD_AUDIO_MIC_IN_EPT & 0x7F))
{
len = audio_codec_mic_get_data(audio_struct.audio_mic_data);
usbd_flush_tx_fifo(udev, USBD_AUDIO_MIC_IN_EPT);
usbd_ept_send(udev, USBD_AUDIO_MIC_IN_EPT, audio_struct.audio_mic_data, len);
}
else if((ept_num & 0x7F) == (USBD_AUDIO_FEEDBACK_EPT & 0x7F))
{
audio_feedback_state = 0;
}
else if((ept_num & 0x7F) == (USBD_HID_IN_EPT & 0x7F))
{
usbd_flush_tx_fifo(udev, USBD_HID_IN_EPT);
}
return status;
}
/**
* @brief usb device endpoint receive data
* @param udev: usb device core handler type
* @param ept_num: endpoint number
* @retval status of usb_sts_type
*/
usb_sts_type class_out_handler(void *udev, uint8_t ept_num)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
uint16_t g_rxlen;
/* get endpoint receive data length */
g_rxlen = usbd_get_recv_len(pudev, ept_num);
if((ept_num & 0x7F) == (USBD_AUDIO_SPK_OUT_EPT & 0x7F))
{
/* speaker data*/
audio_codec_spk_fifo_write(audio_struct.audio_spk_data, g_rxlen);
audio_spk_out_stage = 1;
/* get next data */
usbd_ept_recv(pudev, USBD_AUDIO_SPK_OUT_EPT, audio_struct.audio_spk_data, AUDIO_SPK_OUT_MAXPACKET_SIZE);
}
else if((ept_num & 0x7F) == (USBD_HID_OUT_EPT & 0x7F))
{
/* hid buffer process */
usb_hid_buf_process(udev, g_rxhid_buff, g_rxlen);
/* start receive next packet */
usbd_ept_recv(pudev, USBD_HID_OUT_EPT, g_rxhid_buff, USBD_OUT_MAXPACKET_SIZE);
}
return status;
}
/**
* @brief usb device sof handler
* @param udev: usb device core handler type
* @retval status of usb_sts_type
*/
usb_sts_type class_sof_handler(void *udev)
{
usb_sts_type status = USB_OK;
#if AUDIO_SUPPORT_FEEDBACK
if(audio_spk_out_stage & 2)
{
audio_spk_out_stage = 0;
}
else if( audio_spk_out_stage )
{
audio_spk_out_stage |= 2;
if( 0 == audio_feedback_state )
{
usbd_core_type *pudev = (usbd_core_type *)udev;
int len = audio_codec_spk_feedback(audio_struct.audio_feed_back);
usbd_ept_send(pudev, USBD_AUDIO_FEEDBACK_EPT, audio_struct.audio_feed_back, len);
audio_feedback_state = 1;
}
if( audio_feedback_state++ > (1<<FEEDBACK_REFRESH_TIME) ) //timeout
{
usbd_core_type *pudev = (usbd_core_type *)udev;
int len = audio_codec_spk_feedback(audio_struct.audio_feed_back);
usbd_flush_tx_fifo(pudev, USBD_AUDIO_FEEDBACK_EPT);
usbd_ept_send(pudev, USBD_AUDIO_FEEDBACK_EPT, audio_struct.audio_feed_back, len);
audio_feedback_state = 1;
}
}
#endif
/* ...user code... */
return status;
}
/**
* @brief usb device event handler
* @param udev: usb device core handler type
* @param event: usb device event
* @retval status of usb_sts_type
*/
usb_sts_type class_event_handler(void *udev, usbd_event_type event)
{
usb_sts_type status = USB_OK;
switch(event)
{
case USBD_RESET_EVENT:
/* ...user code... */
break;
case USBD_SUSPEND_EVENT:
audio_struct.spk_alt_setting = 0;
audio_codec_spk_alt_setting(audio_struct.spk_alt_setting);
audio_struct.mic_alt_setting = 0;
audio_codec_mic_alt_setting(audio_struct.spk_alt_setting);
/* ...user code... */
break;
case USBD_WAKEUP_EVENT:
/* ...user code... */
break;
case USBD_INISOINCOM_EVENT:
audio_inisoincom_event(udev);
break;
default:
break;
}
return status;
}
/**
* @brief usb audio in iso incom event
* @param udev: usb device core handler type
* @retval none
*/
void audio_inisoincom_event(void *udev)
{
#if 0
usbd_core_type *pudev = (usbd_core_type *)udev;
uint32_t fnsof = OTG_DEVICE(pudev->usb_reg)->dsts_bit.soffn;
uint32_t epctl_fb = USB_INEPT(pudev->usb_reg, (USBD_AUDIO_FEEDBACK_EPT&0x7F))->diepctl_bit.dpid;
uint32_t epctl_in = USB_INEPT(pudev->usb_reg, (USBD_AUDIO_MIC_IN_EPT&0x7F))->diepctl_bit.dpid;
uint32_t len = 0;
if((fnsof & 0x1) == epctl_fb)
{
USB_INEPT(pudev->usb_reg, (USBD_AUDIO_FEEDBACK_EPT&0x7F))->diepctl_bit.eptdis = 1;
USB_INEPT(pudev->usb_reg, (USBD_AUDIO_FEEDBACK_EPT&0x7F))->diepctl_bit.snak = 1;
usb_flush_tx_fifo(pudev->usb_reg, USBD_AUDIO_FEEDBACK_EPT&0x7F);
usbd_ept_send(pudev, USBD_AUDIO_FEEDBACK_EPT, audio_struct.audio_feed_back, 3);
}
if((fnsof & 0x1) == epctl_in)
{
USB_INEPT(pudev->usb_reg, (USBD_AUDIO_MIC_IN_EPT&0x7F))->diepctl_bit.eptdis = 1;
USB_INEPT(pudev->usb_reg, (USBD_AUDIO_MIC_IN_EPT&0x7F))->diepctl_bit.snak = 1;
usb_flush_tx_fifo(pudev->usb_reg, USBD_AUDIO_MIC_IN_EPT&0x7F);
len = audio_codec_mic_get_data(audio_struct.audio_mic_data);
usbd_ept_send(pudev, USBD_AUDIO_MIC_IN_EPT, audio_struct.audio_mic_data, len);
}
#endif
}
/**
* @brief usb audio request get cur
* @param udev: usb device core handler type
* @param setup: setup class
* @retval none
*/
void audio_req_get_cur(void *udev, usb_setup_type *setup)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
if(HBYTE(setup->wIndex) == AUDIO_SPK_FEATURE_UNIT_ID)
{
if(HBYTE(setup->wValue) == AUDIO_MUTE_CONTROL)
{
audio_struct.g_audio_cur[0] = audio_struct.spk_mute;
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
else
{
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.spk_volume;
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
}
else
{
if(HBYTE(setup->wValue) == AUDIO_MUTE_CONTROL)
{
audio_struct.g_audio_cur[0] = audio_struct.mic_mute;
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
else
{
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.mic_volume;
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
}
}
/**
* @brief usb audio request set cur
* @param udev: usb device core handler type
* @param setup: setup class
* @retval none
*/
void audio_req_set_cur(void *udev, usb_setup_type *setup)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
if(setup->wLength > 0)
{
usbd_ctrl_recv(pudev, audio_struct.g_audio_cur, setup->wLength);
audio_struct.audio_cmd = AUDIO_REQ_SET_CUR;
audio_struct.audio_cmd_len = setup->wLength;
switch(setup->bmRequestType & AUDIO_REQ_CONTROL_MASK)
{
case AUDIO_REQ_CONTROL_INTERFACE:
audio_struct.interface = HBYTE(setup->wIndex);
if(HBYTE(setup->wValue) == AUDIO_MUTE_CONTROL)
{
audio_struct.request_no = AUDIO_MUTE_CONTROL;
}
else
{
audio_struct.request_no = AUDIO_VOLUME_CONTROL;
}
break;
case AUDIO_REQ_CONTROL_ENDPOINT:
audio_struct.enpd = setup->wIndex;
audio_struct.request_no = AUDIO_FREQ_SET_CONTROL;
break;
default:
break;
}
}
}
/**
* @brief usb audio request get min
* @param udev: usb device core handler type
* @param setup: setup class
* @retval none
*/
void audio_req_get_min(void *udev, usb_setup_type *setup)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
if(HBYTE(setup->wIndex) == AUDIO_SPK_FEATURE_UNIT_ID)
{
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.spk_volume_limits[0];
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
else
{
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.mic_volume_limits[0];
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
}
/**
* @brief usb audio request get max
* @param udev: usb device core handler type
* @param setup: setup class
* @retval none
*/
void audio_req_get_max(void *udev, usb_setup_type *setup)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
if(HBYTE(setup->wIndex) == AUDIO_SPK_FEATURE_UNIT_ID)
{
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.spk_volume_limits[1];
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
else
{
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.mic_volume_limits[1];
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
}
/**
* @brief usb audio request get res
* @param udev: usb device core handler type
* @param setup: setup class
* @retval none
*/
void audio_req_get_res(void *udev, usb_setup_type *setup)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
if(HBYTE(setup->wIndex) == AUDIO_SPK_FEATURE_UNIT_ID)
{
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.spk_volume_limits[2];
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
else
{
*((uint16_t *)audio_struct.g_audio_cur) = audio_struct.mic_volume_limits[2];
usbd_ctrl_send(pudev, audio_struct.g_audio_cur, setup->wLength);
}
}
/**
* @brief usb audio set interface
* @param udev: usb device core handler type
* @param setup: setup class
* @retval none
*/
void audio_set_interface(void *udev, usb_setup_type *setup)
{
uint32_t len;
usbd_core_type *pudev = (usbd_core_type *)udev;
if(LBYTE(setup->wIndex) == AUDIO_SPK_INTERFACE_NUMBER)
{
audio_struct.spk_alt_setting = setup->wValue;
audio_codec_spk_alt_setting(audio_struct.spk_alt_setting);
if(audio_struct.spk_alt_setting )
{
usbd_ept_recv(pudev, USBD_AUDIO_SPK_OUT_EPT, audio_struct.audio_spk_data, AUDIO_SPK_OUT_MAXPACKET_SIZE);
}
}
else if(LBYTE(setup->wIndex) == AUDIO_MIC_INTERFACE_NUMBER)
{
audio_struct.mic_alt_setting = setup->wValue;
audio_codec_mic_alt_setting(audio_struct.mic_alt_setting);
if(audio_struct.mic_alt_setting)
{
len = audio_codec_mic_get_data(audio_struct.audio_mic_data);
usbd_ept_send(pudev, USBD_AUDIO_MIC_IN_EPT, audio_struct.audio_mic_data, len);
}
}
}
/**
* @brief usb audio get interface
* @param udev: usb device core handler type
* @param setup: setup class
* @retval none
*/
void audio_get_interface(void *udev, usb_setup_type *setup)
{
usbd_core_type *pudev = (usbd_core_type *)udev;
if(LBYTE(setup->wIndex) == AUDIO_SPK_INTERFACE_NUMBER)
{
usbd_ctrl_send(pudev, (uint8_t *)&audio_struct.spk_alt_setting, 1);
}
else if(LBYTE(setup->wIndex) == AUDIO_MIC_INTERFACE_NUMBER)
{
usbd_ctrl_send(pudev, (uint8_t *)&audio_struct.mic_alt_setting, 1);
}
}
/**
* @brief usb device class send report
* @param udev: to the structure of usbd_core_type
* @param report: report buffer
* @param len: report length
* @retval status of usb_sts_type
*/
usb_sts_type class_send_report(void *udev, uint8_t *report, uint16_t len)
{
usb_sts_type status = USB_OK;
usbd_core_type *pudev = (usbd_core_type *)udev;
if(usbd_connect_state_get(pudev) == USB_CONN_STATE_CONFIGURED)
usbd_ept_send(pudev, USBD_HID_IN_EPT, report, len);
return status;
}
/**
* @brief usb device report function
* @param udev: to the structure of usbd_core_type
* @param report: report buffer
* @param len: report length
* @retval none
*/
void usb_hid_buf_process(void *udev, uint8_t *report, uint16_t len)
{
uint32_t i_index;
usbd_core_type *pudev = (usbd_core_type *)udev;
switch(report[0])
{
case HID_REPORT_ID_2:
if(g_rxhid_buff[1] == 0)
{
at32_led_off(LED2);
}
else
{
at32_led_on(LED2);
}
break;
case HID_REPORT_ID_3:
if(g_rxhid_buff[1] == 0)
{
at32_led_off(LED3);
}
else
{
at32_led_on(LED3);
}
break;
case HID_REPORT_ID_4:
if(g_rxhid_buff[1] == 0)
{
at32_led_off(LED4);
}
else
{
at32_led_on(LED4);
}
break;
case HID_REPORT_ID_6:
for(i_index = 0; i_index < len; i_index ++)
{
g_txhid_buff[i_index] = report[i_index];
}
usbd_ept_send(pudev, USBD_HID_IN_EPT, g_txhid_buff, len);
default:
break;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file audio_class.h
* @version v2.0.4
* @date 2021-12-31
* @brief usb audio class file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AUDIO_CLASS_H
#define __AUDIO_CLASS_H
#ifdef __cplusplus
extern "C" {
#endif
#include "usb_std.h"
#include "usbd_core.h"
#include "audio_conf.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @addtogroup USB_audio_hid_class
* @{
*/
/** @defgroup USB_audio_hid_class_definition
* @{
*/
/**
* @brief endpoint define
*/
#define USBD_AUDIO_MIC_IN_EPT 0x81
#define USBD_AUDIO_SPK_OUT_EPT 0x02
#define USBD_AUDIO_FEEDBACK_EPT 0x83
/**
* @brief usb custom hid use endpoint define
*/
#define USBD_HID_IN_EPT 0x82
#define USBD_HID_OUT_EPT 0x01
/**
* @brief usb custom hid in and out max packet size define
*/
#define USBD_IN_MAXPACKET_SIZE 0x40
#define USBD_OUT_MAXPACKET_SIZE 0x40
/**
* @brief endpoint support max size
*/
#define AUDIO_REMAIN_SIZE 40
#define AUDIO_MIC_IN_MAXPACKET_SIZE (AUDIO_SUPPORT_MAX_FREQ * AUDIO_MIC_CHANEL_NUM * (AUDIO_MIC_DEFAULT_BITW / 8) + AUDIO_REMAIN_SIZE)
#define AUDIO_SPK_OUT_MAXPACKET_SIZE (AUDIO_SUPPORT_MAX_FREQ * AUDIO_SPK_CHANEL_NUM * (AUDIO_SPK_DEFAULT_BITW / 8) + AUDIO_REMAIN_SIZE)
#define AUDIO_FEEDBACK_MAXPACKET_SIZE 0x3
#define FEEDBACK_REFRESH_TIME 0x8
/**
* @brief request type define
*/
#define AUDIO_REQ_CONTROL_INTERFACE 0x01
#define AUDIO_REQ_CONTROL_ENDPOINT 0x02
#define AUDIO_REQ_CONTROL_MASK 0x03
/**
* @brief audio set cur type define
*/
#define AUDIO_MUTE_CONTROL 0x01
#define AUDIO_VOLUME_CONTROL 0x02
#define AUDIO_FREQ_SET_CONTROL 0x03
/**
* @brief audio descriptor type
*/
/**
* @brief audio set cur type define
*/
#define AUDIO_MUTE_CONTROL 0x01
#define AUDIO_VOLUME_CONTROL 0x02
#define AUDIO_FREQ_SET_CONTROL 0x03
/**
* @brief audio descriptor type
*/
#define AUDIO_DESCRIPTOR_TYPE 0x21
#define AUDIO_DESCRIPTOR_SIZE 0x09
/**
* @brief usb custom hid class request code define
*/
#define HID_REQ_SET_PROTOCOL 0x0B
#define HID_REQ_GET_PROTOCOL 0x03
#define HID_REQ_SET_IDLE 0x0A
#define HID_REQ_GET_IDLE 0x02
#define HID_REQ_SET_REPORT 0x09
#define HID_REQ_GET_REPORT 0x01
#define HID_DESCRIPTOR_TYPE 0x21
#define HID_REPORT_DESC 0x22
/**
* @brief usb audio control struct
*/
typedef struct
{
uint8_t enpd;
uint8_t interface;
uint8_t request_no;
uint8_t spk_mute;
uint8_t mic_mute;
uint16_t spk_volume;
uint16_t mic_volume;
uint32_t spk_freq;
uint32_t mic_freq;
uint16_t spk_volume_limits[3]; /*[0] is mininum value, [1] is maxnum value, [2] is volume resolution */
uint16_t mic_volume_limits[3]; /*[0] is mininum value, [1] is maxnum value, [2] is volume resolution */
uint8_t audio_cmd;
uint32_t audio_cmd_len;
uint32_t spk_alt_setting;
uint32_t mic_alt_setting;
uint8_t g_audio_cur[64];
uint8_t audio_spk_data[AUDIO_SPK_OUT_MAXPACKET_SIZE];
uint8_t audio_mic_data[AUDIO_MIC_IN_MAXPACKET_SIZE];
uint8_t audio_feed_back[AUDIO_FEEDBACK_MAXPACKET_SIZE+1];
}usb_audio_type;
extern usbd_class_handler audio_hid_class_handler;
usb_sts_type class_send_report(void *udev, uint8_t *report, uint16_t len);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file audio_desc.c
* @version v2.0.4
* @date 2021-12-31
* @brief usb audio device descriptor
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "usb_std.h"
#include "usbd_sdr.h"
#include "usbd_core.h"
#include "audio_hid_desc.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @defgroup USB_audio_hid_desc
* @brief usb device audio hid descriptor
* @{
*/
/** @defgroup USB_audio_hid_desc_private_functions
* @{
*/
usbd_desc_t *get_device_descriptor(void);
usbd_desc_t *get_device_qualifier(void);
usbd_desc_t *get_device_configuration(void);
usbd_desc_t *get_device_other_speed(void);
usbd_desc_t *get_device_lang_id(void);
usbd_desc_t *get_device_manufacturer_string(void);
usbd_desc_t *get_device_product_string(void);
usbd_desc_t *get_device_serial_string(void);
usbd_desc_t *get_device_interface_string(void);
usbd_desc_t *get_device_config_string(void);
uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
static void get_serial_num(void);
static uint8_t g_usbd_desc_buffer[256];
/**
* @brief device descriptor handler structure
*/
usbd_desc_handler audio_hid_desc_handler =
{
get_device_descriptor,
get_device_qualifier,
get_device_configuration,
get_device_other_speed,
get_device_lang_id,
get_device_manufacturer_string,
get_device_product_string,
get_device_serial_string,
get_device_interface_string,
get_device_config_string,
};
/**
* @brief usb device standard descriptor
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN] ALIGNED_TAIL =
{
USB_DEVICE_DESC_LEN, /* bLength */
USB_DESCIPTOR_TYPE_DEVICE, /* bDescriptorType */
0x00, /* bcdUSB */
0x02,
0x00, /* bDeviceClass */
0x00, /* bDeviceSubClass */
0x00, /* bDeviceProtocol */
USB_MAX_EP0_SIZE, /* bMaxPacketSize */
LBYTE(USBD_VENDOR_ID), /* idVendor */
HBYTE(USBD_VENDOR_ID), /* idVendor */
#if AUDIO_SUPPORT_FEEDBACK
LBYTE(USBD_PRODUCT_ID), /* idProduct */
HBYTE(USBD_PRODUCT_ID), /* idProduct */
#else
LBYTE(USBD_PRODUCT_ID+1), /* idProduct */
HBYTE(USBD_PRODUCT_ID+1), /* idProduct */
#endif
0x00, /* bcdDevice rel. 2.00 */
0x02,
USB_MFC_STRING, /* Index of manufacturer string */
USB_PRODUCT_STRING, /* Index of product string */
USB_SERIAL_STRING, /* Index of serial number string */
0x01 /* bNumConfigurations */
};
/**
* @brief usb configuration standard descriptor
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_usbd_configuration[USBD_CONFIG_DESC_SIZE] ALIGNED_TAIL =
{
USB_DEVICE_CFG_DESC_LEN, /* bLength: configuration descriptor size */
USB_DESCIPTOR_TYPE_CONFIGURATION, /* bDescriptorType: configuration */
LBYTE(USBD_CONFIG_DESC_SIZE), /* wTotalLength: bytes returned */
HBYTE(USBD_CONFIG_DESC_SIZE), /* wTotalLength: bytes returned */
0x1 + AUDIO_INTERFACE_NUM + 0x1, /* bNumInterfaces: n interface */
0x01, /* bConfigurationValue: configuration value */
0x00, /* iConfiguration: index of string descriptor describing
the configuration */
0xC0, /* bmAttributes: self powered */
0x32, /* MaxPower 100 mA: this current is used for detecting vbus */
USB_DEVICE_IF_DESC_LEN, /* bLength: interface descriptor size */
USB_DESCIPTOR_TYPE_INTERFACE, /* bDescriptorType: interface descriptor type */
0x00, /* bInterfaceNumber: number of interface */
0x00, /* bAlternateSetting: alternate set */
0x00, /* bNumEndpoints: number of endpoints */
USB_CLASS_CODE_AUDIO, /* bInterfaceClass: audio class code */
AUDIO_SUBCLASS_AUDIOCONTROL, /* bInterfaceSubClass: audio control */
AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol: undefined */
0x00, /* iInterface: index of string descriptor */
0x08+AUDIO_INTERFACE_NUM, /* bLength: size of this descriptor, in bytes 8+n */
AUDIO_CS_INTERFACE, /* bDescriptorType: cs interface descriptor type */
AUDIO_AC_HEADER, /* bDescriptorSubtype: Header function Descriptor*/
LBYTE(BCD_NUM),
HBYTE(BCD_NUM), /* bcdCDC: audio device class specification release number */
LBYTE(AUDIO_INTERFACE_LEN),
HBYTE(AUDIO_INTERFACE_LEN), /* wTotalLength: total number of bytes returned for the class-specific audio control interface */
AUDIO_INTERFACE_NUM, /* bInClollection: the number of audio streaming */
#if (AUDIO_INTERFACE_NUM == 2) /* two interface */
0x02,
0x01,
#else
0x01,
#endif
/* usb microphone config */
#if (AUDIO_SUPPORT_MIC == 1)
AUDIO_INPUT_TERMINAL_SIZE, /* bLength: descriptor size */
AUDIO_CS_INTERFACE, /* bDescriptorType: configuration */
AUDIO_AC_INPUT_TERMINAL, /* bDescriptorSubtype: input_terminal type*/
AUDIO_MIC_INPUT_TERMINAL_ID, /* bTerminalID: id of this input terminal*/
LBYTE(AUDIO_INPUT_TERMINAL_MICROPHONE),
HBYTE(AUDIO_INPUT_TERMINAL_MICROPHONE),/* wTerminalType: terminal is microphone */
AUDIO_MIC_OUTPUT_TERMINAL_ID, /* bAssocTerminal: no association */
AUDIO_MIC_CHR, /* bNrChannels: two channel */
#if (AUDIO_MIC_CHR == 2)
0x03, /* wChannelConfig: left front and right front */
#endif
#if (AUDIO_MIC_CHR == 1)
0x00, /* wChannelConfig */
#endif
0x00, /* wChannelConfig */
0x00, /* iChannelNames: unused */
0x00, /* iTerminal: unused */
AUDIO_FEATURE_UNIT_SIZE, /* bLength: descriptor size */
AUDIO_CS_INTERFACE, /* bDescriptorType: configuration */
AUDIO_AC_FEATURE_UNIT, /* bDescriptorSubtype: feature unit type*/
AUDIO_MIC_FEATURE_UNIT_ID, /* bUnitID: id of this feature unit */
AUDIO_MIC_INPUT_TERMINAL_ID, /* bSourceID: from input terminal */
0x01, /* bControlSize: 1 byte */
0x01, /* bmaControls0: mute */
0x02, /* bmaControls1: volume */
0x00, /* iFeature: unused */
AUDIO_OUTPUT_TERMINAL_SIZE, /* bLength: descriptor size */
AUDIO_CS_INTERFACE, /* bDescriptorType: configuration */
AUDIO_AC_OUTPUT_TERMINAL, /* bDescriptorSubtype: output_terminal type*/
AUDIO_MIC_OUTPUT_TERMINAL_ID, /* bTerminalID: id of this output terminal*/
LBYTE(AUDIO_TERMINAL_TYPE_STREAMING),
HBYTE(AUDIO_TERMINAL_TYPE_STREAMING), /* wTerminalType: usb streaming */
AUDIO_MIC_INPUT_TERMINAL_ID, /* bAssocTerminal: unused */
AUDIO_MIC_FEATURE_UNIT_ID, /* bSourceID: from feature unit terminal */
0x00, /* iTerminal: unused */
#endif
#if (AUDIO_SUPPORT_SPK == 1)
/* speaker config */
AUDIO_INPUT_TERMINAL_SIZE, /* bLength: descriptor size */
AUDIO_CS_INTERFACE, /* bDescriptorType: configuration */
AUDIO_AC_INPUT_TERMINAL, /* bDescriptorSubtype: input_terminal type*/
AUDIO_SPK_INPUT_TERMINAL_ID, /* bTerminalID: id of this input terminal*/
LBYTE(AUDIO_TERMINAL_TYPE_STREAMING), /* wTerminalType: usb streaming */
HBYTE(AUDIO_TERMINAL_TYPE_STREAMING), /* wTerminalType: usb streaming */
AUDIO_SPK_OUTPUT_TERMINAL_ID, /* bAssocTerminal: no association */
AUDIO_SPK_CHR, /* bNrChannels: two channel */
#if (AUDIO_SPK_CHR == 2)
0x03, /* wChannelConfig: left front and right front */
#endif
#if (AUDIO_SPK_CHR == 1)
0x00, /* wChannelConfig */
#endif
0x00, /* wChannelConfig */
0x00, /* iChannelNames: unused */
0x00, /* iTerminal: unused */
AUDIO_FEATURE_UNIT_SIZE, /* bLength: descriptor size */
AUDIO_CS_INTERFACE, /* bDescriptorType: configuration */
AUDIO_AC_FEATURE_UNIT, /* bDescriptorSubtype: feature unit type*/
AUDIO_SPK_FEATURE_UNIT_ID, /* bUnitID: id of this feature unit */
AUDIO_SPK_INPUT_TERMINAL_ID, /* bSourceID: from input terminal */
0x01, /* bControlSize: 1 byte */
0x01, /* bmaControls0: mute*/
0x02, /* bmaControls1: volume */
0x00, /* iFeature: unused */
AUDIO_OUTPUT_TERMINAL_SIZE, /* bLength: descriptor size */
AUDIO_CS_INTERFACE, /* bDescriptorType: configuration */
AUDIO_AC_OUTPUT_TERMINAL, /* bDescriptorSubtype: output_terminal type*/
AUDIO_SPK_OUTPUT_TERMINAL_ID, /* bTerminalID: id of this output terminal*/
LBYTE(AUDIO_OUTPUT_TERMINAL_SPEAKER), /* wTerminalType: usb speaker */
HBYTE(AUDIO_OUTPUT_TERMINAL_SPEAKER), /* wTerminalType: usb speaker */
AUDIO_SPK_INPUT_TERMINAL_ID, /* bAssocTerminal: unused */
AUDIO_SPK_FEATURE_UNIT_ID, /* bSourceID: from feature unit terminal */
0x00, /* iTerminal: unused */
#endif
#if (AUDIO_SUPPORT_MIC == 1)
/* microphone interface */
0x09, /* bLength: descriptor size */
USB_DESCIPTOR_TYPE_INTERFACE, /* bDescriptorType: interface descriptor type */
AUDIO_MIC_INTERFACE_NUMBER, /* bInterfaceNumber: index of this interface */
0x00, /* bAlternateSetting: index of this setting */
0x00, /* bNumEndpoints: 0 endpoints */
USB_CLASS_CODE_AUDIO, /* bInterfaceClass: audio */
AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubclass: audio streaming */
0x00, /* bInterfaceProtocol: unused */
0x00, /* iInterface: unused */
0x09, /* bLength: descriptor size */
USB_DESCIPTOR_TYPE_INTERFACE, /* bDescriptorType: interface descriptor type */
AUDIO_MIC_INTERFACE_NUMBER, /* bInterfaceNumber: index of this interface */
0x01, /* bAlternateSetting: index of this setting */
0x01, /* bNumEndpoints: 1 endpoints */
USB_CLASS_CODE_AUDIO, /* bInterfaceClass: audio */
AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubclass: audio streaming */
0x00, /* bInterfaceProtocol: unused */
0x00, /* iInterface: unused */
0x07, /* bLength: configuration descriptor size */
AUDIO_CS_INTERFACE, /* bDescriptorType: interface descriptor type */
AUDIO_AS_GENERAL, /* bDescriptorSubtype: general sub type*/
AUDIO_MIC_OUTPUT_TERMINAL_ID, /* bTerminalLink: unit id of the output terminal */
0x01, /* bDelay: interface delay */
0x01, /* wFormatTag: pcm format*/
0x00, /* wFormatTag: pcm format*/
0x08 + AUDIO_MIC_FREQ_SIZE * 3, /* bLength: descriptor size */
AUDIO_CS_INTERFACE, /* bDescriptorType: interface descriptor type */
AUDIO_AS_FORMAT_TYPE, /* bDescriptorSubtype: format subtype */
AUDIO_FORMAT_TYPE_I, /* bFormatType: format type 1 */
AUDIO_MIC_CHR, /* bNrChannels: channel number */
AUDIO_MIC_BITW / 8, /* bSubFrameSize: per audio subframe */
AUDIO_MIC_BITW, /* bBitResolution: n bits per sample */
AUDIO_MIC_FREQ_SIZE, /* bSamFreqType: n frequency supported */
#if (AUDIO_SUPPORT_FREQ_16K == 1)
SAMPLE_FREQ(AT32_AUDIO_FREQ_16K), /* tSamFreq: 16000hz */
#endif
#if (AUDIO_SUPPORT_FREQ_48K == 1)
SAMPLE_FREQ(AT32_AUDIO_FREQ_48K), /* tSamFreq: 48000hz */
#endif
0x09, /* bLength: size of endpoint descriptor in bytes */
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
USBD_AUDIO_MIC_IN_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
USB_EPT_DESC_ISO | USB_ETP_DESC_ASYNC, /* bmAttributes: endpoint attributes */
LBYTE(AUDIO_MIC_IN_MAXPACKET_SIZE),
HBYTE(AUDIO_MIC_IN_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
HID_BINTERVAL_TIME, /* bInterval: interval for polling endpoint for data transfers */
0x00, /* bRefresh: unused */
0x00, /* bSynchAddress: unused */
0x07, /* bLength: size of endpoint descriptor in bytes */
AUDIO_CS_ENDPOINT, /* bDescriptorType: cs endpoint descriptor type */
0x01, /* bDescriptorSubtype: general subtype */
0x01, /* bmAttributes */
0x00, /* bLockDelayUnits: unused */
0x00, /* wLockDelay: unused */
0x00, /* wLockDelay: unused */
#endif
#if (AUDIO_SUPPORT_SPK == 1)
/* speaker interface */
0x09, /* bLength: descriptor size */
USB_DESCIPTOR_TYPE_INTERFACE, /* bDescriptorType: interface descriptor type */
AUDIO_SPK_INTERFACE_NUMBER, /* bInterfaceNumber: index of this interface */
0x00, /* bAlternateSetting: index of this setting */
0x00, /* bNumEndpoints: 0 endpoints */
USB_CLASS_CODE_AUDIO, /* bInterfaceClass: audio */
AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubclass: audio streaming */
0x00, /* bInterfaceProtocol: unused */
0x00, /* iInterface: unused */
0x09, /* bLength: descriptor size */
USB_DESCIPTOR_TYPE_INTERFACE, /* bDescriptorType: interface descriptor type */
AUDIO_SPK_INTERFACE_NUMBER, /* bInterfaceNumber: index of this interface */
0x01, /* bAlternateSetting: index of this setting */
0x01 + AUDIO_SUPPORT_FEEDBACK, /* bNumEndpoints: endpoints */
USB_CLASS_CODE_AUDIO, /* bInterfaceClass: audio */
AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubclass: audio streaming */
0x00, /* bInterfaceProtocol: unused */
0x00, /* iInterface: unused */
0x07, /* bLength: configuration descriptor size */
AUDIO_CS_INTERFACE, /* bDescriptorType: interface descriptor type */
AUDIO_AS_GENERAL, /* bDescriptorSubtype: general sub type*/
AUDIO_SPK_INPUT_TERMINAL_ID, /* bTerminalLink: unit id of the input terminal */
0x01, /* bDelay: interface delay */
0x01, /* wFormatTag: pcm format*/
0x00, /* wFormatTag: pcm format*/
0x08 + AUDIO_SPK_FREQ_SIZE * 3, /* bLength: descriptor size */
AUDIO_CS_INTERFACE, /* bDescriptorType: interface descriptor type */
AUDIO_AS_FORMAT_TYPE, /* bDescriptorSubtype: format subtype */
AUDIO_FORMAT_TYPE_I, /* bFormatType: format type 1 */
AUDIO_SPK_CHR, /* bNrChannels: channel number */
AUDIO_SPK_BITW / 8, /* bSubFrameSize: per audio subframe */
AUDIO_SPK_BITW, /* bBitResolution: n bits per sample */
AUDIO_SPK_FREQ_SIZE, /* bSamFreqType: n frequency supported */
#if (AUDIO_SUPPORT_FREQ_16K == 1)
SAMPLE_FREQ(AT32_AUDIO_FREQ_16K), /* tSamFreq: 16000hz */
#endif
#if (AUDIO_SUPPORT_FREQ_48K == 1)
SAMPLE_FREQ(AT32_AUDIO_FREQ_48K), /* tSamFreq: 48000hz */
#endif
0x09, /* bLength: size of endpoint descriptor in bytes */
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
USBD_AUDIO_SPK_OUT_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
USB_EPT_DESC_ISO | USB_ETP_DESC_ASYNC, /* bmAttributes: endpoint attributes */
LBYTE(AUDIO_SPK_OUT_MAXPACKET_SIZE),
HBYTE(AUDIO_SPK_OUT_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
HID_BINTERVAL_TIME, /* bInterval: interval for polling endpoint for data transfers */
0x00, /* bRefresh: unused */
#if (AUDIO_SUPPORT_FEEDBACK == 1)
USBD_AUDIO_FEEDBACK_EPT, /* bSynchAddress: feedback endpoint */
#else
0x00, /* bSynchAddress: unused */
#endif
0x07, /* bLength: size of endpoint descriptor in bytes */
AUDIO_CS_ENDPOINT, /* bDescriptorType: cs endpoint descriptor type */
0x01, /* bDescriptorSubtype: general subtype */
0x01, /* bmAttributes */
0x00, /* bLockDelayUnits: unused */
0x00, /* wLockDelay: unused */
0x00, /* wLockDelay: unused */
#if (AUDIO_SUPPORT_FEEDBACK == 1)
0x09, /* bLength: size of endpoint descriptor in bytes */
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
USBD_AUDIO_FEEDBACK_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
0x11, /* bmAttributes: endpoint attributes */
LBYTE(AUDIO_FEEDBACK_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
HBYTE(AUDIO_FEEDBACK_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
1, /* bInterval: interval for polling endpoint for data transfers */
FEEDBACK_REFRESH_TIME, /* bRefresh: this field indicates the rate at which an iso syncronization
pipe provides new syncronization feedback data. this rate must be a power of
2, therefore only the power is reported back and the range of this field is from
1(2ms) to 9(512ms) */
0x00, /* bSynchAddress: 0x00*/
#endif
#endif
USB_DEVICE_IF_DESC_LEN, /* bLength: interface descriptor size */
USB_DESCIPTOR_TYPE_INTERFACE, /* bDescriptorType: interface descriptor type */
HID_INTERFACE_NUMBER, /* bInterfaceNumber: number of interface */
0x00, /* bAlternateSetting: alternate set */
0x02, /* bNumEndpoints: number of endpoints */
USB_CLASS_CODE_HID, /* bInterfaceClass: class code hid */
0x00, /* bInterfaceSubClass: subclass code */
0x00, /* bInterfaceProtocol: protocol code */
0x00, /* iInterface: index of string descriptor */
0x09, /* bLength: size of HID descriptor in bytes */
HID_CLASS_DESC_HID, /* bDescriptorType: HID descriptor type */
LBYTE(HID_BCD_NUM),
HBYTE(HID_BCD_NUM), /* bcdHID: HID class specification release number */
0x00, /* bCountryCode: hardware target conutry */
0x01, /* bNumDescriptors: number of HID class descriptor to follow */
HID_CLASS_DESC_REPORT, /* bDescriptorType: report descriptor type */
LBYTE(sizeof(g_usbd_hid_report)),
HBYTE(sizeof(g_usbd_hid_report)), /* wDescriptorLength: total length of reprot descriptor */
USB_DEVICE_EPT_LEN, /* bLength: size of endpoint descriptor in bytes */
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
USBD_HID_IN_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
USB_EPT_DESC_INTERRUPT, /* bmAttributes: endpoint attributes */
LBYTE(USBD_IN_MAXPACKET_SIZE),
HBYTE(USBD_IN_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
HID_BINTERVAL_TIME, /* bInterval: interval for polling endpoint for data transfers */
USB_DEVICE_EPT_LEN, /* bLength: size of endpoint descriptor in bytes */
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
USBD_HID_OUT_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
USB_EPT_DESC_INTERRUPT, /* bmAttributes: endpoint attributes */
LBYTE(USBD_OUT_MAXPACKET_SIZE),
HBYTE(USBD_OUT_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
HID_BINTERVAL_TIME, /* bInterval: interval for polling endpoint for data transfers */
};
/**
* @brief usb hid report descriptor
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_usbd_hid_report[USBD_HID_SIZ_REPORT_DESC] ALIGNED_TAIL =
{
0x06, 0xFF, 0x00, /* USAGE_PAGE(Vendor Page:0xFF00) */
0x09, 0x01, /* USAGE (Demo Kit) */
0xa1, 0x01, /* COLLECTION (Application) */
/* 7 */
/* Led 2 */
0x85, HID_REPORT_ID_2, /* REPORT_ID 2 */
0x09, 0x02, /* USAGE (LED 2) */
0x15, 0x00, /* LOGICAL_MINIMUM (0) */
0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
0x75, 0x08, /* REPORT_SIZE (8) */
0x95, 0x3F, /* REPORT_COUNT (1) */
0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */
0x85, 0x02, /* REPORT_ID (2) */
0x09, 0x02, /* USAGE (LED 2) */
0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */
/* 27 */
/* Led 3 */
0x85, HID_REPORT_ID_3, /* REPORT_ID (3) */
0x09, 0x03, /* USAGE (LED 3) */
0x15, 0x00, /* LOGICAL_MINIMUM (0) */
0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
0x75, 0x08, /* REPORT_SIZE (8) */
0x95, 0x3F, /* REPORT_COUNT (1) */
0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */
0x85, 0x03, /* REPORT_ID (3) */
0x09, 0x03, /* USAGE (LED 3) */
0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */
/* 47 */
/* Led 4 */
0x85, HID_REPORT_ID_4, /* REPORT_ID 4) */
0x09, 0x04, /* USAGE (LED 4) */
0x15, 0x00, /* LOGICAL_MINIMUM (0) */
0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
0x75, 0x08, /* REPORT_SIZE (8) */
0x95, 0x3F, /* REPORT_COUNT (1) */
0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */
0x85, 0x04, /* REPORT_ID (4) */
0x09, 0x04, /* USAGE (LED 4) */
0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */
/* 67 */
/* key Push Button */
0x85, HID_REPORT_ID_5, /* REPORT_ID (5) */
0x09, 0x05, /* USAGE (Push Button) */
0x15, 0x00, /* LOGICAL_MINIMUM (0) */
0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
0x75, 0x01, /* REPORT_SIZE (1) */
0x81, 0x82, /* INPUT (Data,Var,Abs,Vol) */
0x09, 0x05, /* USAGE (Push Button) */
0x75, 0x01, /* REPORT_SIZE (1) */
0xb1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */
0x75, 0x07, /* REPORT_SIZE (7) */
0x81, 0x83, /* INPUT (Cnst,Var,Abs,Vol) */
0x85, 0x05, /* REPORT_ID (5) */
0x75, 0x07, /* REPORT_SIZE (7) */
0xb1, 0x83, /* FEATURE (Cnst,Var,Abs,Vol) */
/* 95 */
/* Data OUT */
0x85, HID_REPORT_ID_6, /* REPORT_ID (0xF0) */
0x09, 0x06, /* USAGE */
0x15, 0x00, /* LOGICAL_MINIMUM (0) */
0x26, 0x00,0xff, /* LOGICAL_MAXIMUM (255) */
0x75, 0x08, /* REPORT_SIZE (8) */
0x95, 0x3F, /* REPORT_COUNT (64) */
0x91, 0x02, /* OUTPUT(Data,Var,Abs,Vol) */
/* 110 */
/* Data IN */
0x85, HID_REPORT_ID_6, /* REPORT_ID (0xF0) */
0x09, 0x07, /* USAGE */
0x15, 0x00, /* LOGICAL_MINIMUM (0) */
0x26, 0x00,0xff, /* LOGICAL_MAXIMUM (255) */
0x75, 0x08, /* REPORT_SIZE (8) */
0x95, 0x3F, /* REPORT_COUNT (64) */
0x81, 0x82, /* INPUT(Data,Var,Abs,Vol) */
/* 125 */
0xc0 /* END_COLLECTION */
};
/**
* @brief usb hid descriptor
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_hid_usb_desc[9] ALIGNED_TAIL =
{
0x09, /* bLength: size of HID descriptor in bytes */
HID_CLASS_DESC_HID, /* bDescriptorType: HID descriptor type */
LBYTE(HID_BCD_NUM),
HBYTE(HID_BCD_NUM), /* bcdHID: HID class specification release number */
0x00, /* bCountryCode: hardware target conutry */
0x01, /* bNumDescriptors: number of HID class descriptor to follow */
HID_CLASS_DESC_REPORT, /* bDescriptorType: report descriptor type */
LBYTE(sizeof(g_usbd_hid_report)),
HBYTE(sizeof(g_usbd_hid_report)), /* wDescriptorLength: total length of reprot descriptor */
};
/**
* @brief usb string lang id
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_string_lang_id[USBD_SIZ_STRING_LANGID] ALIGNED_TAIL =
{
USBD_SIZ_STRING_LANGID,
USB_DESCIPTOR_TYPE_STRING,
0x09,
0x04,
};
/**
* @brief usb string serial
*/
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_string_serial[USBD_SIZ_STRING_SERIAL] ALIGNED_TAIL =
{
USBD_SIZ_STRING_SERIAL,
USB_DESCIPTOR_TYPE_STRING,
};
/* device descriptor */
usbd_desc_t device_descriptor =
{
USB_DEVICE_DESC_LEN,
g_usbd_descriptor
};
/* config descriptor */
usbd_desc_t config_descriptor =
{
USBD_CONFIG_DESC_SIZE,
g_usbd_configuration
};
/* langid descriptor */
usbd_desc_t langid_descriptor =
{
USBD_SIZ_STRING_LANGID,
g_string_lang_id
};
/* serial descriptor */
usbd_desc_t serial_descriptor =
{
USBD_SIZ_STRING_SERIAL,
g_string_serial
};
usbd_desc_t vp_desc;
/**
* @brief standard usb unicode convert
* @param string: source string
* @param unicode_buf: unicode buffer
* @retval length
*/
uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf)
{
uint16_t str_len = 0, id_pos = 2;
uint8_t *tmp_str = string;
while(*tmp_str != '\0')
{
str_len ++;
unicode_buf[id_pos ++] = *tmp_str ++;
unicode_buf[id_pos ++] = 0x00;
}
str_len = str_len * 2 + 2;
unicode_buf[0] = str_len;
unicode_buf[1] = USB_DESCIPTOR_TYPE_STRING;
return str_len;
}
/**
* @brief usb int convert to unicode
* @param value: int value
* @param pbus: unicode buffer
* @param len: length
* @retval none
*/
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len)
{
uint8_t idx = 0;
for( idx = 0 ; idx < len ; idx ++)
{
if( ((value >> 28)) < 0xA )
{
pbuf[2 * idx] = (value >> 28) + '0';
}
else
{
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
}
value = value << 4;
pbuf[2 * idx + 1] = 0;
}
}
/**
* @brief usb get serial number
* @param none
* @retval none
*/
static void get_serial_num(void)
{
uint32_t serial0, serial1, serial2;
serial0 = *(uint32_t*)MCU_ID1;
serial1 = *(uint32_t*)MCU_ID2;
serial2 = *(uint32_t*)MCU_ID3;
serial0 += serial2;
if (serial0 != 0)
{
usbd_int_to_unicode (serial0, &g_string_serial[2] ,8);
usbd_int_to_unicode (serial1, &g_string_serial[18] ,4);
}
}
/**
* @brief get device descriptor
* @param none
* @retval usbd_desc
*/
usbd_desc_t *get_device_descriptor(void)
{
return &device_descriptor;
}
/**
* @brief get device qualifier
* @param none
* @retval usbd_desc
*/
usbd_desc_t * get_device_qualifier(void)
{
return NULL;
}
/**
* @brief get config descriptor
* @param none
* @retval usbd_desc
*/
usbd_desc_t *get_device_configuration(void)
{
return &config_descriptor;
}
/**
* @brief get other speed descriptor
* @param none
* @retval usbd_desc
*/
usbd_desc_t *get_device_other_speed(void)
{
return NULL;
}
/**
* @brief get lang id descriptor
* @param none
* @retval usbd_desc
*/
usbd_desc_t *get_device_lang_id(void)
{
return &langid_descriptor;
}
/**
* @brief get manufacturer descriptor
* @param none
* @retval usbd_desc
*/
usbd_desc_t *get_device_manufacturer_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_DESC_MANUFACTURER_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @brief get product descriptor
* @param none
* @retval usbd_desc
*/
usbd_desc_t *get_device_product_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_DESC_PRODUCT_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @brief get serial descriptor
* @param none
* @retval usbd_desc
*/
usbd_desc_t *get_device_serial_string(void)
{
get_serial_num();
return &serial_descriptor;
}
/**
* @brief get interface descriptor
* @param none
* @retval usbd_desc
*/
usbd_desc_t *get_device_interface_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_DESC_INTERFACE_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @brief get device config descriptor
* @param none
* @retval usbd_desc
*/
usbd_desc_t *get_device_config_string(void)
{
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_DESC_CONFIGURATION_STRING, g_usbd_desc_buffer);
vp_desc.descriptor = g_usbd_desc_buffer;
return &vp_desc;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

266
middlewares/usbd_class/audio_hid/audio_hid_desc.h Normal file
View File

@ -0,0 +1,266 @@
/**
**************************************************************************
* @file audio_desc.h
* @version v2.0.4
* @date 2021-12-31
* @brief usb audio descriptor header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AUDIO_DESC_H
#define __AUDIO_DESC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "audio_hid_class.h"
#include "usbd_core.h"
#include "audio_conf.h"
/** @addtogroup AT32F435_437_middlewares_usbd_class
* @{
*/
/** @addtogroup USB_audio_hid_desc
* @{
*/
/** @defgroup USB_audio_hid_desc_definition
* @{
*/
#define BCD_NUM 0x0100
#define USBD_VENDOR_ID 0x2E3C
#define USBD_PRODUCT_ID 0x5555
#define USBD_SIZ_STRING_LANGID 4
#define USBD_SIZ_STRING_SERIAL 0x1A
#define USBD_DESC_MANUFACTURER_STRING "Artery"
#define USBD_DESC_PRODUCT_STRING "AT32 Audio"
#define USBD_DESC_CONFIGURATION_STRING "Audio Config"
#define USBD_DESC_INTERFACE_STRING "Audio Interface"
/**
* @brief audio interface subclass codes
*/
#define AUDIO_SUBCLASS_UNDEFINED 0x00
#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01
#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02
#define AUDIO_SUBCLASS_MIDISTREMING 0x03
/**
* @brief audio class-specific descriptor types
*/
#define AUDIO_CS_INTERFACE 0x24
#define AUDIO_CS_ENDPOINT 0x25
#define AUDIO_CS_STRING 0x23
#define AUDIO_CS_CONFIGURATION 0x22
#define AUDIO_CS_DEVICE 0x21
#define AUDIO_CS_UNDEFINED 0x20
/**
* @brief audio interface protocol codes
*/
#define AUDIO_PROTOCOL_UNDEFINED 0x00
/**
* @brief audio class-specific ac interface descriptor subtypes
*/
#define AUDIO_AC_DESCRIPTOR_UNDEFINED 0x00
#define AUDIO_AC_HEADER 0x01
#define AUDIO_AC_INPUT_TERMINAL 0x02
#define AUDIO_AC_OUTPUT_TERMINAL 0x03
#define AUDIO_AC_MIXER_UNIT 0x04
#define AUDIO_AC_SELECTOR_UNIT 0x05
#define AUDIO_AC_FEATURE_UNIT 0x06
#define AUDIO_AC_PROCESSING_UNIT 0x07
#define AUDIO_AC_EXTENSION_UNIT 0x08
/**
* @brief audio class-specific as interface descriptor subtypes
*/
#define AUDIO_AS_DESCRIPTOR_UNDEFINED 0x00
#define AUDIO_AS_GENERAL 0x01
#define AUDIO_AS_FORMAT_TYPE 0x02
#define AUDIO_AS_FORMAT_SPECIFIC 0x03
/**
* @brief audio class-specific request codes
*/
#define AUDIO_REQUEST_CODE_UNDEFINED 0x00
#define AUDIO_REQ_SET_CUR 0x01
#define AUDIO_REQ_GET_CUR 0x81
#define AUDIO_REQ_SET_MIN 0x02
#define AUDIO_REQ_GET_MIN 0x82
#define AUDIO_REQ_SET_MAX 0x03
#define AUDIO_REQ_GET_MAX 0x83
#define AUDIO_REQ_SET_RES 0x04
#define AUDIO_REQ_GET_RES 0x84
#define AUDIO_REQ_SET_MEM 0x05
#define AUDIO_REQ_GET_MEM 0x85
#define AUDIO_REQ_GET_STAT 0xFF
/**
* @brief audio feature unit control selectors
*/
#define AUDIO_FU_CONTROL_UNDEFINED 0x00
#define AUDIO_FU_MUTE_CONTROL 0x01
#define AUDIO_FU_VOLUME_CONTROL 0x02
#define AUDIO_FU_BASS_CONTROL 0x03
#define AUDIO_FU_MID_CONTROL 0x04
#define AUDIO_FU_TREBLE_CONTROL 0x05
/**
* @brief audio terminal type
*/
#define AUDIO_TERMINAL_TYPE_UNDEFINED 0x0100
#define AUDIO_TERMINAL_TYPE_STREAMING 0x0101
#define AUDIO_TERMINAL_TYPE_VENDOR 0x01FF
#define AUDIO_INPUT_TERMINAL_UNDEFINED 0x0200
#define AUDIO_INPUT_TERMINAL_MICROPHONE 0x0201
#define AUDIO_OUTPUT_TERMINAL_UNDEFINED 0x0300
#define AUDIO_OUTPUT_TERMINAL_SPEAKER 0x0301
/**
* @brief audio format type 1
*/
#define AUDIO_FORMAT_TYPE_I 0x01
/**
* @brief audio interface config
*/
#define AUDIO_INTERFACE_NUM (AUDIO_SUPPORT_SPK + AUDIO_SUPPORT_MIC)
#define AUDIO_INTERFACE_LEN ((0x08 + AUDIO_INTERFACE_NUM) + AUDIO_INTERFACE_NUM * 0x1E)
#define AUDIO_MIC_INTERFACE 0x01
#define AUDIO_SPK_INTERFACE 0x02
/**
* @brief audio interface descriptor size define
*/
#define AUDIO_INPUT_TERMINAL_SIZE 0x0C
#define AUDIO_OUTPUT_TERMINAL_SIZE 0x09
#define AUDIO_FEATURE_UNIT_SIZE 0x09
/**
* @brief audio terminal id define
*/
#define AUDIO_MIC_INPUT_TERMINAL_ID 0x01
#define AUDIO_MIC_FEATURE_UNIT_ID 0x02
#define AUDIO_MIC_OUTPUT_TERMINAL_ID 0x03
#define AUDIO_SPK_INPUT_TERMINAL_ID 0x04
#define AUDIO_SPK_FEATURE_UNIT_ID 0x05
#define AUDIO_SPK_OUTPUT_TERMINAL_ID 0x06
/**
* @brief audio interface number
*/
#define AUDIO_MIC_INTERFACE_NUMBER 0x01
#if (AUDIO_SUPPORT_MIC == 1)
#define AUDIO_SPK_INTERFACE_NUMBER 0x02
#else
#define AUDIO_SPK_INTERFACE_NUMBER 0x01
#endif
#define HID_INTERFACE_NUMBER 0x03
/**
* @brief audio support freq
*/
#define AT32_AUDIO_FREQ_16K 16000
#define AT32_AUDIO_FREQ_48K 48000
/**
* @brief audio microphone freq and channel config
*/
#define AUDIO_MIC_FREQ_SIZE (AUDIO_SUPPORT_FREQ)
#define AUDIO_MIC_CHR AUDIO_MIC_CHANEL_NUM
#define AUDIO_MIC_BITW (AUDIO_MIC_DEFAULT_BITW)
/**
* @brief audio speaker freq and channel config
*/
#define AUDIO_SPK_FREQ_SIZE (AUDIO_SUPPORT_FREQ)
#define AUDIO_SPK_CHR AUDIO_SPK_CHANEL_NUM
#define AUDIO_SPK_BITW (AUDIO_SPK_DEFAULT_BITW)
#define HID_BINTERVAL_TIME 0x01
/**
* @brief usb bcd number define
*/
#define HID_BCD_NUM 0x0110
/**
* @brief usb hid class descriptor define
*/
#define HID_CLASS_DESC_HID 0x21
#define HID_CLASS_DESC_REPORT 0x22
#define HID_CLASS_DESC_PHYSICAL 0x23
/**
* @brief usb hid report id define
*/
#define HID_REPORT_ID_1 0x01
#define HID_REPORT_ID_2 0x02
#define HID_REPORT_ID_3 0x03
#define HID_REPORT_ID_4 0x04
#define HID_REPORT_ID_5 0x05
#define HID_REPORT_ID_6 0xF0
#define USBD_HID_DESC_SIZE 32
#define USBD_CONFIG_DESC_SIZE ( 0x12 + AUDIO_INTERFACE_LEN + \
+ (0x31 + AUDIO_SPK_FREQ_SIZE * 3) \
+ (0x31 + AUDIO_MIC_FREQ_SIZE * 3) \
+ (9 * AUDIO_SUPPORT_FEEDBACK) \
+ USBD_HID_DESC_SIZE)
#define USBD_HID_SIZ_REPORT_DESC 126
#define SAMPLE_FREQ(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16))
#define MCU_ID1 (0x1FFFF7E8)
#define MCU_ID2 (0x1FFFF7EC)
#define MCU_ID3 (0x1FFFF7F0)
extern uint8_t g_usbd_hid_report[USBD_HID_SIZ_REPORT_DESC];
extern uint8_t g_hid_usb_desc[9];
extern uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN];
extern uint8_t g_usbd_configuration[USBD_CONFIG_DESC_SIZE];
extern usbd_desc_handler audio_hid_desc_handler;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

4
middlewares/usbd_class/cdc/cdc_class.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file cdc_class.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb cdc class type
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/cdc/cdc_class.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file cdc_class.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb cdc class file
**************************************************************************
* Copyright notice & Disclaimer

24
middlewares/usbd_class/cdc/cdc_desc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file cdc_desc.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb cdc device descriptor
**************************************************************************
* Copyright notice & Disclaimer
@ -78,7 +78,10 @@ usbd_desc_handler desc_handler =
/**
* @brief usb device standard descriptor
*/
uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN] =
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN] ALIGNED_TAIL =
{
USB_DEVICE_DESC_LEN, /* bLength */
USB_DESCIPTOR_TYPE_DEVICE, /* bDescriptorType */
@ -103,7 +106,10 @@ uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN] =
/**
* @brief usb configuration standard descriptor
*/
uint8_t g_usbd_configuration[USBD_CONFIG_DESC_SIZE] =
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_usbd_configuration[USBD_CONFIG_DESC_SIZE] ALIGNED_TAIL =
{
USB_DEVICE_CFG_DESC_LEN, /* bLength: configuration descriptor size */
USB_DESCIPTOR_TYPE_CONFIGURATION, /* bDescriptorType: configuration */
@ -188,7 +194,10 @@ uint8_t g_usbd_configuration[USBD_CONFIG_DESC_SIZE] =
/**
* @brief usb string lang id
*/
uint8_t g_string_lang_id[USBD_SIZ_STRING_LANGID] =
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_string_lang_id[USBD_SIZ_STRING_LANGID] ALIGNED_TAIL =
{
USBD_SIZ_STRING_LANGID,
USB_DESCIPTOR_TYPE_STRING,
@ -199,7 +208,10 @@ uint8_t g_string_lang_id[USBD_SIZ_STRING_LANGID] =
/**
* @brief usb string serial
*/
uint8_t g_string_serial[USBD_SIZ_STRING_SERIAL] =
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_string_serial[USBD_SIZ_STRING_SERIAL] ALIGNED_TAIL =
{
USBD_SIZ_STRING_SERIAL,
USB_DESCIPTOR_TYPE_STRING,

4
middlewares/usbd_class/cdc/cdc_desc.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file cdc_desc.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb cdc descriptor header file
**************************************************************************
* Copyright notice & Disclaimer

6
middlewares/usbd_class/composite_cdc_keyboard/cdc_keyboard_class.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file cdc_keyboard_class.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb cdc and keyboard class type
**************************************************************************
* Copyright notice & Disclaimer
@ -66,7 +66,7 @@ static uint8_t g_req;
static uint16_t g_len, g_rxlen;
__IO uint8_t g_tx_completed = 1, g_rx_completed = 0;
uint8_t g_keyboard_tx_completed = 0;
__IO uint8_t g_keyboard_tx_completed = 0;
#define SHIFT 0x80
const unsigned char _asciimap[128] =

6
middlewares/usbd_class/composite_cdc_keyboard/cdc_keyboard_class.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file cdc_keyboard_class.h
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb cdc and keyboard class file
**************************************************************************
* Copyright notice & Disclaimer
@ -106,7 +106,7 @@ typedef struct
* @{
*/
extern usbd_class_handler cdc_keyboard_class_handler;
extern uint8_t g_keyboard_tx_completed;
extern __IO uint8_t g_keyboard_tx_completed;
uint16_t usb_vcp_get_rxdata(void *udev, uint8_t *recv_data);
error_status usb_vcp_send_data(void *udev, uint8_t *send_data, uint16_t len);
usb_sts_type class_send_report(void *udev, uint8_t *report, uint16_t len);

34
middlewares/usbd_class/composite_cdc_keyboard/cdc_keyboard_desc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file cdc_keyboard_desc.c
* @version v2.0.2
* @date 2021-11-26
* @version v2.0.4
* @date 2021-12-31
* @brief usb cdc and keyboard device descriptor
**************************************************************************
* Copyright notice & Disclaimer
@ -76,7 +76,10 @@ usbd_desc_handler cdc_keyboard_desc_handler =
/**
* @brief usb device standard descriptor
*/
uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN] =
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN] ALIGNED_TAIL =
{
USB_DEVICE_DESC_LEN, /* bLength */
USB_DESCIPTOR_TYPE_DEVICE, /* bDescriptorType */
@ -101,7 +104,10 @@ uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN] =
/**
* @brief usb configuration standard descriptor
*/
uint8_t g_usbd_configuration[USBD_CONFIG_DESC_SIZE] =
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_usbd_configuration[USBD_CONFIG_DESC_SIZE] ALIGNED_TAIL =
{
USB_DEVICE_CFG_DESC_LEN, /* bLength: configuration descriptor size */
USB_DESCIPTOR_TYPE_CONFIGURATION, /* bDescriptorType: configuration */
@ -232,7 +238,10 @@ uint8_t g_usbd_configuration[USBD_CONFIG_DESC_SIZE] =
/**
* @brief usb hid descriptor
*/
uint8_t g_hid_usb_desc[9] =
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_hid_usb_desc[9] ALIGNED_TAIL =
{
0x09, /* bLength: size of HID descriptor in bytes */
HID_CLASS_DESC_HID, /* bDescriptorType: HID descriptor type */
@ -248,7 +257,10 @@ uint8_t g_hid_usb_desc[9] =
/**
* @brief usb hid keyboard report descriptor
*/
uint8_t g_usbd_hid_report[USBD_HID_SIZ_REPORT_DESC] =
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_usbd_hid_report[USBD_HID_SIZ_REPORT_DESC] ALIGNED_TAIL =
{
0x05, 0x01, // USAGE_PAGE (Generic Desktop)
0x09, 0x06, // USAGE (Keyboard)
@ -286,7 +298,10 @@ uint8_t g_usbd_hid_report[USBD_HID_SIZ_REPORT_DESC] =
/**
* @brief usb string lang id
*/
uint8_t g_string_lang_id[USBD_SIZ_STRING_LANGID] =
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_string_lang_id[USBD_SIZ_STRING_LANGID] ALIGNED_TAIL =
{
USBD_SIZ_STRING_LANGID,
USB_DESCIPTOR_TYPE_STRING,
@ -297,7 +312,10 @@ uint8_t g_string_lang_id[USBD_SIZ_STRING_LANGID] =
/**
* @brief usb string serial
*/
uint8_t g_string_serial[USBD_SIZ_STRING_SERIAL] =
#if defined ( __ICCARM__ ) /* iar compiler */
#pragma data_alignment=4
#endif
ALIGNED_HEAD uint8_t g_string_serial[USBD_SIZ_STRING_SERIAL] ALIGNED_TAIL =
{
USBD_SIZ_STRING_SERIAL,
USB_DESCIPTOR_TYPE_STRING,

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