project
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https://www.nxp.com/files-static/training_pdf/FTF/2012/americas/WBNR_FTF12_AUT_F0098.pdf has many cool pictures explaining the whole thing.
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https://www.nxp.com/docs/en/application-note/AN4849.pdf is literally a complete example of a four cylinder internal combustion engine (ICE) injector drive.
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PT2001 has four independent microcores - four "threads" of execution.
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One thread has to be controlling variable frequency modulation (VFM) DC-to-DC converter, whatever it means.
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Two more threads are running two banks of two injectors each.
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Each injector has it's own low-side driver.
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Each bank/pair of injectors share a "boosting" - i.e. high-voltage opening high-side driver, and a "holding" - i.e normal battery voltage high-side driver. (page 59)
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bin
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sample_code/*
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!sample_code/PT2001_dram.h
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!sample_code/PT2001_LoadData.c
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!sample_code/PT2001_LoadData.h
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CSV Files
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Registers/*.hex
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*.txt
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*.vsdx
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*.def.hex
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<Actuator name="DCDC_Current" type="DcdcConverterSolenoid">
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<Resistance>10</Resistance>
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<Inductance>10</Inductance>
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<RSense>10</RSense>
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<CurrentFeedback>CurFbk4</CurrentFeedback>
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<FeedBackSource>Form</FeedBackSource>
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<OutputUsed number="1">
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<Output>Ls7Command</Output>
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</OutputUsed>
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<VoltageLoad>
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<Voltage>-52</Voltage>
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<Voltage>13</Voltage>
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</VoltageLoad>
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<LinkedActuator>DCDC_Voltage</LinkedActuator>
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<BoostFeedback>None</BoostFeedback>
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</Actuator>
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<Actuator name="DCDC_Voltage" type="DcdcConverterCapacitor">
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<Resistance>30</Resistance>
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<Inductance>1000</Inductance>
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<RSense>80</RSense>
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<CurrentFeedback>
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</CurrentFeedback>
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<FeedBackSource>Form</FeedBackSource>
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<OutputUsed number="1">
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<Output>Ls7Command</Output>
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</OutputUsed>
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<VoltageLoad>
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<Voltage>-1000</Voltage>
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<Voltage>13</Voltage>
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</VoltageLoad>
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<LinkedActuator>DCDC_Current</LinkedActuator>
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<BoostFeedback>VboostDiv</BoostFeedback>
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</Actuator>
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<Actuator name="Inj1" type="BoostParallelSolenoid2">
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<Resistance>1000</Resistance>
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<Inductance>500</Inductance>
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<RSense>10</RSense>
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<CurrentFeedback>CurFbk1</CurrentFeedback>
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<FeedBackSource>Form</FeedBackSource>
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<OutputUsed number="3">
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<Output>Hs1Command</Output>
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<Output>Ls1Command</Output>
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<Output>Hs2Command</Output>
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</OutputUsed>
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<VoltageLoad>
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<Voltage>-66</Voltage>
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<Voltage>-1</Voltage>
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<Voltage>-1</Voltage>
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<Voltage>65</Voltage>
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<Voltage>-1</Voltage>
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<Voltage>-1</Voltage>
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<Voltage>13</Voltage>
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<Voltage>65</Voltage>
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</VoltageLoad>
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<BoostFeedback>None</BoostFeedback>
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</Actuator>
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<LoadDefault xmlns="http://tempuri.org/AutoLoad.xsd">
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<MicroCodesReload ch1="True" ch2="True" />
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<DPRamsReload ch1="True" ch2="True" />
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<ChannelParametersReload ch1="True" ch2="True" />
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<MainConfigurationReload reload="True" />
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<DiagnosisConfigurationReload reload="True" />
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<CrossbarConfigurationReload reload="True" />
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<StimulusReload reload="True" />
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<ActuatorReload reload="True" />
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<FeedbackReload reload="True" />
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<GraphicsReload reload="True" />
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<ForceFlashEnable ch1="True" ch2="True" />
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</LoadDefault>
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<VoltageFeedbacks>
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<Transition threshold="False" type="2">
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<Input>FeedbackHs1Vds</Input>
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<Output>Hs1Command</Output>
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<SourceShared level="True">Hs2Command</SourceShared>
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<AboveHigh>
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<Value>False</Value>
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<Delay>500 ns</Delay>
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</AboveHigh>
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<AboveLow>
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<Value>True</Value>
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<Delay>500 ns</Delay>
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</AboveLow>
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</Transition>
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<Transition threshold="True" type="2">
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<Input>FeedbackHs1Vsrc</Input>
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<Output>Hs1Command</Output>
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<SourceShared level="True">Hs2Command</SourceShared>
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<ActuatorNumber>-1</ActuatorNumber>
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<Current>0</Current>
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<AboveHigh>
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<Value>True</Value>
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<Delay>500 ns</Delay>
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</AboveHigh>
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<AboveLow>
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<Value>False</Value>
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<Delay>500 ns</Delay>
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</AboveLow>
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<BelowHigh>
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<Value>True</Value>
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<Delay>500 ns</Delay>
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</BelowHigh>
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<BelowLow>
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<Value>True</Value>
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<Delay>500 ns</Delay>
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</BelowLow>
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</Transition>
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<Transition threshold="False" type="2">
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<Input>FeedbackHs2Vds</Input>
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<Output>Hs2Command</Output>
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<SourceShared level="False">Hs1Command</SourceShared>
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<AboveHigh>
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<Value>False</Value>
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<Delay>500 ns</Delay>
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</AboveHigh>
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<AboveLow>
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<Value>True</Value>
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<Delay>500 ns</Delay>
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</AboveLow>
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</Transition>
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<Transition threshold="True" type="2">
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<Input>FeedbackHs2Vsrc</Input>
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<Output>Hs2Command</Output>
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<SourceShared level="False">Hs1Command</SourceShared>
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<ActuatorNumber>-1</ActuatorNumber>
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<Current>0</Current>
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<AboveHigh>
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<Value>True</Value>
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<Delay>500 ns</Delay>
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</AboveHigh>
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<AboveLow>
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<Value>False</Value>
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<Delay>500 ns</Delay>
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</AboveLow>
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<BelowHigh>
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<Value>True</Value>
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<Delay>500 ns</Delay>
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</BelowHigh>
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<BelowLow>
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<Value>True</Value>
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<Delay>500 ns</Delay>
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</BelowLow>
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</Transition>
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<Transition threshold="False" type="1">
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<Input>FeedbackLs1Vds</Input>
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<Output>Ls1Command</Output>
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<AboveHigh>
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<Value>False</Value>
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<Delay>500 ns</Delay>
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</AboveHigh>
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<AboveLow>
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<Value>True</Value>
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<Delay>500 ns</Delay>
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</AboveLow>
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</Transition>
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<Transition threshold="False" type="2">
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<Input>FeedbackHs2VdsVbat</Input>
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<Output>Hs2Command</Output>
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<SourceShared level="False">Hs1Command</SourceShared>
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<AboveHigh>
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<Value>False</Value>
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<Delay>500 ns</Delay>
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</AboveHigh>
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<AboveLow>
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<Value>True</Value>
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<Delay>500 ns</Delay>
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</AboveLow>
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</Transition>
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</VoltageFeedbacks>
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<Waves>
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<Wave>
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<Name>Start1</Name>
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<Path>
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<PathElement>PT2001</PathElement>
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</Path>
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<Ordinal>6</Ordinal>
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<Direction>Input</Direction>
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<Radix>Decimal</Radix>
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</Wave>
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<Wave>
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<Name>Flag2Out</Name>
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<Path>
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<PathElement>PT2001</PathElement>
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</Path>
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<Ordinal>0</Ordinal>
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<Direction>Output</Direction>
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<Radix>Decimal</Radix>
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</Wave>
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<Wave>
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<Name>Flag1Out</Name>
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<Path>
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<PathElement>PT2001</PathElement>
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</Path>
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<Ordinal>1</Ordinal>
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<Direction>Output</Direction>
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<Radix>Decimal</Radix>
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</Wave>
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<Wave>
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<Name>Flag0Out</Name>
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<Path>
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<PathElement>PT2001</PathElement>
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</Path>
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<Ordinal>2</Ordinal>
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<Direction>Output</Direction>
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<Radix>Decimal</Radix>
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</Wave>
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<Wave>
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<Name>Dac1</Name>
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<Path>
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<PathElement>PT2001</PathElement>
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</Path>
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<Ordinal>43</Ordinal>
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<Direction>Output</Direction>
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<Radix>Decimal</Radix>
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</Wave>
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<Wave>
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<Name>Hs1Command</Name>
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<Path>
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<PathElement>PT2001</PathElement>
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</Path>
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<Ordinal>4</Ordinal>
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<Direction>Output</Direction>
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<Radix>Decimal</Radix>
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</Wave>
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<Wave>
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<Name>Hs2Command</Name>
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<Path>
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<PathElement>PT2001</PathElement>
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</Path>
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<Ordinal>5</Ordinal>
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<Direction>Output</Direction>
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<Radix>Decimal</Radix>
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</Wave>
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<Wave>
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<Name>Ls1Command</Name>
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<Path>
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<PathElement>PT2001</PathElement>
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</Path>
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<Ordinal>9</Ordinal>
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<Direction>Output</Direction>
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<Radix>Decimal</Radix>
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</Wave>
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<Wave>
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<Name>Cnt1</Name>
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<Path>
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<PathElement>PT2001</PathElement>
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<PathElement>Injection Channel 1</PathElement>
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<PathElement>ChSequencers</PathElement>
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<PathElement>MicroMachineSeq0</PathElement>
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<PathElement>Counters</PathElement>
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</Path>
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<Ordinal>0</Ordinal>
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<Direction>Output</Direction>
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<Radix>Decimal</Radix>
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</Wave>
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<Wave>
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<Name>Cnt2</Name>
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<Path>
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<PathElement>PT2001</PathElement>
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<PathElement>Injection Channel 1</PathElement>
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<PathElement>ChSequencers</PathElement>
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<PathElement>MicroMachineSeq0</PathElement>
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<PathElement>Counters</PathElement>
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</Path>
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<Ordinal>1</Ordinal>
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<Direction>Output</Direction>
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<Radix>Decimal</Radix>
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</Wave>
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<Wave>
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<Name>Cnt3</Name>
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<Path>
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<PathElement>PT2001</PathElement>
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<PathElement>Injection Channel 1</PathElement>
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<PathElement>ChSequencers</PathElement>
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<PathElement>MicroMachineSeq0</PathElement>
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<PathElement>Counters</PathElement>
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</Path>
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<Ordinal>2</Ordinal>
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<Direction>Output</Direction>
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<Radix>Decimal</Radix>
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</Wave>
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<Wave>
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<Name>Cnt4</Name>
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<Path>
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<PathElement>PT2001</PathElement>
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<PathElement>Injection Channel 1</PathElement>
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<PathElement>ChSequencers</PathElement>
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<PathElement>MicroMachineSeq0</PathElement>
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<PathElement>Counters</PathElement>
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</Path>
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<Ordinal>3</Ordinal>
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<Direction>Output</Direction>
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<Radix>Decimal</Radix>
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</Wave>
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<Wave>
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<Name>Eoc1</Name>
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<Path>
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<PathElement>PT2001</PathElement>
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<PathElement>Injection Channel 1</PathElement>
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<PathElement>ChSequencers</PathElement>
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<PathElement>MicroMachineSeq0</PathElement>
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<PathElement>Counters</PathElement>
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</Path>
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<Ordinal>4</Ordinal>
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<Direction>Output</Direction>
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<Radix>Decimal</Radix>
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</Wave>
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<Wave>
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<Name>Eoc2</Name>
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<Path>
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<PathElement>PT2001</PathElement>
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<PathElement>Injection Channel 1</PathElement>
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||||
<PathElement>ChSequencers</PathElement>
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<PathElement>MicroMachineSeq0</PathElement>
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<PathElement>Counters</PathElement>
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</Path>
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<Ordinal>5</Ordinal>
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<Direction>Output</Direction>
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||||
<Radix>Decimal</Radix>
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</Wave>
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<Wave>
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||||
<Name>Eoc3</Name>
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||||
<Path>
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||||
<PathElement>PT2001</PathElement>
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||||
<PathElement>Injection Channel 1</PathElement>
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||||
<PathElement>ChSequencers</PathElement>
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||||
<PathElement>MicroMachineSeq0</PathElement>
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||||
<PathElement>Counters</PathElement>
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||||
</Path>
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||||
<Ordinal>6</Ordinal>
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<Direction>Output</Direction>
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||||
<Radix>Decimal</Radix>
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||||
</Wave>
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||||
<Wave>
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||||
<Name>Eoc4</Name>
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||||
<Path>
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||||
<PathElement>PT2001</PathElement>
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||||
<PathElement>Injection Channel 1</PathElement>
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||||
<PathElement>ChSequencers</PathElement>
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||||
<PathElement>MicroMachineSeq0</PathElement>
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||||
<PathElement>Counters</PathElement>
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||||
</Path>
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||||
<Ordinal>7</Ordinal>
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||||
<Direction>Output</Direction>
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||||
<Radix>Decimal</Radix>
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||||
</Wave>
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||||
<Wave>
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||||
<Name>TerminalCount1</Name>
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||||
<Path>
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||||
<PathElement>PT2001</PathElement>
|
||||
<PathElement>Injection Channel 1</PathElement>
|
||||
<PathElement>ChSequencers</PathElement>
|
||||
<PathElement>MicroMachineSeq0</PathElement>
|
||||
<PathElement>Counters</PathElement>
|
||||
</Path>
|
||||
<Ordinal>8</Ordinal>
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||||
<Direction>Output</Direction>
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||||
<Radix>Decimal</Radix>
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||||
</Wave>
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||||
<Wave>
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||||
<Name>TerminalCount2</Name>
|
||||
<Path>
|
||||
<PathElement>PT2001</PathElement>
|
||||
<PathElement>Injection Channel 1</PathElement>
|
||||
<PathElement>ChSequencers</PathElement>
|
||||
<PathElement>MicroMachineSeq0</PathElement>
|
||||
<PathElement>Counters</PathElement>
|
||||
</Path>
|
||||
<Ordinal>9</Ordinal>
|
||||
<Direction>Output</Direction>
|
||||
<Radix>Decimal</Radix>
|
||||
</Wave>
|
||||
<Wave>
|
||||
<Name>TerminalCount3</Name>
|
||||
<Path>
|
||||
<PathElement>PT2001</PathElement>
|
||||
<PathElement>Injection Channel 1</PathElement>
|
||||
<PathElement>ChSequencers</PathElement>
|
||||
<PathElement>MicroMachineSeq0</PathElement>
|
||||
<PathElement>Counters</PathElement>
|
||||
</Path>
|
||||
<Ordinal>10</Ordinal>
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||||
<Direction>Output</Direction>
|
||||
<Radix>Decimal</Radix>
|
||||
</Wave>
|
||||
<Wave>
|
||||
<Name>TerminalCount4</Name>
|
||||
<Path>
|
||||
<PathElement>PT2001</PathElement>
|
||||
<PathElement>Injection Channel 1</PathElement>
|
||||
<PathElement>ChSequencers</PathElement>
|
||||
<PathElement>MicroMachineSeq0</PathElement>
|
||||
<PathElement>Counters</PathElement>
|
||||
</Path>
|
||||
<Ordinal>11</Ordinal>
|
||||
<Direction>Output</Direction>
|
||||
<Radix>Decimal</Radix>
|
||||
</Wave>
|
||||
<Wave>
|
||||
<Name>Oaout1FlagOut</Name>
|
||||
<Path>
|
||||
<PathElement>PT2001</PathElement>
|
||||
</Path>
|
||||
<Ordinal>16</Ordinal>
|
||||
<Direction>Output</Direction>
|
||||
<Radix>Decimal</Radix>
|
||||
</Wave>
|
||||
<Wave>
|
||||
<Name>Flag0Out</Name>
|
||||
<Path>
|
||||
<PathElement>PT2001</PathElement>
|
||||
</Path>
|
||||
<Ordinal>2</Ordinal>
|
||||
<Direction>Output</Direction>
|
||||
<Radix>Decimal</Radix>
|
||||
</Wave>
|
||||
</Waves>
|
|
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|
|||
#include "dram1.def";
|
||||
* ### Channel 1 - uCore0 controls the injectors 1 and 2 ###
|
||||
|
||||
|
||||
* Note: The Thold_tot variable defines the current profile time out. The active STARTx pin is expected to toggle in is low state before this time out.
|
||||
|
||||
* ### Initialization phase ###
|
||||
init0: stgn gain12.6 sssc; * Set the gain of the opamp of the current measure block 1
|
||||
ldjr1 eoinj0; * Load the eoinj line label Code RAM address into the register jr1
|
||||
ldjr2 idle0; * Load the idle line label Code RAM address into the register jr2
|
||||
cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase
|
||||
|
||||
* ### Idle phase- the uPC loops here until start signal is present ###
|
||||
idle0: joslr inj1_start start1; * Perform an actuation on inj1 if start 1 (only) is active
|
||||
joslr inj2_start start2; * Perform an actuation on inj2 if start 2 (only) is active
|
||||
jmpf jr1; * If more than 1 start active at the same time(or none), no actuation
|
||||
|
||||
* ### Shortcuts definition per the injector to be actuated ###
|
||||
inj1_start: dfsct hs1 hs2 ls1; * Set the 3 shortcuts: VBAT, VBOOST, LS
|
||||
jmpr boost0; * Jump to launch phase
|
||||
|
||||
inj2_start: dfsct hs1 hs2 ls2; * Set the 3 shortcuts: VBAT, VBOOST, LS
|
||||
jmpr boost0; * Jump to launch phase
|
||||
|
||||
* ### Launch phase enable boost ###
|
||||
* Row1 - !start: injection ended
|
||||
* Row2 - Overcurrent, jump to error case (threshold is reached early)
|
||||
* Row3 - Overcurrent, jump to peak phase (threshold is reached on time)
|
||||
* Row4 - timer1: Minimum boost time reached - switch to row3 instead of row2 to allow peak phase
|
||||
* Row5 - timer2: Boost phase timeout - boost took too long, go to error phase
|
||||
boost0: load Iboost dac_sssc _ofs; * Load the boost phase current threshold in the current DAC
|
||||
cwer boost0_err ocur row2; * On overcurrent, go to boost error case
|
||||
cwer peak0 ocur row3; * Jump to peak phase when current is over threshold
|
||||
|
||||
ldcd rst _ofs keep keep Tboost_min c1; * Start boost counter to switch out of error behavior if threshold reached
|
||||
cwer boost0_mintime tc1 row4; * On timer timeout, go allow overcurrent without error (ie, end of boost)
|
||||
|
||||
ldcd rst _ofs keep keep Tboost_max c2; * Start boost counter in case Iboost never reached
|
||||
cwer boost0_err tc2 row5; * Jump to boost0_err in case boost phase takes too long
|
||||
|
||||
stf low b0; * set flag0 low to force the DC-DC converter in idle mode
|
||||
stos off on on; * Turn VBAT off, BOOST on, LS on
|
||||
wait row1245; * Wait for one of the previously defined conditions
|
||||
|
||||
* ### Boost phase - minimum time reached ###
|
||||
boost0_mintime: wait row135; * Minimum time for boost phase has been reached, now wait for !start, overcurrent or timeout
|
||||
|
||||
boost0_err: stos off off off; * Turn off all drivers
|
||||
stf low b10; * Set ch1 error flag (OA_1) to signal MCU
|
||||
stf high b0; * set flag0 high to release the DC-DC converter idle mode
|
||||
wait row1; * Wait for start signal to go low for the next injection attempt
|
||||
|
||||
* ### Peak phase continue on Vbat ###
|
||||
peak0: ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1
|
||||
load Ipeak dac_sssc _ofs; * Load the peak current threshold in the current DAC
|
||||
cwer bypass0 tc1 row2; * Jump to bypass phase when tc1 reaches end of count
|
||||
cwer peak_on0 tc2 row3; * Jump to peak_on when tc2 reaches end of count
|
||||
cwer peak_off0 ocur row4; * Jump to peak_off when current is over threshold
|
||||
stf high b0; * set flag0 high to release the DC-DC converter idle mode
|
||||
|
||||
peak_on0: stos on off on; * Turn VBAT on, BOOST off, LS on
|
||||
wait row124; * Wait for one of the previously defined conditions
|
||||
|
||||
peak_off0: ldcd rst ofs keep keep Tpeak_off c2; * Load in the counter 2 the length of the peak_off phase
|
||||
stos off off on; * Turn VBAT off, BOOST off, LS on
|
||||
wait row123; * Wait for one of the previously defined conditions
|
||||
|
||||
* ### Bypass phase ###
|
||||
bypass0: ldcd rst ofs keep keep Tbypass c3; * Load in the counter 3 the length of the off_phase phase
|
||||
stos off off off; * Turn VBAT off, BOOST off, LS off
|
||||
cwer hold0 tc3 row4; * Jump to hold when tc3 reaches end of count
|
||||
wait row14; * Wait for one of the previously defined conditions
|
||||
|
||||
* ### Hold phase on Vbat ###
|
||||
hold0: ldcd rst _ofs keep keep Thold_tot c1; * Load the length of the total hold phase in counter 2
|
||||
load Ihold dac_sssc _ofs; * Load the hold current threshold in the DAC
|
||||
cwer eoinj0 tc1 row2; * Jump to eoinj phase when tc1 reaches end of count
|
||||
cwer hold_on0 tc2 row3; * Jump to hold_on when tc2 reaches end of count
|
||||
cwer hold_off0 ocur row4; * Jump to hold_off when current is over threshold
|
||||
|
||||
hold_on0: stos on off on; * Turn VBAT on, BOOST off, LS on
|
||||
wait row124; * Wait for one of the previously defined conditions
|
||||
|
||||
hold_off0: ldcd rst _ofs keep keep Thold_off c2; * Load the length of the hold_off phase in counter 1
|
||||
stos off off on; * Turn VBAT off, BOOST off, LS on
|
||||
wait row123; * Wait for one of the previously defined conditions
|
||||
|
||||
* ### End of injection phase ###
|
||||
eoinj0: stos off off off; * Turn VBAT off, BOOST off, LS off
|
||||
stf high b0; * set flag0 to high to release the DC-DC converter idle mode
|
||||
jmpf jr2; * Jump back to idle phase
|
||||
|
||||
* ### End of Channel 1 - uCore0 code ###
|
||||
|
||||
*********************************************************************************
|
||||
|
||||
* ### Channel 1 - uCore1 controls the injectors 3 and 4 ###
|
||||
|
||||
* ### Initialization phase ###
|
||||
init1: stgn gain12.6 sssc; * Set the gain of the opamp of the current measure block 1
|
||||
ldjr1 eoinj1; * Load the eoinj line label Code RAM address into the register jr1
|
||||
ldjr2 idle1; * Load the idle line label Code RAM address into the register jr2
|
||||
cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase
|
||||
|
||||
|
||||
* ### Idle phase- the uPC loops here until start signal is present ###
|
||||
idle1: joslr inj3_start start3; * Perform an actuation on inj1 if start 1 (only) is active
|
||||
joslr inj4_start start4; * Perform an actuation on inj2 if start 2 (only) is active
|
||||
jmpf jr1; * If more than 1 start active at the same time(or none), no actuation
|
||||
|
||||
* ### Shortcuts definition per the injector to be actuated ###
|
||||
inj3_start: dfsct hs3 hs4 ls3; * Set the 3 shortcuts: VBAT, VBOOST, LS
|
||||
jmpr boost1; * Jump to launch phase
|
||||
|
||||
inj4_start: dfsct hs3 hs4 ls4; * Set the 3 shortcuts: VBAT, VBOOST, LS
|
||||
jmpr boost1; * Jump to launch phase
|
||||
|
||||
* ### Launch phase enable boost ###
|
||||
* Row1 - !start: injection ended
|
||||
* Row2 - Overcurrent, jump to error case (threshold is reached early)
|
||||
* Row3 - Overcurrent, jump to peak phase (threshold is reached on time)
|
||||
* Row4 - timer1: Minimum boost time reached - switch to row3 instead of row2 to allow peak phase
|
||||
* Row5 - timer2: Boost phase timeout - boost took too long, go to error phase
|
||||
boost1: load Iboost dac_sssc _ofs; * Load the boost phase current threshold in the current DAC
|
||||
cwer boost1_err ocur row2; * On overcurrent, go to boost error case
|
||||
cwer peak1 ocur row3; * Jump to peak phase when current is over threshold
|
||||
|
||||
ldcd rst _ofs keep keep Tboost_min c1; * Start boost counter to switch out of error behavior if threshold reached
|
||||
cwer boost1_mintime tc1 row4; * On timer timeout, go allow overcurrent without error (ie, end of boost)
|
||||
|
||||
ldcd rst _ofs keep keep Tboost_max c2; * Start boost counter in case Iboost never reached
|
||||
cwer boost1_err tc2 row5; * Jump to boost1_err in case boost phase takes too long
|
||||
|
||||
stf low b0; * set flag0 low to force the DC-DC converter in idle mode
|
||||
stos off on on; * Turn VBAT off, BOOST on, LS on
|
||||
wait row1245; * Wait for one of the previously defined conditions
|
||||
|
||||
* ### Boost phase - minimum time reached ###
|
||||
boost1_mintime: wait row135; * Minimum time for boost phase has been reached, now wait for !start, overcurrent or timeout
|
||||
|
||||
boost1_err: stos off off off; * Turn off all drivers
|
||||
stf low b11; * Set ch1 error flag (OA_1) to signal MCU
|
||||
stf high b0; * set flag0 high to release the DC-DC converter idle mode
|
||||
wait row1; * Wait for start signal to go low for the next injection attempt
|
||||
|
||||
|
||||
* ### Peak phase continue on Vbat ###
|
||||
peak1: ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1
|
||||
load Ipeak dac_sssc _ofs; * Load the peak current threshold in the current DAC
|
||||
cwer bypass1 tc1 row2; * Jump to bypass phase when tc1 reaches end of count
|
||||
cwer peak_on1 tc2 row3; * Jump to peak_on when tc2 reaches end of count
|
||||
cwer peak_off1 ocur row4; * Jump to peak_off when current is over threshold
|
||||
stf high b0; * set flag0 high to release the DC-DC converter idle mode
|
||||
|
||||
peak_on1: stos on off on; * Turn VBAT on, BOOST off, LS on
|
||||
wait row124; * Wait for one of the previously defined conditions
|
||||
|
||||
peak_off1: ldcd rst ofs keep keep Tpeak_off c2; * Load in the counter 2 the length of the peak_off phase
|
||||
stos off off on; * Turn VBAT off, BOOST off, LS on
|
||||
wait row123; * Wait for one of the previously defined conditions
|
||||
|
||||
* ### Bypass phase ###
|
||||
bypass1: ldcd rst ofs keep keep Tbypass c3; * Load in the counter 3 the length of the off_phase phase
|
||||
stos off off off; * Turn VBAT off, BOOST off, LS off
|
||||
cwer hold1 tc3 row4; * Jump to hold when tc3 reaches end of count
|
||||
wait row14; * Wait for one of the previously defined conditions
|
||||
|
||||
* ### Hold phase on Vbat ###
|
||||
hold1: ldcd rst _ofs keep keep Thold_tot c1; * Load the length of the total hold phase in counter 2
|
||||
load Ihold dac_sssc _ofs; * Load the hold current threshold in the DAC
|
||||
cwer eoinj1 tc1 row2; * Jump to eoinj phase when tc1 reaches end of count
|
||||
cwer hold_on1 tc2 row3; * Jump to hold_on when tc2 reaches end of count
|
||||
cwer hold_off1 ocur row4; * Jump to hold_off when current is over threshold
|
||||
|
||||
hold_on1: stos on off on; * Turn VBAT on, BOOST off, LS on
|
||||
wait row124; * Wait for one of the previously defined conditions
|
||||
|
||||
hold_off1: ldcd rst _ofs keep keep Thold_off c2; * Load the length of the hold_off phase in counter 1
|
||||
stos off off on; * Turn VBAT off, BOOST off, LS on
|
||||
wait row123; * Wait for one of the previously defined conditions
|
||||
|
||||
* ### End of injection phase ###
|
||||
eoinj1: stos off off off; * Turn VBAT off, BOOST off, LS off
|
||||
stf high b0; * set flag0 to high to release the DC-DC converter idle mode
|
||||
jmpf jr2; * Jump back to idle phase
|
||||
|
||||
* ### End of Channel 1 - uCore1 code ###
|
|
@ -0,0 +1,10 @@
|
|||
#define Iboost 0;
|
||||
#define Ipeak 1;
|
||||
#define Ihold 2;
|
||||
#define Tpeak_off 3;
|
||||
#define Tpeak_tot 4;
|
||||
#define Tbypass 5;
|
||||
#define Thold_off 6;
|
||||
#define Thold_tot 7;
|
||||
#define Tboost_max 8;
|
||||
#define Tboost_min 9;
|
|
@ -0,0 +1,77 @@
|
|||
#include "dram2.def";
|
||||
* ### Channel 2 - uCore0 controls dc-dc ###
|
||||
|
||||
* ### Initialization phase ###
|
||||
init0: stgn gain5.8 ossc; * Set the gain of the opamp of the current measure block 4
|
||||
load Isense4_low dac_ossc _ofs; * Load Isense4_high current threshold in DAC 4L
|
||||
load Isense4_high dac4h4n _ofs; * Load Isense4_high current threshold in DAC 4H
|
||||
stdm null; * Set the boost voltage DAC access mode
|
||||
cwer dcdc_idle _f0 row1; * Wait table entry for Vboost under Vboost_low threshold condition
|
||||
cwer dcdc_on _vb row2; * Wait table entry for Vboost under Vboost_low threshold condition
|
||||
cwer dcdc_off vb row3; * Wait table entry for Vboost over Vboost_high threshold condition
|
||||
|
||||
* ### Asynchronous phase ###
|
||||
dcdc_on: load Vboost_high dac4h4n _ofs; * Load the upper Vboost threshold in vboost_dac register
|
||||
stf high b1;
|
||||
stdcctl async; * Enable asynchronous mode
|
||||
wait row13; * Wait for one of the previously defined conditions
|
||||
|
||||
* ### Synchronous phase ###
|
||||
dcdc_off: load Vboost_low dac4h4n _ofs; * Load the upper Vboost threshold in vboost_dac register
|
||||
stf low b1;
|
||||
stdcctl sync; * Enable synchronous mode
|
||||
wait row12; * Wait for one of the previously defined conditions
|
||||
|
||||
* ### Idle phase ###
|
||||
dcdc_idle: stdcctl sync; * Enable synchronous mode
|
||||
stf low b1;
|
||||
stf high b1;
|
||||
jocr dcdc_idle _f0; * jump to previous line while flag 0 is low
|
||||
jmpr dcdc_on; * force the DC-DC converter on when flag 0 goes high
|
||||
|
||||
* ### End of Channel 2 - uCore0 code ###
|
||||
|
||||
*********************************************************************************
|
||||
|
||||
* ### Channel 2 - uCore1 drives HPFP high pressure fuel pump pressure control valve ###
|
||||
* todo: replace 'PCV' with HPFP
|
||||
|
||||
* Note: The Tpeak_tot variable defines the current profile time out. The active STARTx pin is expected to toggle in is low state before this time out.
|
||||
|
||||
* ### Initialization phase ###
|
||||
init1: stgn gain19.3 ossc; * Set the gain of the opamp of the current measure block 1
|
||||
ldjr1 eoact1; * Load the eoinj line label Code RAM address into the register jr1
|
||||
ldjr2 idle1; * Load the idle line label Code RAM address into the register jr2
|
||||
cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase
|
||||
|
||||
* ### Idle phase- the uPC loops here until start signal is present ###
|
||||
idle1: joslr act6_start start6; * Perform an actuation on act6 if start 6 (only) is active
|
||||
jmpf jr1; * If more than 1 start active at the same time(or none), no actuation
|
||||
|
||||
act6_start: dfsct hs5 ls6 undef; * Set the 2 shortcuts: VBAT, LS
|
||||
jmpr peak1; * Jump to launch phase
|
||||
|
||||
* ### Launch peak phase on bat ###
|
||||
peak1: load PCV_Ipeak dac_ossc _ofs; * Load the boost phase current threshold in the current DAC
|
||||
cwer hold1 cur3 row2; * Jump to hold phase when current is over threshold
|
||||
stos on on keep; * Turn VBAT on, LS on
|
||||
wait row12; * Wait for one of the previously defined conditions
|
||||
|
||||
* ### Hold phase on Vbat ###
|
||||
hold1: ldcd rst _ofs keep keep PCV_Thold_tot c1; * Load the length of the total hold phase in counter 1
|
||||
load PCV_Ihold dac_ossc _ofs; * Load the hold current threshold in the DAC
|
||||
cwer eoact1 tc1 row2; * Jump to eoinj phase when tc1 reaches end of count
|
||||
cwer hold_on1 tc2 row3; * Jump to hold_on when tc2 reaches end of count
|
||||
cwer hold_off1 cur3 row4; * Jump to hold_off when current is over threshold
|
||||
|
||||
hold_on1: stos on on keep; * Turn VBAT on, LS on
|
||||
wait row124; * Wait for one of the previously defined conditions
|
||||
|
||||
hold_off1: ldcd rst _ofs off on PCV_Thold_off c2; * Load the length of the hold_off phase in counter 2 and turn VBAT off, LS on
|
||||
wait row123; * Wait for one of the previously defined conditions
|
||||
|
||||
* ### End of injection phase ###
|
||||
eoact1: stos off off keep; * Turn VBAT off, LS off
|
||||
jmpf jr2; * Jump back to idle phase
|
||||
|
||||
* ### End of Channel 2 - uCore1 code ###
|
|
@ -0,0 +1,8 @@
|
|||
#define Vboost_high 0;
|
||||
#define Vboost_low 1;
|
||||
#define Isense4_high 2;
|
||||
#define Isense4_low 3;
|
||||
#define PCV_Ipeak 5;
|
||||
#define PCV_Ihold 6;
|
||||
#define PCV_Thold_off 7;
|
||||
#define PCV_Thold_tot 8;
|
|
@ -0,0 +1,19 @@
|
|||
0000000000001000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000101100010011
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000001101100
|
||||
0110101101011001
|
||||
1100100010100101
|
||||
0000000000000000
|
||||
0000000000101100
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
|
@ -0,0 +1,19 @@
|
|||
0000000000001000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000110000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000101011
|
||||
0010000110001100
|
||||
1101110010110110
|
||||
0000000000000000
|
||||
0000000000010100
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
|
@ -0,0 +1,44 @@
|
|||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000011110
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000011110
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000011110
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000011110
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000011110
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000011110
|
||||
0000000000011110
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000011110
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000011110
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000011110
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000011110
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000011110
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000001
|
|
@ -0,0 +1,64 @@
|
|||
0000000011000000
|
||||
0000000010010010
|
||||
0000000001001001
|
||||
0000000000111100
|
||||
0001000001101000
|
||||
0000000000111100
|
||||
0000000101101000
|
||||
1110101001100000
|
||||
0000100101100000
|
||||
0000001001011000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
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|
||||
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|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
|
@ -0,0 +1,64 @@
|
|||
0000000011000001
|
||||
0000000010111111
|
||||
0000000000101111
|
||||
0000000000011101
|
||||
0000000000000000
|
||||
0000000001000110
|
||||
0000000000110111
|
||||
0000000000111100
|
||||
1110101001100000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
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|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
|
||||
0000000000000000
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0000000000000000
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||||
0000000000000000
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0000000000000000
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0000000000000000
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0000000000000000
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0000000000000000
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0000000000000000
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0000000000000000
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0000000000000000
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0000000000000000
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0000000000000000
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||||
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0000000000000000
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0000000000000000
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||||
0000000000000000
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||||
0000000000000000
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|
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|||
0000000000000000
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||||
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0000000000000000
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||||
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||||
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||||
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||||
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||||
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0000000000000000
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||||
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||||
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||||
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||||
0000000000000000
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||||
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0000000000000000
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||||
0000000000000000
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||||
0000000000000000
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||||
0000000000000000
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||||
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||||
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||||
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||||
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||||
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||||
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||||
0000000000000000
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||||
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|
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|
|||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
0000000000000000
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|
@ -0,0 +1,13 @@
|
|||
<LoadDefault xmlns="http://tempuri.org/AutoLoad.xsd">
|
||||
<MicroCodesReload ch1="True" ch2="True" ch3="True" />
|
||||
<DPRamsReload ch1="True" ch2="True" ch3="True" />
|
||||
<ChannelParametersReload ch1="True" ch2="True" ch3="True" />
|
||||
<MainConfigurationReload reload="True" />
|
||||
<DiagnosisConfigurationReload reload="True" />
|
||||
<CrossbarConfigurationReload reload="True" />
|
||||
<StimulusReload reload="True" />
|
||||
<ActuatorReload reload="True" />
|
||||
<FeedbackReload reload="True" />
|
||||
<GraphicsReload reload="True" />
|
||||
<ForceFlashEnable ch1="True" ch2="True" ch3="True" />
|
||||
</LoadDefault>
|
|
@ -0,0 +1,4 @@
|
|||
<Stimuli>
|
||||
<Stimulus target="Start1" time="1 ms" period="" value="high" />
|
||||
<Stimulus target="Start1" time="3 ms" period="" value="low" />
|
||||
</Stimuli>
|
|
@ -0,0 +1,29 @@
|
|||
<AddressLabels>
|
||||
<Channel1>
|
||||
<uc0>
|
||||
<Entrypoint>init0</Entrypoint>
|
||||
<DiagRoutineAddress>init0</DiagRoutineAddress>
|
||||
<DriverDisabledAddress>init0</DriverDisabledAddress>
|
||||
<SwInterruptAddress>init0</SwInterruptAddress>
|
||||
</uc0>
|
||||
<uc1>
|
||||
<DiagRoutineAddress>init0</DiagRoutineAddress>
|
||||
<DriverDisabledAddress>init0</DriverDisabledAddress>
|
||||
<SwInterruptAddress>init0</SwInterruptAddress>
|
||||
</uc1>
|
||||
</Channel1>
|
||||
<Channel2>
|
||||
<uc0>
|
||||
<Entrypoint>init0</Entrypoint>
|
||||
<DiagRoutineAddress>init0</DiagRoutineAddress>
|
||||
<DriverDisabledAddress>init0</DriverDisabledAddress>
|
||||
<SwInterruptAddress>init0</SwInterruptAddress>
|
||||
</uc0>
|
||||
<uc1>
|
||||
<Entrypoint>init1</Entrypoint>
|
||||
<DiagRoutineAddress>init0</DiagRoutineAddress>
|
||||
<DriverDisabledAddress>init0</DriverDisabledAddress>
|
||||
<SwInterruptAddress>init0</SwInterruptAddress>
|
||||
</uc1>
|
||||
</Channel2>
|
||||
</AddressLabels>
|
|
@ -0,0 +1,371 @@
|
|||
<Project xmlns="http://tempuri.org/project.xsd">
|
||||
<Identifiers>
|
||||
<Device>PT2001</Device>
|
||||
<ECU>IDE Project</ECU>
|
||||
<Application>%APPLICATION%</Application>
|
||||
<DeviceName>%DEVICEID%</DeviceName>
|
||||
<Version>rusefi</Version>
|
||||
<Prefix>%PREFIX%</Prefix>
|
||||
</Identifiers>
|
||||
<Files>
|
||||
<RegisterFile areaName="Main Configuration Registers (MCR)">Registers\main_config_reg.hex</RegisterFile>
|
||||
<RegisterFile areaName="Channel 1 Configuration Registers (C1PR)">Registers\ch1_config_reg.hex</RegisterFile>
|
||||
<RegisterFile areaName="Channel 2 Configuration Registers (C2PR)">Registers\ch2_config_reg.hex</RegisterFile>
|
||||
<RegisterFile areaName="Diagnosis Configuration Registers (DCR)">Registers\diag_config_reg.hex</RegisterFile>
|
||||
<RegisterFile areaName="Crossbar Configuration Registers (XCR)">Registers\io_config_reg.hex</RegisterFile>
|
||||
<MicroCodeFile channel="1" type="source" date="133028365609622710">MicrocodeCh1\ch1.psc</MicroCodeFile>
|
||||
<MicroCodeFile channel="2" type="source" date="133028364882509871">MicrocodeCh2\ch2.psc</MicroCodeFile>
|
||||
<MicroCodeFile channel="1" type="binary" date="133028335142178693">bin\ch1.bin</MicroCodeFile>
|
||||
<MicroCodeFile channel="2" type="binary" date="133028335144648651">bin\ch2.bin</MicroCodeFile>
|
||||
<MicroCodeFile channel="1" type="hex" date="133028335142698602">bin\ch1.hex</MicroCodeFile>
|
||||
<MicroCodeFile channel="2" type="hex" date="133028335145068598">bin\ch2.hex</MicroCodeFile>
|
||||
<DPramFile channel="1">Registers\dram1.hex</DPramFile>
|
||||
<DPramFile channel="2">Registers\dram2.hex</DPramFile>
|
||||
<LabelFile>labels.xml</LabelFile>
|
||||
<ActuatorFile>Actuator\inj1.xml</ActuatorFile>
|
||||
<ActuatorFile>Actuator\dcdc_current.xml</ActuatorFile>
|
||||
<ActuatorFile>Actuator\dcdc_voltage.xml</ActuatorFile>
|
||||
<VoltageFile>Feedbacks\dcdc_voltage.xml</VoltageFile>
|
||||
<StimulusFile>Stimulus\stim.xml</StimulusFile>
|
||||
<WaveFile>Logic_Wave\wave_list.do</WaveFile>
|
||||
<AutoLoadFile>AutoLoad.xml</AutoLoadFile>
|
||||
</Files>
|
||||
<General>
|
||||
<Clock>1 MHz</Clock>
|
||||
</General>
|
||||
<Windows>
|
||||
<Structure x="292" y="767" xSize="392" ySize="482" state="Normal" visible="True" />
|
||||
<Signals x="698" y="177" xSize="250" ySize="1083" state="Normal" visible="True" />
|
||||
<Micro x="0" y="0" xSize="936" ySize="715" state="Normal" visible="True">
|
||||
<Hex8ForLine>True</Hex8ForLine>
|
||||
<SeparateCompiledFolder>True</SeparateCompiledFolder>
|
||||
<DPram channel="1" addressFormat="Hex">
|
||||
<Entry address="0" format="Source" unit="None" indexSelected="0" />
|
||||
<Entry address="1" format="Source" unit="None" indexSelected="0" />
|
||||
<Entry address="2" format="Source" unit="None" indexSelected="0" />
|
||||
<Entry address="3" format="Source" unit="None" indexSelected="0" />
|
||||
<Entry address="4" format="Source" unit="None" indexSelected="0" />
|
||||
<Entry address="5" format="Source" unit="None" indexSelected="0" />
|
||||
<Entry address="6" format="Source" unit="None" indexSelected="0" />
|
||||
<Entry address="7" format="Source" unit="None" indexSelected="0" />
|
||||
<Entry address="8" format="Source" unit="None" indexSelected="0" />
|
||||
<Entry address="9" format="Source" unit="None" indexSelected="0" />
|
||||
<Entry address="10" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="11" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="12" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="13" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="14" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="15" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="16" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="17" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="18" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="19" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="20" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="21" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="22" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="23" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="24" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="25" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="26" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="27" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="28" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="29" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="30" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="31" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="32" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="33" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="34" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="35" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="36" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="37" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="38" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="39" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="40" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="41" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="42" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="43" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="44" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="45" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="46" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="47" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="48" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="49" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="50" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="51" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="52" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="53" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="54" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="55" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="56" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="57" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="58" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="59" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="60" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="61" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="62" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="63" format="Hex" unit="None" indexSelected="0" />
|
||||
</DPram>
|
||||
<DPram channel="2" addressFormat="Hex">
|
||||
<Entry address="0" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="1" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="2" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="3" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="4" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="5" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="6" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="7" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="8" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="9" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="10" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="11" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="12" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="13" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="14" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="15" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="16" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="17" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="18" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="19" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="20" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="21" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="22" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="23" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="24" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="25" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="26" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="27" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="28" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="29" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="30" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="31" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="32" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="33" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="34" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="35" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="36" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="37" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="38" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="39" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="40" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="41" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="42" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="43" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="44" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="45" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="46" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="47" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="48" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="49" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="50" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="51" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="52" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="53" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="54" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="55" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="56" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="57" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="58" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="59" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="60" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="61" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="62" format="Hex" unit="None" indexSelected="0" />
|
||||
<Entry address="63" format="Hex" unit="None" indexSelected="0" />
|
||||
</DPram>
|
||||
<RegisterArea name="Main Configuration Registers (MCR)">
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
</RegisterArea>
|
||||
<RegisterArea name="Diagnosis Configuration Registers (DCR)">
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
</RegisterArea>
|
||||
<RegisterArea name="Crossbar Configuration Registers (XCR)">
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
</RegisterArea>
|
||||
<RegisterArea name="Channel 1 Configuration Registers (C1PR)">
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
</RegisterArea>
|
||||
<RegisterArea name="Channel 2 Configuration Registers (C2PR)">
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
</RegisterArea>
|
||||
<RegisterArea name="Channel 3 Configuration Registers (C3PR)">
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
<Reg>Hex</Reg>
|
||||
</RegisterArea>
|
||||
</Micro>
|
||||
<Log x="156" y="156" xSize="931" ySize="663" state="Normal" visible="True" />
|
||||
<Wave x="957" y="5" xSize="1567" ySize="805" state="Normal" visible="True" />
|
||||
<Current x="1096" y="828" xSize="1436" ySize="464" state="Normal" visible="True" />
|
||||
<Stimulus x="214" y="183" xSize="540" ySize="368" state="Normal" visible="False" />
|
||||
<Voltage x="0" y="0" xSize="580" ySize="357" state="Normal" visible="False" />
|
||||
<Actuator x="15" y="733" xSize="601" ySize="444" state="Normal" visible="True" />
|
||||
</Windows>
|
||||
</Project>
|
|
@ -0,0 +1,22 @@
|
|||
|
||||
Source code here is different from but is heavily inspired by MC33816 example as conveniently comes with MC33816 Dev Studio.
|
||||
|
||||
## Workflow:
|
||||
|
||||
### PT2001 Studio: Compiling/Generating C/header Files
|
||||
|
||||
1. Open "PT2001 Developer Studio", and open project `firmware/hw_layer/mc33816/rusefi/project.xml`.
|
||||
2. Press the "Build" button at the right/center of the window to assemble the microcode.
|
||||
3. Use `Tools` -> `Generate PT2001 Load Data Code` to generate C/header files used by rusEFI to program the PT2001 over SPI at boot (see `mc33816/rusefi/sample_code/`).
|
||||
|
||||
### PSC Simulator: Simulating microcode/config changes
|
||||
|
||||
1. Follow "PT2001 Studio" steps to build the project first.
|
||||
2. Open "PSC Simulator", add the project if not added yet (`Project` -> `Add Existing`), and open it from the tree view.
|
||||
3. Press `Compile All` in the toolbar.
|
||||
4. In the top bar, push `Run`, and type in the desired simulation length. `4 ms` (with a space) is a good starting point for the existing stimulus.
|
||||
5. Press OK on the `Auto Load` dialog box that comes up (all boxes checked).
|
||||
6. Wait for the simulation to run. There's an indication in the bottom left corner of the main window about simulation progress.
|
||||
7. Inspect the simulation results!
|
||||
|
||||
Just in case we have a backup of tools at https://github.com/rusefi/rusefi_external_utils/tree/master/NXP-GDI
|
|
@ -0,0 +1,136 @@
|
|||
/*******************************************************************************
|
||||
* Example Code
|
||||
*
|
||||
* Copyright(C) 2022 NXP Semiconductors
|
||||
* NXP Semiconductors Confidential and Proprietary
|
||||
*
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* NXP products. This software is supplied "AS IS" without any warranties
|
||||
* of any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights
|
||||
* under any patent, copyright, mask work right, or any other intellectual
|
||||
* property rights in or to any products. NXP Semiconductors reserves the
|
||||
* right to make changes in the software without notification. NXP
|
||||
* Semiconductors also makes no representation or warranty that such
|
||||
* application will be suitable for the specified use without further testing
|
||||
* or modification.
|
||||
*
|
||||
* IN NO EVENT WILL NXP SEMICONDUCTORS BE LIABLE, WHETHER IN CONTRACT,
|
||||
* TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL
|
||||
* OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY
|
||||
* LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST
|
||||
* PROFITS, SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED
|
||||
* BY LAW. NXP SEMICONDUCTOR’S TOTAL LIABILITY FOR ALL COSTS, DAMAGES,
|
||||
* CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP SEMICONDUCTORS
|
||||
* IN CONNECTION WITH THE SOFTWARE TO WHICH LOSSES OR DAMAGES ARE CLAIMED.
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided
|
||||
* that it is used in conjunction with NXP Semiconductors devices. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies
|
||||
* of this code.
|
||||
*******************************************************************************/
|
||||
|
||||
//==============================================================================
|
||||
// This file contains data arrays that are used to load the code RAM, data RAM
|
||||
// and registers on the PT2001.
|
||||
//==============================================================================
|
||||
|
||||
// ECU: IDE Project
|
||||
// Project: rusefi
|
||||
|
||||
#include "PT2001_LoadData.h"
|
||||
|
||||
// Data to be loaded into the Code RAM 1 memory space
|
||||
unsigned short PT2001_code_RAM1[108] =
|
||||
{
|
||||
0x7612, 0x6C43, 0x917F, 0xA514, 0x8DD1, 0xC289, 0x7C38, 0xA73B, 0xF359, 0x56C3,
|
||||
0xEE73, 0x812F, 0xC3A9, 0xC08B, 0x4371, 0x45BB, 0x64D7, 0xB185, 0x1C57, 0x49AA,
|
||||
0x40E9, 0xBF4C, 0x2F07, 0xDBCD, 0x057C, 0x8C8A, 0xD1F7, 0x3B13, 0x492C, 0x6544,
|
||||
0x277D, 0x799E, 0xD6B1, 0x477E, 0x0091, 0x0103, 0x6DA0, 0xA3AE, 0xE91C, 0xAF72,
|
||||
0x3DAC, 0x2230, 0xB8C0, 0x8A6B, 0x1E34, 0xDEBF, 0x0592, 0x9E7A, 0x8E2D, 0x809B,
|
||||
0x4F9F, 0x85C9, 0x5119, 0x7C72, 0xF333, 0xC575, 0x8B35, 0xD254, 0xD8FA, 0x3D01,
|
||||
0x1B1D, 0xDA87, 0xFE4A, 0x74B1, 0x789D, 0x2B94, 0x360D, 0x00A8, 0x8F78, 0xC909,
|
||||
0x3F0C, 0x9409, 0xFDFB, 0x43E3, 0x56E1, 0x9FA5, 0xEC49, 0xDEC7, 0x3A2C, 0xD350,
|
||||
0x40AC, 0x3447, 0xC1EB, 0x2D74, 0x1526, 0x7C64, 0xE7AE, 0x17AF, 0xDA5A, 0x78DB,
|
||||
0x1F1B, 0x5A34, 0x6503, 0xD511, 0xF26C, 0x9461, 0x7962, 0x531A, 0xB074, 0xF3C1,
|
||||
0xB55C, 0xDAC7, 0x4746, 0x3AE8, 0xDFB2, 0x04D9, 0x05F1, 0x1C88
|
||||
};
|
||||
|
||||
// Data to be loaded into the Code RAM 2 memory space
|
||||
unsigned short PT2001_code_RAM2[43] =
|
||||
{
|
||||
0x761B, 0x6F45, 0x838D, 0x80B4, 0x53F2, 0x0EBC, 0x8F2D, 0xA78E, 0xE8AB, 0xE3DB,
|
||||
0xF477, 0x800F, 0x2336, 0x2F77, 0x267B, 0xBC19, 0x007E, 0x4E55, 0x28AA, 0x52E4,
|
||||
0x40CF, 0x0AFD, 0x8B32, 0xFF03, 0x3D8E, 0x802E, 0x1340, 0x95D0, 0x1E86, 0x6591,
|
||||
0xDBEB, 0x786D, 0xB2DF, 0xF4BF, 0xBEB2, 0xF1F4, 0x9E53, 0xE743, 0xE842, 0x3DD7,
|
||||
0x3DA2, 0x4663, 0x03AF
|
||||
};
|
||||
|
||||
// Data to be loaded into the Data RAM memory space
|
||||
unsigned short PT2001_data_RAM[128] =
|
||||
{
|
||||
0x00C0, 0x0092, 0x0049, 0x003C, 0x1068, 0x003C, 0x0168, 0xEA60, 0x0960, 0x0258,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x00C1, 0x00BF, 0x002F, 0x001D, 0x0000, 0x0046,
|
||||
0x0037, 0x003C, 0xEA60, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
|
||||
};
|
||||
|
||||
// Data to be loaded into the Main register memory space
|
||||
unsigned short PT2001_main_config[29] =
|
||||
{
|
||||
0x0003, 0x13FE, 0x0000, 0x1E00, 0x0000, 0x0000, 0x0001, 0x0000, 0x001F, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
|
||||
};
|
||||
|
||||
// Data to be loaded into the CH1 register memory space
|
||||
unsigned short PT2001_ch1_config[19] =
|
||||
{
|
||||
0x0008, 0x0000, 0x0000, 0x0000, 0x0B13, 0x0000, 0x0000, 0x006C, 0x6B59, 0xC8A5,
|
||||
0x0000, 0x002C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
|
||||
};
|
||||
|
||||
// Data to be loaded into the CH2 register memory space
|
||||
unsigned short PT2001_ch2_config[19] =
|
||||
{
|
||||
0x0008, 0x0000, 0x0000, 0x0000, 0x0C00, 0x0000, 0x0000, 0x002B, 0x218C, 0xDCB6,
|
||||
0x0000, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
|
||||
};
|
||||
|
||||
// Data to be loaded into the IO register memory space
|
||||
unsigned short PT2001_io_config[53] =
|
||||
{
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0063, 0x018C, 0x0800, 0x0410, 0x0041, 0x0098,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0041, 0x0041, 0x0041, 0x0000, 0x0004, 0x1000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x7F7F, 0x7F7F,
|
||||
0x007F, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000
|
||||
};
|
||||
|
||||
// Data to be loaded into the Diag register memory space
|
||||
unsigned short PT2001_diag_config[44] =
|
||||
{
|
||||
0x0000, 0x0000, 0x001E, 0x0000, 0x0000, 0x001E, 0x0000, 0x0000, 0x001E, 0x0000,
|
||||
0x0000, 0x001E, 0x0000, 0x0000, 0x001E, 0x0000, 0x0000, 0x001E, 0x001E, 0x0000,
|
||||
0x0000, 0x001E, 0x0000, 0x0000, 0x001E, 0x0000, 0x0000, 0x001E, 0x0000, 0x0000,
|
||||
0x001E, 0x0000, 0x0000, 0x001E, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0001
|
||||
};
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/*******************************************************************************
|
||||
* Example Code
|
||||
*
|
||||
* Copyright(C) 2022 NXP Semiconductors
|
||||
* NXP Semiconductors Confidential and Proprietary
|
||||
*
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* NXP products. This software is supplied "AS IS" without any warranties
|
||||
* of any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights
|
||||
* under any patent, copyright, mask work right, or any other intellectual
|
||||
* property rights in or to any products. NXP Semiconductors reserves the
|
||||
* right to make changes in the software without notification. NXP
|
||||
* Semiconductors also makes no representation or warranty that such
|
||||
* application will be suitable for the specified use without further testing
|
||||
* or modification.
|
||||
*
|
||||
* IN NO EVENT WILL NXP SEMICONDUCTORS BE LIABLE, WHETHER IN CONTRACT,
|
||||
* TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL
|
||||
* OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY
|
||||
* LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST
|
||||
* PROFITS, SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED
|
||||
* BY LAW. NXP SEMICONDUCTOR’S TOTAL LIABILITY FOR ALL COSTS, DAMAGES,
|
||||
* CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP SEMICONDUCTORS
|
||||
* IN CONNECTION WITH THE SOFTWARE TO WHICH LOSSES OR DAMAGES ARE CLAIMED.
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided
|
||||
* that it is used in conjunction with NXP Semiconductors devices. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies
|
||||
* of this code.
|
||||
*******************************************************************************/
|
||||
|
||||
//==============================================================================
|
||||
// This file contains data array declarations for the code RAM, data RAM and
|
||||
// register arrays for the PT2001.
|
||||
//==============================================================================
|
||||
|
||||
// ECU: IDE Project
|
||||
// Project: rusefi
|
||||
|
||||
#ifndef PT2001_DATA_H_
|
||||
#define PT2001_DATA_H_
|
||||
|
||||
extern unsigned short PT2001_code_RAM1[108]; // CODE RAM CH 1
|
||||
extern unsigned short PT2001_code_RAM2[43]; // CODE RAM CH 2
|
||||
extern unsigned short PT2001_data_RAM[128]; // DATA RAM
|
||||
extern unsigned short PT2001_main_config[29]; // main configurations
|
||||
extern unsigned short PT2001_ch1_config[19]; // CH 1 configurations
|
||||
extern unsigned short PT2001_ch2_config[19]; // CH 2 configurations
|
||||
extern unsigned short PT2001_io_config[53]; // IO configurations
|
||||
extern unsigned short PT2001_diag_config[44]; // diag configurations
|
||||
|
||||
#endif /* PT2001_DATA_H_ */
|
|
@ -0,0 +1,72 @@
|
|||
/*******************************************************************************
|
||||
* Example Code
|
||||
*
|
||||
* Copyright(C) 2022 NXP Semiconductors
|
||||
* NXP Semiconductors Confidential and Proprietary
|
||||
*
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* NXP products. This software is supplied "AS IS" without any warranties
|
||||
* of any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights
|
||||
* under any patent, copyright, mask work right, or any other intellectual
|
||||
* property rights in or to any products. NXP Semiconductors reserves the
|
||||
* right to make changes in the software without notification. NXP
|
||||
* Semiconductors also makes no representation or warranty that such
|
||||
* application will be suitable for the specified use without further testing
|
||||
* or modification.
|
||||
*
|
||||
* IN NO EVENT WILL NXP SEMICONDUCTORS BE LIABLE, WHETHER IN CONTRACT,
|
||||
* TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL
|
||||
* OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY
|
||||
* LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST
|
||||
* PROFITS, SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED
|
||||
* BY LAW. NXP SEMICONDUCTOR’S TOTAL LIABILITY FOR ALL COSTS, DAMAGES,
|
||||
* CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP SEMICONDUCTORS
|
||||
* IN CONNECTION WITH THE SOFTWARE TO WHICH LOSSES OR DAMAGES ARE CLAIMED.
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided
|
||||
* that it is used in conjunction with NXP Semiconductors devices. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies
|
||||
* of this code.
|
||||
*******************************************************************************/
|
||||
|
||||
/*
|
||||
* PT2001_dram.h
|
||||
*
|
||||
* DRAM Header File
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PT2001_DRAM_H_
|
||||
#define PT2001_DRAM_H_
|
||||
|
||||
// DRAM 1 Parameter Addresses
|
||||
#define PT2001_D1_Iboost 0x00
|
||||
#define PT2001_D1_Ipeak 0x01
|
||||
#define PT2001_D1_Ihold 0x02
|
||||
#define PT2001_D1_Tpeak_off 0x03
|
||||
#define PT2001_D1_Tpeak_tot 0x04
|
||||
#define PT2001_D1_Tbypass 0x05
|
||||
#define PT2001_D1_Thold_off 0x06
|
||||
#define PT2001_D1_Thold_tot 0x07
|
||||
#define PT2001_D1_Tboost_max 0x08
|
||||
#define PT2001_D1_Tboost_min 0x09
|
||||
|
||||
// DRAM 2 Parameter Addresses
|
||||
#define PT2001_D2_Vboost_high 0x40
|
||||
#define PT2001_D2_Vboost_low 0x41
|
||||
#define PT2001_D2_Isense4_high 0x42
|
||||
#define PT2001_D2_Isense4_low 0x43
|
||||
#define PT2001_D2_PCV_Ipeak 0x45
|
||||
#define PT2001_D2_PCV_Ihold 0x46
|
||||
#define PT2001_D2_PCV_Thold_off 0x47
|
||||
#define PT2001_D2_PCV_Thold_tot 0x48
|
||||
|
||||
#endif /* PT2001_DRAM_H_ */
|
Loading…
Reference in New Issue