diff --git a/hardware/Breakout_TLE6244/Breakout_TLE6244.kicad_pcb b/hardware/Breakout_TLE6244/Breakout_TLE6244.kicad_pcb
new file mode 100644
index 0000000000..81d619944b
--- /dev/null
+++ b/hardware/Breakout_TLE6244/Breakout_TLE6244.kicad_pcb
@@ -0,0 +1,323 @@
+(kicad_pcb (version 3) (host pcbnew "(2013-07-07 BZR 4022)-stable")
+
+  (general
+    (links 0)
+    (no_connects 0)
+    (area 199.664319 139.6695 217.836485 159.745681)
+    (thickness 1.6)
+    (drawings 0)
+    (tracks 0)
+    (zones 0)
+    (modules 1)
+    (nets 1)
+  )
+
+  (page A)
+  (title_block 
+    (title "TLE6244 Breakout")
+    (rev R0.1)
+    (company rusEFI)
+  )
+
+  (layers
+    (15 F.Cu signal)
+    (0 B.Cu signal)
+    (16 B.Adhes user)
+    (17 F.Adhes user)
+    (18 B.Paste user)
+    (19 F.Paste user)
+    (20 B.SilkS user)
+    (21 F.SilkS user)
+    (22 B.Mask user)
+    (23 F.Mask user)
+    (24 Dwgs.User user)
+    (25 Cmts.User user)
+    (26 Eco1.User user)
+    (27 Eco2.User user)
+    (28 Edge.Cuts user)
+  )
+
+  (setup
+    (last_trace_width 0.254)
+    (trace_clearance 0.254)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.254)
+    (segment_width 0.2)
+    (edge_width 0.1)
+    (via_size 0.889)
+    (via_drill 0.635)
+    (via_min_size 0.889)
+    (via_min_drill 0.508)
+    (uvia_size 0.508)
+    (uvia_drill 0.127)
+    (uvias_allowed no)
+    (uvia_min_size 0.508)
+    (uvia_min_drill 0.127)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.15)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.5 1.5)
+    (pad_drill 0.6)
+    (pad_to_mask_clearance 0)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFFBF)
+    (pcbplotparams
+      (layerselection 3178497)
+      (usegerberextensions true)
+      (excludeedgelayer true)
+      (linewidth 0.150000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15)
+      (hpglpenoverlay 2)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotothertext true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+
+  (net_class Default "This is the default net class."
+    (clearance 0.254)
+    (trace_width 0.254)
+    (via_dia 0.889)
+    (via_drill 0.635)
+    (uvia_dia 0.508)
+    (uvia_drill 0.127)
+    (add_net "")
+  )
+
+  (module HiQUAD64 (layer F.Cu) (tedit 5483B1B5) (tstamp 5483B49E)
+    (at 208.915 150.495)
+    (fp_text reference Test (at -6.5 -10) (layer F.SilkS)
+      (effects (font (size 1.016 1.016) (thickness 0.127)))
+    )
+    (fp_text value VAL** (at 5.5 -10) (layer F.SilkS)
+      (effects (font (size 1.016 1.016) (thickness 0.127)))
+    )
+    (fp_line (start -8.5 -2.5) (end -8.5 2.5) (layer F.SilkS) (width 0.15))
+    (fp_line (start 8.5 -2.5) (end 8.5 2.5) (layer F.SilkS) (width 0.15))
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+    (fp_line (start 6.37286 -8.5979) (end 8.5979 -8.5979) (layer F.SilkS) (width 0.09906))
+    (fp_line (start 8.5979 -8.5979) (end 8.5979 -6.37286) (layer F.SilkS) (width 0.09906))
+    (fp_line (start 8.5979 6.37286) (end 8.5979 8.5979) (layer F.SilkS) (width 0.09906))
+    (fp_line (start -8.5979 8.5979) (end -6.37286 8.5979) (layer F.SilkS) (width 0.09906))
+    (fp_line (start 6.37286 8.5979) (end 8.5979 8.5979) (layer F.SilkS) (width 0.09906))
+    (fp_line (start -8.5979 -8.5979) (end -8.5979 -6.37286) (layer F.SilkS) (width 0.09906))
+    (fp_line (start -8.5979 6.37286) (end -8.5979 8.5979) (layer F.SilkS) (width 0.09906))
+    (fp_line (start -8.89762 8.89762) (end -8.89762 8.89762) (layer F.SilkS) (width 0.19812))
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+    (pad EP smd rect (at 0 0) (size 9.5 9.5)
+      (layers F.Cu F.Paste F.Mask)
+    )
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+
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diff --git a/hardware/Breakout_TLE6244/Breakout_TLE6244.pro b/hardware/Breakout_TLE6244/Breakout_TLE6244.pro
new file mode 100644
index 0000000000..164e725498
--- /dev/null
+++ b/hardware/Breakout_TLE6244/Breakout_TLE6244.pro
@@ -0,0 +1,87 @@
+update=12/6/2014 8:55:54 PM
+version=1
+last_client=pcbnew
+[cvpcb]
+version=1
+NetIExt=net
+[cvpcb/libraries]
+EquName1=devcms
+[eeschema]
+version=1
+LibDir=
+NetFmtName=
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
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+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
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+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+[general]
+version=1
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
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+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[pcbnew/libraries]
+LibDir=../rusefi_lib
+LibName1=sockets
+LibName2=connect
+LibName3=discret
+LibName4=pin_array
+LibName5=divers
+LibName6=smd_capacitors
+LibName7=smd_resistors
+LibName8=smd_crystal&oscillator
+LibName9=smd_dil
+LibName10=smd_transistors
+LibName11=libcms
+LibName12=display
+LibName13=led
+LibName14=dip_sockets
+LibName15=pga_sockets
+LibName16=valves
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diff --git a/hardware/rusefi_lib/HiQUAD64.mod b/hardware/rusefi_lib/HiQUAD64.mod
new file mode 100644
index 0000000000..2db7031fc0
--- /dev/null
+++ b/hardware/rusefi_lib/HiQUAD64.mod
@@ -0,0 +1,482 @@
+PCBNEW-LibModule-V1  12/6/2014 8:50:39 PM
+# encoding utf-8
+Units mm
+$INDEX
+HiQUAD64
+$EndINDEX
+$MODULE HiQUAD64
+Po 0 0 0 15 5483B1B5 00000000 ~~
+Li HiQUAD64
+Sc 0
+AR 
+Op 0 0 0
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+$EndLIBRARY