diff --git a/firmware/hw_layer/ports/stm32/port_mpu_util.h b/firmware/hw_layer/ports/stm32/port_mpu_util.h
index 769d8c2fe7..9018f2149a 100644
--- a/firmware/hw_layer/ports/stm32/port_mpu_util.h
+++ b/firmware/hw_layer/ports/stm32/port_mpu_util.h
@@ -23,6 +23,17 @@
 #define SCHEDULER_TIMER_DEVICE TIM5
 #define SCHEDULER_TIMER_FREQ (US_TO_NT_MULTIPLIER * 1'000'000)
 
+/* TODO: rename includes to hal_flash_ex.h with no MCU specific? */
+#ifdef STM32F4XX
+#include "stm32f4xx_hal_flash_ex.h"
+#endif
+#ifdef STM32F7XX
+#include "stm32f7xx_hal_flash_ex.h"
+#endif
+#ifdef STM32H7XX
+#include "stm32h7xx_hal_flash_ex.h"
+#endif
+
 #ifdef AT32F4XX
 /* TODO: Artery */
 typedef enum {
@@ -32,7 +43,6 @@ typedef enum {
     BOR_Level_3 = PWR_CR_PLS_LEV7  // 0x00     Supply voltage ranges from 2.70 to 3.60 V
 } BOR_Level_t;
 #else
-#include "stm32f4xx_hal_flash_ex.h"
 typedef enum {
 	BOR_Level_None = OB_BOR_OFF, // 0x0C=12  Supply voltage ranges from 1.62 to 2.10 V
 	BOR_Level_1 = OB_BOR_LEVEL1, // 0x08     Supply voltage ranges from 2.10 to 2.40 V
diff --git a/firmware/rusefi.mk b/firmware/rusefi.mk
index 5bef206f10..e3b9d7bd55 100644
--- a/firmware/rusefi.mk
+++ b/firmware/rusefi.mk
@@ -44,33 +44,33 @@ endif
 
 # CPU-dependent defs
 ifeq ($(PROJECT_CPU),ARCH_STM32F7)
-	CPU_STARTUP = startup_stm32f7xx.mk
-	# next file is included through Contrib's platform.ml
-	#CPU_PLATFORM = $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/platform.mk
-	CPU_PLATFORM = ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/STM32F7xx/platform.mk
-	CPU_HWLAYER = ports/stm32/stm32f7
+  CPU_STARTUP = startup_stm32f7xx.mk
+  # next file is included through Contrib's platform.ml
+  #CPU_PLATFORM = $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/platform.mk
+  CPU_PLATFORM = ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/STM32F7xx/platform.mk
+  CPU_HWLAYER = ports/stm32/stm32f7
 else ifeq ($(PROJECT_CPU),ARCH_STM32F4)
-	CPU_STARTUP = startup_stm32f4xx.mk
-	# next file is included through Contrib's platform.ml
-	#CPU_PLATFORM = $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk
-	CPU_PLATFORM = ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/STM32F4xx/platform.mk
-	CPU_HWLAYER = ports/stm32/stm32f4
+  CPU_STARTUP = startup_stm32f4xx.mk
+  # next file is included through Contrib's platform.ml
+  #CPU_PLATFORM = $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk
+  CPU_PLATFORM = ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/STM32F4xx/platform.mk
+  CPU_HWLAYER = ports/stm32/stm32f4
 else ifeq ($(PROJECT_CPU),ARCH_STM32H7)
-	CPU_STARTUP = startup_stm32h7xx.mk
-	# next file is included through Contrib's platform.ml
-	#CPU_PLATFORM = $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/platform.mk
-	CPU_PLATFORM = ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/STM32H7xx/platform.mk
-	CPU_HWLAYER = ports/stm32/stm32h7
+  CPU_STARTUP = startup_stm32h7xx.mk
+  # next file is included through Contrib's platform.ml
+  #CPU_PLATFORM = $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/platform.mk
+  CPU_PLATFORM = ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/STM32H7xx/platform.mk
+  CPU_HWLAYER = ports/stm32/stm32h7
 else ifeq ($(PROJECT_CPU),ARCH_AT32F4)
-	CPU_STARTUP = startup_at32f4xx.mk
-	CPU_PLATFORM = $(CHIBIOS)/os/hal/ports/AT32/AT32F4xx/platform.mk
-	# Reuse STM32F4 port
-	CPU_HWLAYER = ports/stm32/stm32f4
+  CPU_STARTUP = startup_at32f4xx.mk
+  CPU_PLATFORM = $(CHIBIOS)/os/hal/ports/AT32/AT32F4xx/platform.mk
+  # Reuse STM32F4 port
+  CPU_HWLAYER = ports/stm32/stm32f4
 else ifeq ($(PROJECT_CPU),custom_platform)
-	include $(BOARD_DIR)/custom_platform.mk
-	$(info Using custom CPU_STARTUP_DIR $(CPU_STARTUP_DIR))
-	$(info Using custom CPU_PLATFORM $(CPU_PLATFORM))
-	$(info Using custom CPU_HWLAYER $(CPU_HWLAYER))
+  include $(BOARD_DIR)/custom_platform.mk
+  $(info Using custom CPU_STARTUP_DIR $(CPU_STARTUP_DIR))
+  $(info Using custom CPU_PLATFORM $(CPU_PLATFORM))
+  $(info Using custom CPU_HWLAYER $(CPU_HWLAYER))
 else ifeq ($(PROJECT_CPU),simulator)
 else
 $(error Unexpected PROJECT_CPU [$(PROJECT_CPU)])