mirror of https://github.com/rusefi/rusefi.git
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This commit is contained in:
rusEfi
parent
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commit
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|
|
@ -205,7 +205,7 @@
|
|||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry excluding="chibios/os/ports/GCC/ARMCMx/STM32F1xx|chibios/os/hal/platforms/STM32F1xx|chibios/boards/ST_NUCLEO_F103RB|config/stm32f0egt|egt2can.cpp|chibios/boards/simulator|chibios/boards/OLIMEX_STM32_E407|chibios/boards/ST_STM32F0_DISCOVERY|chibios/os/ports/GCC/ARMCMx/STM32F0xx|hw_layer/stm32f0|chibios/os/hal/platforms/STM32/I2Cv2|chibios/os/hal/platforms/STM32/SPIv2|chibios/os/hal/platforms/STM32/USARTv2|chibios/os/ports/IAR|chibios/os/hal/platforms/STM32F0xx|chibios/os/hal/platforms/Win32|chibios/os/ports/GCC/ARMCMx/chcore_v6m.c|chibios/os/ports/GCC/SIMIA32|chibios/os/ports/IAR/ARMCMx/chcore_v6m.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
<entry excluding="chibios/os/hal/platforms/STM32/RTCv1|chibios/os/hal/platforms/STM32/GPIOv1|chibios/os/ports/GCC/ARMCMx/STM32F1xx|chibios/os/hal/platforms/STM32F1xx|chibios/boards/ST_NUCLEO_F103RB|config/stm32f0egt|egt2can.cpp|chibios/boards/simulator|chibios/boards/OLIMEX_STM32_E407|chibios/boards/ST_STM32F0_DISCOVERY|chibios/os/ports/GCC/ARMCMx/STM32F0xx|hw_layer/stm32f0|chibios/os/hal/platforms/STM32/I2Cv2|chibios/os/hal/platforms/STM32/SPIv2|chibios/os/hal/platforms/STM32/USARTv2|chibios/os/ports/IAR|chibios/os/hal/platforms/STM32F0xx|chibios/os/hal/platforms/Win32|chibios/os/ports/GCC/ARMCMx/chcore_v6m.c|chibios/os/ports/GCC/SIMIA32|chibios/os/ports/IAR/ARMCMx/chcore_v6m.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
|
|
@ -288,7 +288,7 @@
|
|||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry excluding="chibios/os/ports/GCC/ARMCMx/STM32F1xx|chibios/os/hal/platforms/STM32F1xx|chibios/boards/ST_NUCLEO_F103RB|config/stm32f0egt|egt2can.cpp|chibios/boards/simulator|chibios/boards/OLIMEX_STM32_E407|chibios/boards/ST_STM32F0_DISCOVERY|chibios/os/ports/GCC/ARMCMx/STM32F0xx|hw_layer/stm32f0|chibios/os/hal/platforms/STM32/I2Cv2|chibios/os/hal/platforms/STM32/SPIv2|chibios/os/hal/platforms/STM32/USARTv2|chibios/os/ports/IAR|chibios/os/hal/platforms/STM32F0xx|chibios/os/hal/platforms/Win32|chibios/os/ports/GCC/ARMCMx/chcore_v6m.c|chibios/os/ports/GCC/SIMIA32|chibios/os/ports/IAR/ARMCMx/chcore_v6m.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
<entry excluding="chibios/os/hal/platforms/STM32/RTCv1|chibios/os/hal/platforms/STM32/GPIOv1|chibios/os/ports/GCC/ARMCMx/STM32F1xx|chibios/os/hal/platforms/STM32F1xx|chibios/boards/ST_NUCLEO_F103RB|config/stm32f0egt|egt2can.cpp|chibios/boards/simulator|chibios/boards/OLIMEX_STM32_E407|chibios/boards/ST_STM32F0_DISCOVERY|chibios/os/ports/GCC/ARMCMx/STM32F0xx|hw_layer/stm32f0|chibios/os/hal/platforms/STM32/I2Cv2|chibios/os/hal/platforms/STM32/SPIv2|chibios/os/hal/platforms/STM32/USARTv2|chibios/os/ports/IAR|chibios/os/hal/platforms/STM32F0xx|chibios/os/hal/platforms/Win32|chibios/os/ports/GCC/ARMCMx/chcore_v6m.c|chibios/os/ports/GCC/SIMIA32|chibios/os/ports/IAR/ARMCMx/chcore_v6m.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,184 @@
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|||
/*
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||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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||||
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||||
Licensed under the Apache License, Version 2.0 (the "License");
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||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
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||||
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||||
/**
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||||
* @file STM32/GPIOv1/pal_lld.c
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* @brief STM32F1xx GPIO low level driver code.
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*
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* @addtogroup PAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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||||
/* Driver local definitions. */
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/*===========================================================================*/
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#if STM32_HAS_GPIOG
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#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
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RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
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RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \
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RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN)
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#elif STM32_HAS_GPIOE
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#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
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RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
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RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN)
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#else
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#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
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RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
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RCC_APB2ENR_AFIOEN)
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#endif
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||||
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||||
/*===========================================================================*/
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||||
/* Driver exported variables. */
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||||
/*===========================================================================*/
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||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
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||||
/*===========================================================================*/
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||||
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||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
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||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
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||||
/*===========================================================================*/
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||||
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||||
/*===========================================================================*/
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||||
/* Driver exported functions. */
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||||
/*===========================================================================*/
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||||
/**
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* @brief STM32 I/O ports configuration.
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* @details Ports A-D(E, F, G) clocks enabled, AFIO clock enabled.
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*
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* @param[in] config the STM32 ports configuration
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*
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* @notapi
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*/
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void _pal_lld_init(const PALConfig *config) {
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/*
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* Enables the GPIO related clocks.
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*/
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rccEnableAPB2(APB2_EN_MASK, FALSE);
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/*
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* Initial GPIO setup.
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*/
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GPIOA->ODR = config->PAData.odr;
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GPIOA->CRH = config->PAData.crh;
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GPIOA->CRL = config->PAData.crl;
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GPIOB->ODR = config->PBData.odr;
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GPIOB->CRH = config->PBData.crh;
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GPIOB->CRL = config->PBData.crl;
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GPIOC->ODR = config->PCData.odr;
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GPIOC->CRH = config->PCData.crh;
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GPIOC->CRL = config->PCData.crl;
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GPIOD->ODR = config->PDData.odr;
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GPIOD->CRH = config->PDData.crh;
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GPIOD->CRL = config->PDData.crl;
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#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
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GPIOE->ODR = config->PEData.odr;
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GPIOE->CRH = config->PEData.crh;
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GPIOE->CRL = config->PEData.crl;
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#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
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GPIOF->ODR = config->PFData.odr;
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GPIOF->CRH = config->PFData.crh;
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GPIOF->CRL = config->PFData.crl;
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#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
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GPIOG->ODR = config->PGData.odr;
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GPIOG->CRH = config->PGData.crh;
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GPIOG->CRL = config->PGData.crl;
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#endif
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#endif
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#endif
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}
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/**
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* @brief Pads mode setup.
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* @details This function programs a pads group belonging to the same port
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* with the specified mode.
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* @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz.
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* @note Writing on pads programmed as pull-up or pull-down has the side
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* effect to modify the resistor setting because the output latched
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* data is used for the resistor selection.
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*
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* @param[in] port the port identifier
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* @param[in] mask the group mask
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* @param[in] mode the mode
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*
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* @notapi
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||||
*/
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void _pal_lld_setgroupmode(ioportid_t port,
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ioportmask_t mask,
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iomode_t mode) {
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static const uint8_t cfgtab[] = {
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4, /* PAL_MODE_RESET, implemented as input.*/
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2, /* PAL_MODE_UNCONNECTED, implemented as push pull output 2MHz.*/
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4, /* PAL_MODE_INPUT */
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8, /* PAL_MODE_INPUT_PULLUP */
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8, /* PAL_MODE_INPUT_PULLDOWN */
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0, /* PAL_MODE_INPUT_ANALOG */
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3, /* PAL_MODE_OUTPUT_PUSHPULL, 50MHz.*/
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7, /* PAL_MODE_OUTPUT_OPENDRAIN, 50MHz.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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0xB, /* PAL_MODE_STM32_ALTERNATE_PUSHPULL, 50MHz.*/
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0xF, /* PAL_MODE_STM32_ALTERNATE_OPENDRAIN, 50MHz.*/
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};
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uint32_t mh, ml, crh, crl, cfg;
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unsigned i;
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if (mode == PAL_MODE_INPUT_PULLUP)
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port->BSRR = mask;
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else if (mode == PAL_MODE_INPUT_PULLDOWN)
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port->BRR = mask;
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cfg = cfgtab[mode];
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mh = ml = crh = crl = 0;
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for (i = 0; i < 8; i++) {
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ml <<= 4;
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mh <<= 4;
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crl <<= 4;
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crh <<= 4;
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if ((mask & 0x0080) == 0)
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ml |= 0xf;
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||||
else
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crl |= cfg;
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if ((mask & 0x8000) == 0)
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mh |= 0xf;
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else
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crh |= cfg;
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mask <<= 1;
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}
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port->CRH = (port->CRH & mh) | crh;
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port->CRL = (port->CRL & ml) | crl;
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}
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||||
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#endif /* HAL_USE_PAL */
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||||
|
||||
/** @} */
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||||
|
|
@ -0,0 +1,334 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32/GPIOv1/pal_lld.h
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||||
* @brief STM32F1xx GPIO low level driver header.
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||||
*
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* @addtogroup PAL
|
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* @{
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||||
*/
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||||
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||||
#ifndef _PAL_LLD_H_
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#define _PAL_LLD_H_
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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||||
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/*===========================================================================*/
|
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/* Unsupported modes and specific modes */
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/*===========================================================================*/
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|
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/**
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* @name STM32-specific I/O mode flags
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* @{
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||||
*/
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||||
/**
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* @brief STM32 specific alternate push-pull output mode.
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*/
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#define PAL_MODE_STM32_ALTERNATE_PUSHPULL 16
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/**
|
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* @brief STM32 specific alternate open-drain output mode.
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*/
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#define PAL_MODE_STM32_ALTERNATE_OPENDRAIN 17
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/** @} */
|
||||
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/*===========================================================================*/
|
||||
/* I/O Ports Types and constants. */
|
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/*===========================================================================*/
|
||||
|
||||
/**
|
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* @brief GPIO port setup info.
|
||||
*/
|
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typedef struct {
|
||||
/** Initial value for ODR register.*/
|
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uint32_t odr;
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/** Initial value for CRL register.*/
|
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uint32_t crl;
|
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/** Initial value for CRH register.*/
|
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uint32_t crh;
|
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} stm32_gpio_setup_t;
|
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|
||||
/**
|
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* @brief STM32 GPIO static initializer.
|
||||
* @details An instance of this structure must be passed to @p palInit() at
|
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* system startup time in order to initialize the digital I/O
|
||||
* subsystem. This represents only the initial setup, specific pads
|
||||
* or whole ports can be reprogrammed at later time.
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||||
*/
|
||||
typedef struct {
|
||||
/** @brief Port A setup data.*/
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||||
stm32_gpio_setup_t PAData;
|
||||
/** @brief Port B setup data.*/
|
||||
stm32_gpio_setup_t PBData;
|
||||
/** @brief Port C setup data.*/
|
||||
stm32_gpio_setup_t PCData;
|
||||
/** @brief Port D setup data.*/
|
||||
stm32_gpio_setup_t PDData;
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
/** @brief Port E setup data.*/
|
||||
stm32_gpio_setup_t PEData;
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
/** @brief Port F setup data.*/
|
||||
stm32_gpio_setup_t PFData;
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
/** @brief Port G setup data.*/
|
||||
stm32_gpio_setup_t PGData;
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
} PALConfig;
|
||||
|
||||
/**
|
||||
* @brief Width, in bits, of an I/O port.
|
||||
*/
|
||||
#define PAL_IOPORTS_WIDTH 16
|
||||
|
||||
/**
|
||||
* @brief Whole port mask.
|
||||
* @details This macro specifies all the valid bits into a port.
|
||||
*/
|
||||
#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
|
||||
|
||||
/**
|
||||
* @brief Digital I/O port sized unsigned type.
|
||||
*/
|
||||
typedef uint32_t ioportmask_t;
|
||||
|
||||
/**
|
||||
* @brief Digital I/O modes.
|
||||
*/
|
||||
typedef uint32_t iomode_t;
|
||||
|
||||
/**
|
||||
* @brief Port Identifier.
|
||||
* @details This type can be a scalar or some kind of pointer, do not make
|
||||
* any assumption about it, use the provided macros when populating
|
||||
* variables of this type.
|
||||
*/
|
||||
typedef GPIO_TypeDef * ioportid_t;
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I/O Ports Identifiers. */
|
||||
/* The low level driver wraps the definitions already present in the STM32 */
|
||||
/* firmware library. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief GPIO port A identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
#define IOPORT1 GPIOA
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port B identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
#define IOPORT2 GPIOB
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port C identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
#define IOPORT3 GPIOC
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port D identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
#define IOPORT4 GPIOD
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port E identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
#define IOPORT5 GPIOE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port F identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
#define IOPORT6 GPIOF
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port G identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
#define IOPORT7 GPIOG
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Implementation, some of the following macros could be implemented as */
|
||||
/* functions, if so please put them in pal_lld.c. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief GPIO ports subsystem initialization.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_init(config) _pal_lld_init(config)
|
||||
|
||||
/**
|
||||
* @brief Reads an I/O port.
|
||||
* @details This function is implemented by reading the GPIO IDR register, the
|
||||
* implementation has no side effects.
|
||||
* @note This function is not meant to be invoked directly by the application
|
||||
* code.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @return The port bits.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_readport(port) ((port)->IDR)
|
||||
|
||||
/**
|
||||
* @brief Reads the output latch.
|
||||
* @details This function is implemented by reading the GPIO ODR register, the
|
||||
* implementation has no side effects.
|
||||
* @note This function is not meant to be invoked directly by the application
|
||||
* code.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @return The latched logical states.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_readlatch(port) ((port)->ODR)
|
||||
|
||||
/**
|
||||
* @brief Writes on a I/O port.
|
||||
* @details This function is implemented by writing the GPIO ODR register, the
|
||||
* implementation has no side effects.
|
||||
* @note Writing on pads programmed as pull-up or pull-down has the side
|
||||
* effect to modify the resistor setting because the output latched
|
||||
* data is used for the resistor selection.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] bits bits to be written on the specified port
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
|
||||
|
||||
/**
|
||||
* @brief Sets a bits mask on a I/O port.
|
||||
* @details This function is implemented by writing the GPIO BSRR register, the
|
||||
* implementation has no side effects.
|
||||
* @note Writing on pads programmed as pull-up or pull-down has the side
|
||||
* effect to modify the resistor setting because the output latched
|
||||
* data is used for the resistor selection.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] bits bits to be ORed on the specified port
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_setport(port, bits) ((port)->BSRR = (bits))
|
||||
|
||||
/**
|
||||
* @brief Clears a bits mask on a I/O port.
|
||||
* @details This function is implemented by writing the GPIO BRR register, the
|
||||
* implementation has no side effects.
|
||||
* @note Writing on pads programmed as pull-up or pull-down has the side
|
||||
* effect to modify the resistor setting because the output latched
|
||||
* data is used for the resistor selection.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] bits bits to be cleared on the specified port
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_clearport(port, bits) ((port)->BRR = (bits))
|
||||
|
||||
/**
|
||||
* @brief Writes a group of bits.
|
||||
* @details This function is implemented by writing the GPIO BSRR register, the
|
||||
* implementation has no side effects.
|
||||
* @note Writing on pads programmed as pull-up or pull-down has the side
|
||||
* effect to modify the resistor setting because the output latched
|
||||
* data is used for the resistor selection.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] mask group mask
|
||||
* @param[in] offset the group bit offset within the port
|
||||
* @param[in] bits bits to be written. Values exceeding the group
|
||||
* width are masked.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_writegroup(port, mask, offset, bits) \
|
||||
((port)->BSRR = ((~(bits) & (mask)) << (16 + (offset))) | \
|
||||
(((bits) & (mask)) << (offset)))
|
||||
|
||||
/**
|
||||
* @brief Pads group mode setup.
|
||||
* @details This function programs a pads group belonging to the same port
|
||||
* with the specified mode.
|
||||
* @note Writing on pads programmed as pull-up or pull-down has the side
|
||||
* effect to modify the resistor setting because the output latched
|
||||
* data is used for the resistor selection.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] mask group mask
|
||||
* @param[in] offset group bit offset within the port
|
||||
* @param[in] mode group mode
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_setgroupmode(port, mask, offset, mode) \
|
||||
_pal_lld_setgroupmode(port, mask << offset, mode)
|
||||
|
||||
/**
|
||||
* @brief Writes a logical state on an output pad.
|
||||
* @note Writing on pads programmed as pull-up or pull-down has the side
|
||||
* effect to modify the resistor setting because the output latched
|
||||
* data is used for the resistor selection.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] pad pad number within the port
|
||||
* @param[in] bit logical value, the value must be @p PAL_LOW or
|
||||
* @p PAL_HIGH
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
|
||||
|
||||
extern const PALConfig pal_default_config;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void _pal_lld_init(const PALConfig *config);
|
||||
void _pal_lld_setgroupmode(ioportid_t port,
|
||||
ioportmask_t mask,
|
||||
iomode_t mode);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_PAL */
|
||||
|
||||
#endif /* _PAL_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,329 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
/*
|
||||
Concepts and parts of this file have been contributed by Uladzimir Pylinsky
|
||||
aka barthess.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32/RTCv1/rtc_lld.c
|
||||
* @brief STM32 RTC subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
|
||||
#if HAL_USE_RTC || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief RTC driver identifier.
|
||||
*/
|
||||
RTCDriver RTCD1;
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Wait for synchronization of RTC registers with APB1 bus.
|
||||
* @details This function must be invoked before trying to read RTC registers
|
||||
* in the backup domain: DIV, CNT, ALR. CR registers can always
|
||||
* be read.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define rtc_lld_apb1_sync() {while ((RTC->CRL & RTC_CRL_RSF) == 0);}
|
||||
|
||||
/**
|
||||
* @brief Wait for for previous write operation complete.
|
||||
* @details This function must be invoked before writing to any RTC registers
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define rtc_lld_wait_write() {while ((RTC->CRL & RTC_CRL_RTOFF) == 0);}
|
||||
|
||||
/**
|
||||
* @brief Acquires write access to RTC registers.
|
||||
* @details Before writing to the backup domain RTC registers the previous
|
||||
* write operation must be completed. Use this function before
|
||||
* writing to PRL, CNT, ALR registers.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define rtc_lld_acquire() {rtc_lld_wait_write(); RTC->CRL |= RTC_CRL_CNF;}
|
||||
|
||||
/**
|
||||
* @brief Releases write access to RTC registers.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define rtc_lld_release() {RTC->CRL &= ~RTC_CRL_CNF;}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief RTC interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(RTC_IRQHandler) {
|
||||
uint16_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
/* This wait works only when AHB1 bus was previously powered off by any
|
||||
reason (standby, reset, etc). In other cases it does nothing.*/
|
||||
rtc_lld_apb1_sync();
|
||||
|
||||
/* Mask of all enabled and pending sources.*/
|
||||
flags = RTC->CRH & RTC->CRL;
|
||||
RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF);
|
||||
|
||||
if (flags & RTC_CRL_SECF)
|
||||
RTCD1.callback(&RTCD1, RTC_EVENT_SECOND);
|
||||
|
||||
if (flags & RTC_CRL_ALRF)
|
||||
RTCD1.callback(&RTCD1, RTC_EVENT_ALARM);
|
||||
|
||||
if (flags & RTC_CRL_OWF)
|
||||
RTCD1.callback(&RTCD1, RTC_EVENT_OVERFLOW);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Load value of RTCCLK to prescaler registers.
|
||||
* @note The pre-scaler must not be set on every reset as RTC clock
|
||||
* counts are lost when it is set.
|
||||
* @note This function designed to be called from
|
||||
* hal_lld_backup_domain_init(). Because there is only place
|
||||
* where possible to detect BKP domain reset event reliably.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void rtc_lld_set_prescaler(void){
|
||||
rtc_lld_acquire();
|
||||
RTC->PRLH = (uint16_t)((STM32_RTCCLK - 1) >> 16) & 0x000F;
|
||||
RTC->PRLL = (uint16_t)(((STM32_RTCCLK - 1)) & 0xFFFF);
|
||||
rtc_lld_release();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize RTC.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void rtc_lld_init(void){
|
||||
|
||||
/* RSF bit must be cleared by software after an APB1 reset or an APB1 clock
|
||||
stop. Otherwise its value will not be actual. */
|
||||
RTC->CRL &= ~RTC_CRL_RSF;
|
||||
|
||||
/* Required because access to PRL.*/
|
||||
rtc_lld_apb1_sync();
|
||||
|
||||
/* All interrupts initially disabled.*/
|
||||
rtc_lld_wait_write();
|
||||
RTC->CRH = 0;
|
||||
|
||||
/* Callback initially disabled.*/
|
||||
RTCD1.callback = NULL;
|
||||
|
||||
/* IRQ vector permanently assigned to this driver.*/
|
||||
nvicEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set current time.
|
||||
* @note Fractional part will be silently ignored. There is no possibility
|
||||
* to change it on STM32F1xx platform.
|
||||
*
|
||||
* @param[in] rtcp pointer to RTC driver structure
|
||||
* @param[in] timespec pointer to a @p RTCTime structure
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) {
|
||||
|
||||
(void)rtcp;
|
||||
|
||||
rtc_lld_acquire();
|
||||
RTC->CNTH = (uint16_t)(timespec->tv_sec >> 16);
|
||||
RTC->CNTL = (uint16_t)(timespec->tv_sec & 0xFFFF);
|
||||
rtc_lld_release();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get current time.
|
||||
*
|
||||
* @param[in] rtcp pointer to RTC driver structure
|
||||
* @param[in] timespec pointer to a @p RTCTime structure
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) {
|
||||
(void)rtcp;
|
||||
|
||||
uint32_t time_frac;
|
||||
|
||||
/* Required because access to CNT and DIV.*/
|
||||
rtc_lld_apb1_sync();
|
||||
|
||||
/* Loops until two consecutive read returning the same value.*/
|
||||
do {
|
||||
timespec->tv_sec = ((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL;
|
||||
time_frac = (((uint32_t)RTC->DIVH) << 16) + (uint32_t)RTC->DIVL;
|
||||
} while ((timespec->tv_sec) != (((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL));
|
||||
|
||||
timespec->tv_msec = (uint16_t)(((STM32_RTCCLK - 1 - time_frac) * 1000) /
|
||||
STM32_RTCCLK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set alarm time.
|
||||
*
|
||||
* @note Default value after BKP domain reset is 0xFFFFFFFF
|
||||
*
|
||||
* @param[in] rtcp pointer to RTC driver structure
|
||||
* @param[in] alarm alarm identifier
|
||||
* @param[in] alarmspec pointer to a @p RTCAlarm structure
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void rtc_lld_set_alarm(RTCDriver *rtcp,
|
||||
rtcalarm_t alarm,
|
||||
const RTCAlarm *alarmspec) {
|
||||
|
||||
(void)rtcp;
|
||||
(void)alarm;
|
||||
|
||||
rtc_lld_acquire();
|
||||
if (alarmspec != NULL) {
|
||||
RTC->ALRH = (uint16_t)(alarmspec->tv_sec >> 16);
|
||||
RTC->ALRL = (uint16_t)(alarmspec->tv_sec & 0xFFFF);
|
||||
}
|
||||
else {
|
||||
RTC->ALRH = 0;
|
||||
RTC->ALRL = 0;
|
||||
}
|
||||
rtc_lld_release();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get current alarm.
|
||||
* @note If an alarm has not been set then the returned alarm specification
|
||||
* is not meaningful.
|
||||
*
|
||||
* @note Default value after BKP domain reset is 0xFFFFFFFF.
|
||||
*
|
||||
* @param[in] rtcp pointer to RTC driver structure
|
||||
* @param[in] alarm alarm identifier
|
||||
* @param[out] alarmspec pointer to a @p RTCAlarm structure
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void rtc_lld_get_alarm(RTCDriver *rtcp,
|
||||
rtcalarm_t alarm,
|
||||
RTCAlarm *alarmspec) {
|
||||
|
||||
(void)rtcp;
|
||||
(void)alarm;
|
||||
|
||||
/* Required because access to ALR.*/
|
||||
rtc_lld_apb1_sync();
|
||||
|
||||
alarmspec->tv_sec = ((RTC->ALRH << 16) + RTC->ALRL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables RTC callbacks.
|
||||
* @details This function enables or disables callbacks, use a @p NULL pointer
|
||||
* in order to disable a callback.
|
||||
*
|
||||
* @param[in] rtcp pointer to RTC driver structure
|
||||
* @param[in] callback callback function pointer or @p NULL
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
|
||||
|
||||
if (callback != NULL) {
|
||||
|
||||
/* IRQ sources enabled only after setting up the callback.*/
|
||||
rtcp->callback = callback;
|
||||
|
||||
rtc_lld_wait_write();
|
||||
RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF);
|
||||
RTC->CRH = RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE;
|
||||
}
|
||||
else {
|
||||
rtc_lld_wait_write();
|
||||
RTC->CRH = 0;
|
||||
|
||||
/* Callback set to NULL only after disabling the IRQ sources.*/
|
||||
rtcp->callback = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
#include "chrtclib.h"
|
||||
|
||||
/**
|
||||
* @brief Get current time in format suitable for usage in FatFS.
|
||||
*
|
||||
* @param[in] rtcp pointer to RTC driver structure
|
||||
* @return FAT time value.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp) {
|
||||
uint32_t fattime;
|
||||
struct tm timp;
|
||||
|
||||
rtcGetTimeTm(rtcp, &timp);
|
||||
|
||||
fattime = (timp.tm_sec) >> 1;
|
||||
fattime |= (timp.tm_min) << 5;
|
||||
fattime |= (timp.tm_hour) << 11;
|
||||
fattime |= (timp.tm_mday) << 16;
|
||||
fattime |= (timp.tm_mon + 1) << 21;
|
||||
fattime |= (timp.tm_year - 80) << 25;
|
||||
|
||||
return fattime;
|
||||
}
|
||||
#endif /* HAL_USE_RTC */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,187 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
/*
|
||||
Concepts and parts of this file have been contributed by Uladzimir Pylinsky
|
||||
aka barthess.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32/RTCv1/rtc_lld.h
|
||||
* @brief STM32F1xx RTC subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _RTC_LLD_H_
|
||||
#define _RTC_LLD_H_
|
||||
|
||||
#if HAL_USE_RTC || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief This RTC implementation supports callbacks.
|
||||
*/
|
||||
#define RTC_SUPPORTS_CALLBACKS TRUE
|
||||
|
||||
/**
|
||||
* @brief One alarm comparator available.
|
||||
*/
|
||||
#define RTC_ALARMS 1
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_IRQ_PRIORITY 15
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if HAL_USE_RTC && !STM32_HAS_RTC
|
||||
#error "RTC not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_RTCCLK == 0
|
||||
#error "RTC clock not enabled"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Type of a structure representing an RTC alarm time stamp.
|
||||
*/
|
||||
typedef struct RTCAlarm RTCAlarm;
|
||||
|
||||
/**
|
||||
* @brief Type of a structure representing an RTC callbacks config.
|
||||
*/
|
||||
typedef struct RTCCallbackConfig RTCCallbackConfig;
|
||||
|
||||
/**
|
||||
* @brief Type of an RTC alarm.
|
||||
* @details Meaningful on platforms with more than 1 alarm comparator.
|
||||
*/
|
||||
typedef uint32_t rtcalarm_t;
|
||||
|
||||
/**
|
||||
* @brief Type of an RTC event.
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_EVENT_SECOND = 0, /** Triggered every second. */
|
||||
RTC_EVENT_ALARM = 1, /** Triggered on alarm. */
|
||||
RTC_EVENT_OVERFLOW = 2 /** Triggered on counter overflow. */
|
||||
} rtcevent_t;
|
||||
|
||||
/**
|
||||
* @brief Type of a generic RTC callback.
|
||||
*/
|
||||
typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event);
|
||||
|
||||
/**
|
||||
* @brief Structure representing an RTC callbacks config.
|
||||
*/
|
||||
struct RTCCallbackConfig{
|
||||
/**
|
||||
* @brief Generic RTC callback pointer.
|
||||
*/
|
||||
rtccb_t callback;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Structure representing an RTC time stamp.
|
||||
*/
|
||||
struct RTCTime {
|
||||
/**
|
||||
* @brief Seconds since UNIX epoch.
|
||||
*/
|
||||
uint32_t tv_sec;
|
||||
/**
|
||||
* @brief Fractional part.
|
||||
*/
|
||||
uint32_t tv_msec;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Structure representing an RTC alarm time stamp.
|
||||
*/
|
||||
struct RTCAlarm {
|
||||
/**
|
||||
* @brief Seconds since UNIX epoch.
|
||||
*/
|
||||
uint32_t tv_sec;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Structure representing an RTC driver.
|
||||
*/
|
||||
struct RTCDriver{
|
||||
/**
|
||||
* @brief Callback pointer.
|
||||
*/
|
||||
rtccb_t callback;
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
extern RTCDriver RTCD1;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void rtc_lld_set_prescaler(void);
|
||||
void rtc_lld_init(void);
|
||||
void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec);
|
||||
void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec);
|
||||
void rtc_lld_set_alarm(RTCDriver *rtcp,
|
||||
rtcalarm_t alarm,
|
||||
const RTCAlarm *alarmspec);
|
||||
void rtc_lld_get_alarm(RTCDriver *rtcp,
|
||||
rtcalarm_t alarm,
|
||||
RTCAlarm *alarmspec);
|
||||
void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback);
|
||||
uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_RTC */
|
||||
|
||||
#endif /* _RTC_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
Loading…
Reference in New Issue