From d1ac9add2ea3f6d0ad17fc223c69b04d167e3f8d Mon Sep 17 00:00:00 2001 From: rusEfi Date: Sat, 6 Dec 2014 09:03:23 -0600 Subject: [PATCH] auto-sync --- hardware/soic8_breakout/soic8_breakout.cmp | 24 ++ .../soic8_breakout/soic8_breakout.kicad_pcb | 236 ++++++++++++++++++ hardware/soic8_breakout/soic8_breakout.net | 81 ++++++ hardware/soic8_breakout/soic8_breakout.pro | 86 +++++++ hardware/soic8_breakout/soic8_breakout.sch | 99 ++++++++ 5 files changed, 526 insertions(+) create mode 100644 hardware/soic8_breakout/soic8_breakout.cmp create mode 100644 hardware/soic8_breakout/soic8_breakout.kicad_pcb create mode 100644 hardware/soic8_breakout/soic8_breakout.net create mode 100644 hardware/soic8_breakout/soic8_breakout.pro create mode 100644 hardware/soic8_breakout/soic8_breakout.sch diff --git a/hardware/soic8_breakout/soic8_breakout.cmp b/hardware/soic8_breakout/soic8_breakout.cmp new file mode 100644 index 0000000000..dcb7dd04bf --- /dev/null +++ b/hardware/soic8_breakout/soic8_breakout.cmp @@ -0,0 +1,24 @@ +Cmp-Mod V01 Created by CvPcb (2013-07-07 BZR 4022)-stable date = 06/12/2014 09:24:36 + +BeginCmp +TimeStamp = /54830CC1; +Reference = P1; +ValeurCmp = CONN_4; +IdModule = SIL-4; +EndCmp + +BeginCmp +TimeStamp = /54830CCE; +Reference = P2; +ValeurCmp = CONN_4; +IdModule = SIL-4; +EndCmp + +BeginCmp +TimeStamp = /54830CB2; +Reference = U1; +ValeurCmp = XTR116U; +IdModule = so-8; +EndCmp + +EndListe diff --git a/hardware/soic8_breakout/soic8_breakout.kicad_pcb b/hardware/soic8_breakout/soic8_breakout.kicad_pcb new file mode 100644 index 0000000000..f22a04b6f4 --- /dev/null +++ b/hardware/soic8_breakout/soic8_breakout.kicad_pcb @@ -0,0 +1,236 @@ +(kicad_pcb (version 3) (host pcbnew "(2013-07-07 BZR 4022)-stable") + + (general + (links 4) + (no_connects 4) + (area 94.907099 69.40169 106.641901 111.467901) + (thickness 1.6) + (drawings 0) + (tracks 0) + (zones 0) + (modules 3) + (nets 5) + ) + + (page A3) + (layers + (15 F.Cu signal) + (0 B.Cu signal) + (16 B.Adhes user) + (17 F.Adhes user) + (18 B.Paste user) + (19 F.Paste user) + (20 B.SilkS user) + (21 F.SilkS user) + (22 B.Mask user) + (23 F.Mask user) + (24 Dwgs.User user) + (25 Cmts.User user) + (26 Eco1.User user) + (27 Eco2.User user) + (28 Edge.Cuts user) + ) + + (setup + (last_trace_width 0.254) + (trace_clearance 0.254) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.254) + (segment_width 0.2) + (edge_width 0.1) + (via_size 0.889) + (via_drill 0.635) + (via_min_size 0.889) + (via_min_drill 0.508) + (uvia_size 0.508) + (uvia_drill 0.127) + (uvias_allowed no) + (uvia_min_size 0.508) + (uvia_min_drill 0.127) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.5 1.5) + (pad_drill 0.6) + (pad_to_mask_clearance 0) + (aux_axis_origin 0 0) + (visible_elements FFFFFBBF) + (pcbplotparams + (layerselection 3178497) + (usegerberextensions true) + (excludeedgelayer true) + (linewidth 0.150000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15) + (hpglpenoverlay 2) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotothertext true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 N-000003) + (net 2 N-000006) + (net 3 N-000007) + (net 4 N-000008) + + (net_class Default "This is the default net class." + (clearance 0.254) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.635) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net "") + (add_net N-000003) + (add_net N-000006) + (add_net N-000007) + (add_net N-000008) + ) + + (module so-8 (layer F.Cu) (tedit 48A6C16E) (tstamp 548311C3) + (at 100.5205 87.884 180) + (descr SO-8) + (path /54830CB2) + (attr smd) + (fp_text reference U1 (at 0 -1.016 180) (layer F.SilkS) + (effects (font (size 0.7493 0.7493) (thickness 0.14986))) + ) + (fp_text value XTR116U (at 0 1.016 180) (layer F.SilkS) + (effects (font (size 0.7493 0.7493) (thickness 0.14986))) + ) + (fp_line (start -2.413 -1.9812) (end -2.413 1.9812) (layer F.SilkS) (width 0.127)) + (fp_line (start -2.413 1.9812) (end 2.413 1.9812) (layer F.SilkS) (width 0.127)) + (fp_line (start 2.413 1.9812) (end 2.413 -1.9812) (layer F.SilkS) (width 0.127)) + (fp_line (start 2.413 -1.9812) (end -2.413 -1.9812) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.9812) (end -1.905 -3.0734) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.635 -1.9812) (end -0.635 -3.0734) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.635 -1.9812) (end 0.635 -3.0734) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -3.0734) (end 1.905 -1.9812) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 1.9812) (end 1.905 3.0734) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.635 3.0734) (end 0.635 1.9812) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.635 3.0734) (end -0.635 1.9812) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 3.0734) (end -1.905 1.9812) (layer F.SilkS) (width 0.127)) + (fp_circle (center -1.6764 1.2446) (end -1.9558 1.6256) (layer F.SilkS) (width 0.127)) + (pad 1 smd rect (at -1.905 2.794 180) (size 0.635 1.27) + (layers F.Cu F.Paste F.Mask) + (net 4 N-000008) + ) + (pad 2 smd rect (at -0.635 2.794 180) (size 0.635 1.27) + (layers F.Cu F.Paste F.Mask) + (net 3 N-000007) + ) + (pad 3 smd rect (at 0.635 2.794 180) (size 0.635 1.27) + (layers F.Cu F.Paste F.Mask) + (net 2 N-000006) + ) + (pad 4 smd rect (at 1.905 2.794 180) (size 0.635 1.27) + (layers F.Cu F.Paste F.Mask) + ) + (pad 5 smd rect (at 1.905 -2.794 180) (size 0.635 1.27) + (layers F.Cu F.Paste F.Mask) + ) + (pad 6 smd rect (at 0.635 -2.794 180) (size 0.635 1.27) + (layers F.Cu F.Paste F.Mask) + (net 1 N-000003) + ) + (pad 7 smd rect (at -0.635 -2.794 180) (size 0.635 1.27) + (layers F.Cu F.Paste F.Mask) + ) + (pad 8 smd rect (at -1.905 -2.794 180) (size 0.635 1.27) + (layers F.Cu F.Paste F.Mask) + ) + (model smd/smd_dil/so-8.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module SIL-4 (layer F.Cu) (tedit 200000) (tstamp 548311D2) + (at 100.33 75.565 180) + (descr "Connecteur 4 pibs") + (tags "CONN DEV") + (path /54830CC1) + (fp_text reference P1 (at 0 -2.54 180) (layer F.SilkS) + (effects (font (size 1.73482 1.08712) (thickness 0.3048))) + ) + (fp_text value CONN_4 (at 0 -2.54 180) (layer F.SilkS) hide + (effects (font (size 1.524 1.016) (thickness 0.3048))) + ) + (fp_line (start -5.08 -1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.3048)) + (fp_line (start -5.08 1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.3048)) + (fp_line (start -5.08 -1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.3048)) + (fp_line (start -5.08 -1.27) (end 5.08 -1.27) (layer F.SilkS) (width 0.3048)) + (fp_line (start 5.08 -1.27) (end 5.08 1.27) (layer F.SilkS) (width 0.3048)) + (fp_line (start 5.08 1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.3048)) + (fp_line (start -2.54 1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.3048)) + (pad 1 thru_hole rect (at -3.81 0 180) (size 1.397 1.397) (drill 0.8128) + (layers *.Cu *.Mask F.SilkS) + (net 4 N-000008) + ) + (pad 2 thru_hole circle (at -1.27 0 180) (size 1.397 1.397) (drill 0.8128) + (layers *.Cu *.Mask F.SilkS) + (net 3 N-000007) + ) + (pad 3 thru_hole circle (at 1.27 0 180) (size 1.397 1.397) (drill 0.8128) + (layers *.Cu *.Mask F.SilkS) + (net 2 N-000006) + ) + (pad 4 thru_hole circle (at 3.81 0 180) (size 1.397 1.397) (drill 0.8128) + (layers *.Cu *.Mask F.SilkS) + ) + ) + + (module SIL-4 (layer F.Cu) (tedit 200000) (tstamp 548311E1) + (at 100.838 98.6155) + (descr "Connecteur 4 pibs") + (tags "CONN DEV") + (path /54830CCE) + (fp_text reference P2 (at 0 -2.54) (layer F.SilkS) + (effects (font (size 1.73482 1.08712) (thickness 0.3048))) + ) + (fp_text value CONN_4 (at 0 -2.54) (layer F.SilkS) hide + (effects (font (size 1.524 1.016) (thickness 0.3048))) + ) + (fp_line (start -5.08 -1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.3048)) + (fp_line (start -5.08 1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.3048)) + (fp_line (start -5.08 -1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.3048)) + (fp_line (start -5.08 -1.27) (end 5.08 -1.27) (layer F.SilkS) (width 0.3048)) + (fp_line (start 5.08 -1.27) (end 5.08 1.27) (layer F.SilkS) (width 0.3048)) + (fp_line (start 5.08 1.27) (end -5.08 1.27) (layer F.SilkS) (width 0.3048)) + (fp_line (start -2.54 1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.3048)) + (pad 1 thru_hole rect (at -3.81 0) (size 1.397 1.397) (drill 0.8128) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 2 thru_hole circle (at -1.27 0) (size 1.397 1.397) (drill 0.8128) + (layers *.Cu *.Mask F.SilkS) + (net 1 N-000003) + ) + (pad 3 thru_hole circle (at 1.27 0) (size 1.397 1.397) (drill 0.8128) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 4 thru_hole circle (at 3.81 0) (size 1.397 1.397) (drill 0.8128) + (layers *.Cu *.Mask F.SilkS) + ) + ) + +) diff --git a/hardware/soic8_breakout/soic8_breakout.net b/hardware/soic8_breakout/soic8_breakout.net new file mode 100644 index 0000000000..5b50fd98b4 --- /dev/null +++ b/hardware/soic8_breakout/soic8_breakout.net @@ -0,0 +1,81 @@ +(export (version D) + (design + (source F:/stuff/rusefi_sourceforge/hardware/soic8_breakout/soic8_breakout.sch) + (date "06/12/2014 09:06:30") + (tool "eeschema (2013-07-07 BZR 4022)-stable")) + (components + (comp (ref P1) + (value CONN_4) + (libsource (lib conn) (part CONN_4)) + (sheetpath (names /) (tstamps /)) + (tstamp 54830CC1)) + (comp (ref P2) + (value CONN_4) + (libsource (lib conn) (part CONN_4)) + (sheetpath (names /) (tstamps /)) + (tstamp 54830CCE)) + (comp (ref U1) + (value XTR116U) + (libsource (lib interface) (part XTR116U)) + (sheetpath (names /) (tstamps /)) + (tstamp 54830CB2))) + (libparts + (libpart (lib conn) (part CONN_4) + (description "Symbole general de connecteur") + (fields + (field (name Reference) P) + (field (name Value) CONN_4)) + (pins + (pin (num 1) (name P1) (type passive)) + (pin (num 2) (name P2) (type passive)) + (pin (num 3) (name P3) (type passive)) + (pin (num 4) (name P4) (type passive)))) + (libpart (lib interface) (part XTR115U) + (description "XTR115U, 4-20mA Current Loop Transmitter, SO8") + (docs http://www.ti.com/lit/ds/symlink/xtr115.pdf) + (fields + (field (name Reference) U) + (field (name Value) XTR115U)) + (pins + (pin (num 1) (name Vref) (type output)) + (pin (num 2) (name Iin) (type input)) + (pin (num 3) (name Iret) (type input)) + (pin (num 4) (name Io) (type output)) + (pin (num 5) (name E) (type passive)) + (pin (num 6) (name B) (type passive)) + (pin (num 7) (name V+) (type input)) + (pin (num 8) (name Vreg) (type output))))) + (libraries + (library (logical conn) + (uri "C:\\Program Files (x86)\\KiCad\\share\\library\\conn.lib")) + (library (logical interface) + (uri "C:\\Program Files (x86)\\KiCad\\share\\library\\interface.lib"))) + (nets + (net (code 1) (name "") + (node (ref U1) (pin 8))) + (net (code 2) (name "") + (node (ref U1) (pin 7))) + (net (code 3) (name "") + (node (ref U1) (pin 6)) + (node (ref P2) (pin 2))) + (net (code 4) (name "") + (node (ref U1) (pin 5))) + (net (code 5) (name "") + (node (ref U1) (pin 4))) + (net (code 6) (name "") + (node (ref U1) (pin 3)) + (node (ref P1) (pin 3))) + (net (code 7) (name "") + (node (ref P1) (pin 2)) + (node (ref U1) (pin 2))) + (net (code 8) (name "") + (node (ref P1) (pin 1)) + (node (ref U1) (pin 1))) + (net (code 9) (name "") + (node (ref P2) (pin 1))) + (net (code 10) (name "") + (node (ref P2) (pin 4))) + (net (code 11) (name "") + (node (ref P2) (pin 3))) + (net (code 12) (name "") + (node (ref P1) (pin 4))))) \ No newline at end of file diff --git a/hardware/soic8_breakout/soic8_breakout.pro b/hardware/soic8_breakout/soic8_breakout.pro new file mode 100644 index 0000000000..f525828305 --- /dev/null +++ b/hardware/soic8_breakout/soic8_breakout.pro @@ -0,0 +1,86 @@ +update=06/12/2014 09:01:53 +version=1 +last_client=kicad +[cvpcb] +version=1 +NetIExt=net +[cvpcb/libraries] +EquName1=devcms +[eeschema] +version=1 +LibDir= +NetFmtName= +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[pcbnew/libraries] +LibDir= +LibName1=sockets +LibName2=connect +LibName3=discret +LibName4=pin_array +LibName5=divers +LibName6=smd_capacitors +LibName7=smd_resistors +LibName8=smd_crystal&oscillator +LibName9=smd_dil +LibName10=smd_transistors +LibName11=libcms +LibName12=display +LibName13=led +LibName14=dip_sockets +LibName15=pga_sockets +LibName16=valves +[general] +version=1 diff --git a/hardware/soic8_breakout/soic8_breakout.sch b/hardware/soic8_breakout/soic8_breakout.sch new file mode 100644 index 0000000000..647dd3ae69 --- /dev/null +++ b/hardware/soic8_breakout/soic8_breakout.sch @@ -0,0 +1,99 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +EELAYER 27 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "6 dec 2014" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L CONN_4 P1 +U 1 1 54830CC1 +P 3500 3450 +F 0 "P1" V 3450 3450 50 0000 C CNN +F 1 "CONN_4" V 3550 3450 50 0000 C CNN +F 2 "" H 3500 3450 60 0000 C CNN +F 3 "" H 3500 3450 60 0000 C CNN + 1 3500 3450 + -1 0 0 -1 +$EndComp +$Comp +L CONN_4 P2 +U 1 1 54830CCE +P 6000 3200 +F 0 "P2" V 5950 3200 50 0000 C CNN +F 1 "CONN_4" V 6050 3200 50 0000 C CNN +F 2 "" H 6000 3200 60 0000 C CNN +F 3 "" H 6000 3200 60 0000 C CNN + 1 6000 3200 + 1 0 0 1 +$EndComp +Wire Wire Line + 5250 3400 5650 3400 +Wire Wire Line + 5650 3400 5650 3350 +Wire Wire Line + 5650 3250 5200 3250 +Wire Wire Line + 5200 3250 5200 3200 +Wire Wire Line + 3850 3400 4400 3400 +Wire Wire Line + 3850 3300 4400 3300 +Wire Wire Line + 4400 3300 4400 3150 +Wire Wire Line + 3850 3500 4150 3500 +Wire Wire Line + 4150 3500 4150 3700 +Wire Wire Line + 4150 3700 4400 3700 +$Comp +L XTR116U U1 +U 1 1 54830CB2 +P 4800 3350 +F 0 "U1" H 4600 3800 50 0000 C CNN +F 1 "XTR116U" H 4700 2900 50 0000 C CNN +F 2 "" H 4800 3350 60 0000 C CNN +F 3 "" H 4800 3350 60 0000 C CNN + 1 4800 3350 + 1 0 0 -1 +$EndComp +$EndSCHEMATC