diff --git a/firmware/global.h b/firmware/global.h
index 5a032895e0..16ddf4ac99 100644
--- a/firmware/global.h
+++ b/firmware/global.h
@@ -60,36 +60,6 @@ typedef unsigned int time_t;
 
 #define EFI_ERROR_CODE 0xffffffff
 
-/**
- * rusEfi is placing some of data structures into CCM memory simply
- * in order to use that memory - no magic about which RAM is faster etc.
- * That said, CCM/TCM could be faster as there will be less bus contention
- * with DMA.
- *
- * Please note that DMA does not work with CCM memory
- */
-#if defined(STM32F4XX)
-// CCM memory is 64k
-#define CCM_OPTIONAL __attribute__((section(".ram4")))
-#define SDRAM_OPTIONAL __attribute__((section(".ram7")))
-#define NO_CACHE	// F4 has no cache, do nothing
-#elif defined(STM32F7XX)
-// DTCM memory is 128k
-#define CCM_OPTIONAL __attribute__((section(".ram3")))
-//TODO: update LD file!
-#define SDRAM_OPTIONAL __attribute__((section(".ram7")))
-// SRAM2 is 16k and set to disable dcache
-#define NO_CACHE __attribute__((section(".ram2")))
-#elif defined(STM32H7XX)
-// DTCM memory is 128k
-#define CCM_OPTIONAL __attribute__((section(".ram5")))
-//TODO: update LD file!
-#define SDRAM_OPTIONAL __attribute__((section(".ram8")))
-// SRAM3 is 32k and set to disable dcache
-#define NO_CACHE __attribute__((section(".ram3")))
-#else /* this MCU doesn't need these */
-#define CCM_OPTIONAL
-#define NO_CACHE
-#endif
+#include "global_port.h"
 
 #define UNIT_TEST_BUSY_WAIT_CALLBACK() {}
diff --git a/firmware/hw_layer/ports/cypress/global_port.h b/firmware/hw_layer/ports/cypress/global_port.h
new file mode 100644
index 0000000000..2e87df9360
--- /dev/null
+++ b/firmware/hw_layer/ports/cypress/global_port.h
@@ -0,0 +1,3 @@
+/* this MCU doesn't need these */
+#define CCM_OPTIONAL
+#define NO_CACHE
\ No newline at end of file
diff --git a/firmware/hw_layer/ports/kinetis/global_port.h b/firmware/hw_layer/ports/kinetis/global_port.h
new file mode 100644
index 0000000000..2e87df9360
--- /dev/null
+++ b/firmware/hw_layer/ports/kinetis/global_port.h
@@ -0,0 +1,3 @@
+/* this MCU doesn't need these */
+#define CCM_OPTIONAL
+#define NO_CACHE
\ No newline at end of file
diff --git a/firmware/hw_layer/ports/stm32/stm32f4/global_port.h b/firmware/hw_layer/ports/stm32/stm32f4/global_port.h
new file mode 100644
index 0000000000..a58c249c94
--- /dev/null
+++ b/firmware/hw_layer/ports/stm32/stm32f4/global_port.h
@@ -0,0 +1,13 @@
+/**
+ * rusEfi is placing some of data structures into CCM memory simply
+ * in order to use that memory - no magic about which RAM is faster etc.
+ * That said, CCM/TCM could be faster as there will be less bus contention
+ * with DMA.
+ *
+ * Please note that DMA does not work with CCM memory
+ */
+
+// CCM memory is 64k
+#define CCM_OPTIONAL __attribute__((section(".ram4")))
+#define SDRAM_OPTIONAL __attribute__((section(".ram7")))
+#define NO_CACHE	// F4 has no cache, do nothing
diff --git a/firmware/hw_layer/ports/stm32/stm32f7/global_port.h b/firmware/hw_layer/ports/stm32/stm32f7/global_port.h
new file mode 100644
index 0000000000..cccc485ebc
--- /dev/null
+++ b/firmware/hw_layer/ports/stm32/stm32f7/global_port.h
@@ -0,0 +1,6 @@
+// DTCM memory is 128k
+#define CCM_OPTIONAL __attribute__((section(".ram3")))
+//TODO: update LD file!
+#define SDRAM_OPTIONAL __attribute__((section(".ram7")))
+// SRAM2 is 16k and set to disable dcache
+#define NO_CACHE __attribute__((section(".ram2")))
diff --git a/firmware/hw_layer/ports/stm32/stm32h7/global_port.h b/firmware/hw_layer/ports/stm32/stm32h7/global_port.h
new file mode 100644
index 0000000000..f4b56c7028
--- /dev/null
+++ b/firmware/hw_layer/ports/stm32/stm32h7/global_port.h
@@ -0,0 +1,6 @@
+// DTCM memory is 128k
+#define CCM_OPTIONAL __attribute__((section(".ram5")))
+//TODO: update LD file!
+#define SDRAM_OPTIONAL __attribute__((section(".ram8")))
+// SRAM3 is 32k and set to disable dcache
+#define NO_CACHE __attribute__((section(".ram3")))