0x451 STMicroelectronics MCU Cortex-M7 STM32F76x/STM32F77x STM32F7 ARM 32-bit Cortex-M7 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x20 Dual 0x10 Single 0x20 Dual 0x10 ITCM Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x20 Dual 0x10 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 (VBOR3), brownout threshold level 3 BOR Level 2 (VBOR2), brownout threshold level 2 BOR Level 1 (VBOR1), brownout threshold level 1 BOR off, POR/PDR reset threshold level is applied User Configuration IWDG_STOP 0x1F 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x1E 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode nDBANK 0x1D 0x1 RW Flash in dual bank with 128 bits read access Flash in single bank with 256 bits read access nDBOOT 0x1C 0x1 RW Dual Boot enabled Dual Boot disabled WWDG_SW 0x4 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x5 0x1 RW Hardware independent watchdog Software independent watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Boot address Option Bytes BOOT_ADD0 Define the boot address when BOOT0=0 0x0 0x10 RW BOOT_ADD1 Define the boot address when BOOT0=1 0x10 0x10 RW Write Protection nWRP0 0x10 0xC RW Write protection active on this sector Write protection not active on this sector nWRP0 0x10 0x6 RW Write protection active on bank1 sector 2i and 2i+1 Write protection not active on bank1 sector 2i, 2i+1 nWRP6 0x16 0x6 RW Write protection active on bank2 sector 2i and 2i+1 Write protection not active on bank2 sector 2i, 2i+1 Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 (VBOR3), brownout threshold level 3 BOR Level 2 (VBOR2), brownout threshold level 2 BOR Level 1 (VBOR1), brownout threshold level 1 BOR off, POR/PDR reset threshold level is applied User Configuration IWDG_STOP 0xF 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0xE 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode nDBANK 0xD 0x1 RW Flash in dual bank with 128 bits read access Flash in single bank with 256 bits read access nDBOOT 0xC 0x1 RW Dual Boot enabled Dual Boot disabled WWDG_SW 0x4 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x5 0x1 RW Hardware independent watchdog Software independent watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Boot address Option Bytes BOOT_ADD0 Define the boot address when BOOT0=0 0x0 0x10 RW BOOT_ADD1 Define the boot address when BOOT0=1 0x0 0x10 RW Write Protection nWRP0 0x0 0xC RW Write protection active on this sector Write protection not active on this sector nWRP0 0x0 0x6 RW Write protection active on bank1 sector 2i and 2i+1 Write protection not active on bank1 sector 2i, 2i+1 nWRP6 0x6 0x6 RW Write protection active on bank2 sector 2i and 2i+1 Write protection not active on bank2 sector 2i, 2i+1