mirror of https://github.com/rusefi/rusefi.git
229 lines
8.5 KiB
C
229 lines
8.5 KiB
C
/*
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* hal_flash_device.h
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*
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* QSPI NOR flash driver with JEDEC SFDP for ChibiOS
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* Tested and developed with Microchip SST26F064A
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*
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* @date Aug 14, 2021
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* @author Andrey Gusakov, (c) 2021
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*/
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/**
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* @file hal_flash_device.h
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* @brief Jedec JESD216 SFDP
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*
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* @addtogroup JEDEC_SFDP
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* @{
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*/
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#ifndef HAL_FLASH_DEVICE_H
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#define HAL_FLASH_DEVICE_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Device capabilities
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* @{
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*/
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#define SNOR_DEVICE_SUPPORTS_XIP TRUE
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/** @} */
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/**
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* @name Device identification
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* @{
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*/
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/** @} */
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/**
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* @name Command codes
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* @{
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*/
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#define JEDEC_CMD_READ_DISCOVERY_PARAMETER 0x5A
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/* default/fallback commands */
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#define JEDEC_CMD_WRITE_STATUS_REGISTER 0x01
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#define JEDEC_CMD_PAGE_PROGRAM 0x02
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#define JEDEC_CMD_READ 0x03
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#define JEDEC_CMD_WRITE_DISABLE 0x04
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#define JEDEC_CMD_READ_STATUS_REGISTER 0x05
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#define JEDEC_CMD_WRITE_ENABLE 0x06
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#define JEDEC_CMD_FAST_READ 0x0B
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#define JEDEC_CMD_SUBSECTOR_ERASE 0x20
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#define JEDEC_CMD_READ_CONFIGURATION_REGISTER 0x35
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#define JEDEC_CMD_READ_DUAL 0x3B
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#define JEDEC_CMD_BULK_ERASE 0xC7
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#define JEDEC_CMD_RESET_ENABLE 0x66
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#define JEDEC_CMD_READ_QUAD 0x6B
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#define JEDEC_CMD_GLOBAL_BLOCK_PROTECTION_UNLOCK 0x98
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#define JEDEC_CMD_RESET_MEMORY 0x99
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/** @} */
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/**
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* @name Flags status register bits
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* @{
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*/
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#define JEDEC_FLAGS_STS_BUSY 0x80U
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/** @} */
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/**
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* @name Bus interface modes.
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* @{
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*/
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#define JEDEC_BUS_MODE_WSPI1L 1U
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#define JEDEC_BUS_MODE_WSPI2L 2U
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#define JEDEC_BUS_MODE_WSPI4L 4U
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Switch WSPI bus width on initialization.
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* @details A bus width initialization is performed by writing the
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* Enhanced Volatile Configuration Register. If the flash
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* device is configured using the Non Volatile Configuration
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* Register then this option is not required.
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* @note This option is only valid in WSPI bus mode.
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*/
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#if !defined(JEDEC_SWITCH_WIDTH) || defined(__DOXYGEN__)
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#define JEDEC_SWITCH_WIDTH TRUE
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#endif
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/**
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* @brief Device bus mode to be used.
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* #note if @p JEDEC_SWITCH_WIDTH is @p FALSE then this is the bus mode
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* that the device is expected to be using.
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* #note if @p JEDEC_SWITCH_WIDTH is @p TRUE then this is the bus mode
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* that the device will be switched in.
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* @note This option is only valid in WSPI bus mode.
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*/
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#if !defined(JEDEC_BUS_MODE) || defined(__DOXYGEN__)
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#define JEDEC_BUS_MODE JEDEC_BUS_MODE_WSPI4L
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#endif
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/**
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* @brief Delays insertions.
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* @details If enabled this options inserts delays into the flash waiting
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* routines releasing some extra CPU time for threads with lower
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* priority, this may slow down the driver a bit however.
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*/
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#if !defined(JEDEC_NICE_WAITING) || defined(__DOXYGEN__)
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#define JEDEC_NICE_WAITING TRUE
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#endif
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/**
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* @brief Uses 4kB sub-sectors rather than 64kB sectors.
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*/
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#if !defined(JEDEC_USE_SUB_SECTORS) || defined(__DOXYGEN__)
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#define JEDEC_USE_SUB_SECTORS FALSE
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#endif
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/**
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* @brief Number of dummy cycles for fast read (1..15).
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* @details This is the number of dummy cycles to be used for fast read
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* operations.
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*/
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#if !defined(JEDEC_READ_DUMMY_CYCLES) || defined(__DOXYGEN__)
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#define JEDEC_READ_DUMMY_CYCLES 8
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if (JEDEC_READ_DUMMY_CYCLES < 1) || (JEDEC_READ_DUMMY_CYCLES > 15)
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#error "invalid JEDEC_READ_DUMMY_CYCLES value (1..15)"
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#endif
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/**
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* @brief WSPI settings for command only.
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*/
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#define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_ONE_LINE | \
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WSPI_CFG_ADDR_MODE_NONE | \
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WSPI_CFG_ALT_MODE_NONE | \
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WSPI_CFG_DATA_MODE_NONE | \
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WSPI_CFG_CMD_SIZE_8 | \
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WSPI_CFG_ADDR_SIZE_24)
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/**
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* @brief WSPI settings for command and address.
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*/
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#define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_ONE_LINE | \
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WSPI_CFG_ADDR_MODE_ONE_LINE | \
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WSPI_CFG_ALT_MODE_NONE | \
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WSPI_CFG_DATA_MODE_NONE | \
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WSPI_CFG_CMD_SIZE_8 | \
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WSPI_CFG_ADDR_SIZE_24)
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/**
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* @brief WSPI settings for command and data.
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*/
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#define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \
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WSPI_CFG_ADDR_MODE_NONE | \
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WSPI_CFG_ALT_MODE_NONE | \
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WSPI_CFG_DATA_MODE_ONE_LINE | \
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WSPI_CFG_CMD_SIZE_8 | \
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WSPI_CFG_ADDR_SIZE_24)
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/**
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* @brief WSPI settings for command, address and data.
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*/
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#define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \
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WSPI_CFG_ADDR_MODE_ONE_LINE | \
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WSPI_CFG_ALT_MODE_NONE | \
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WSPI_CFG_DATA_MODE_ONE_LINE | \
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WSPI_CFG_CMD_SIZE_8 | \
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WSPI_CFG_ADDR_SIZE_24)
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if !defined(__DOXYGEN__)
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extern flash_descriptor_t snor_descriptor;
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#endif
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#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) && (WSPI_SUPPORTS_MEMMAP == TRUE)
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extern const wspi_command_t snor_memmap_read;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void snor_device_init(SNORDriver *devp);
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flash_error_t snor_device_read(SNORDriver *devp, flash_offset_t offset,
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size_t n, uint8_t *rp);
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flash_error_t snor_device_program(SNORDriver *devp, flash_offset_t offset,
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size_t n, const uint8_t *pp);
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flash_error_t snor_device_start_erase_all(SNORDriver *devp);
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flash_error_t snor_device_start_erase_sector(SNORDriver *devp,
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flash_sector_t sector);
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flash_error_t snor_device_verify_erase(SNORDriver *devp,
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flash_sector_t sector);
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flash_error_t snor_device_query_erase(SNORDriver *devp, uint32_t *msec);
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flash_error_t snor_device_read_sfdp(SNORDriver *devp, flash_offset_t offset,
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size_t n, uint8_t *rp);
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#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) && \
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(SNOR_DEVICE_SUPPORTS_XIP == TRUE)
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void snor_activate_xip(SNORDriver *devp);
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void snor_reset_xip(SNORDriver *devp);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_FLASH_DEVICE_H */
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/** @} */
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