mirror of https://github.com/rusefi/rusefi.git
52 lines
1.4 KiB
INI
52 lines
1.4 KiB
INI
[DEFAULT]
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projdir = .
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[Options]
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ExcellonLeadingZeros = 1
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PanelWidth = 11.8
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PanelHeight = 11.8
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XSpacing = 0.1
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YSpacing = 0.1
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AllowMissingLayers = 0
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[MergeOutputFiles]
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Prefix = %(projdir)s/merged2layer
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*TopLayer=%(prefix)s/Top.gbr
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*BottomLayer=%(prefix)s/Bottom.gbr
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*TopSilkscreen=%(prefix)s/TopSilk.gbr
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*BottomSilkscreen=%(prefix)s/BottomSilk.gbr
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*TopSoldermask=%(prefix)s/TopMask.gbr
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*BottomSoldermask=%(prefix)s/BottomMask.gbr
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Drills=%(prefix)s/Drills.txt
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holes=%(prefix)s/Drills-unplated.txt
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BoardOutline=%(prefix)s/BoardOutline.gbr
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ToolList = %(prefix)s/Tools.drl
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Placement = %(prefix)s/Placement.txt
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[brain100]
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Prefix=%(projdir)s/../brain_board/gerber/brain_board_STM32F407_R0.3/brain_board_STM32F407
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*TopLayer=%(prefix)s-F.Cu.gtl
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*BottomLayer=%(prefix)s-B.Cu.gbl
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*TopSilkscreen=%(prefix)s-F.SilkS.gto
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*TopSoldermask=%(prefix)s-F.Mask.gts
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*BottomSilkscreen=%(prefix)s-B.SilkS.gbo
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*BottomSoldermask=%(prefix)s-B.Mask.gbs
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Drills=%(prefix)s_gm.drl
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BoardOutline=%(prefix)s-Edge.Cuts.gm1
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Repeat = 1
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[connector64]
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Prefix=%(projdir)s/../176122-6-connector/176122-6-mfg/176122-6-mfg_R0.2/176122-6
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*TopLayer=%(prefix)s-Front.gtl
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*BottomLayer=%(prefix)s-Back.gbl
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*TopSilkscreen=%(prefix)s-F.SilkS.gto
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*TopSoldermask=%(prefix)s-F.Mask.gts
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*BottomSilkscreen=%(prefix)s-B.SilkS.gbo
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*BottomSoldermask=%(prefix)s-B.Mask.gbs
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Drills=%(prefix)s_gm.drl
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BoardOutline=%(prefix)s-Edge.Cuts.gm1
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Repeat = 2
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