mirror of https://github.com/rusefi/rusefi.git
269 lines
7.1 KiB
C++
269 lines
7.1 KiB
C++
/**
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* @file stm32_common.cpp
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* @brief Low level common STM32 code
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*
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* @date Mar 28, 2019
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* @author Andrey Belomutskiy, (c) 2012-2020
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*/
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#include "pch.h"
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#include <rusefi/expected.h>
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#include "hardware.h"
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#ifdef STM32F4XX
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#include "stm32f4xx_hal_flash.h"
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#elif defined(STM32F7XX)
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#include "stm32f7xx_hal_flash.h"
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#elif defined(STM32H7XX)
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#include "stm32h7xx_hal_flash.h"
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#endif
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#if EFI_USE_OPENBLT
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/* communication with OpenBLT that is plain C, not to modify external file */
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extern "C" {
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#include "openblt/shared_params.h"
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};
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#endif
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#if EFI_PROD_CODE
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#include "mpu_util.h"
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#include "backup_ram.h"
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#endif /* EFI_PROD_CODE */
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#if EFI_PROD_CODE
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static void reset_and_jump(void) {
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#ifdef STM32H7XX
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// H7 needs a forcible reset of the USB peripheral(s) in order for the bootloader to work properly.
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// If you don't do this, the bootloader will execute, but USB doesn't work (nobody knows why)
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// See https://community.st.com/s/question/0D53W00000vQEWsSAO/stm32h743-dfu-entry-doesnt-work-unless-boot0-held-high-at-poweron
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RCC->AHB1ENR &= ~(RCC_AHB1ENR_USB1OTGHSEN | RCC_AHB1ENR_USB2OTGFSEN);
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#endif
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// and now reboot
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NVIC_SystemReset();
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}
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void jump_to_bootloader() {
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// leave DFU breadcrumb which assembly startup code would check, see [rusefi][DFU] section in assembly code
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*((unsigned long *)0x2001FFF0) = 0xDEADBEEF; // End of RAM
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reset_and_jump();
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}
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void jump_to_openblt() {
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#if EFI_USE_OPENBLT
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/* safe to call on already inited shares area */
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SharedParamsInit();
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/* Store sing to stay in OpenBLT */
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SharedParamsWriteByIndex(0, 0x01);
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reset_and_jump();
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#endif
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}
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#endif /* EFI_PROD_CODE */
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#if EFI_PROD_CODE
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BOR_Level_t BOR_Get(void) {
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FLASH_OBProgramInitTypeDef FLASH_Handle;
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/* Read option bytes */
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HAL_FLASHEx_OBGetConfig(&FLASH_Handle);
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/* Return BOR value */
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return (BOR_Level_t) FLASH_Handle.BORLevel;
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}
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BOR_Result_t BOR_Set(BOR_Level_t BORValue) {
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if (BOR_Get() == BORValue) {
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return BOR_Result_Ok;
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}
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FLASH_OBProgramInitTypeDef FLASH_Handle;
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FLASH_Handle.BORLevel = (uint32_t)BORValue;
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FLASH_Handle.OptionType = OPTIONBYTE_BOR;
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HAL_FLASH_OB_Unlock();
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HAL_FLASHEx_OBProgram(&FLASH_Handle);
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HAL_StatusTypeDef status = HAL_FLASH_OB_Launch();
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HAL_FLASH_OB_Lock();
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if (status != HAL_OK) {
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return BOR_Result_Error;
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}
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return BOR_Result_Ok;
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}
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void startWatchdog(int timeoutMs) {
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#if HAL_USE_WDG
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// RL is a 12-bit value so we use a "2 ms" prescaler to support long timeouts (> 4.095 sec)
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static WDGConfig wdgcfg;
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wdgcfg.pr = STM32_IWDG_PR_64; // t = (1/32768) * 64 = ~2 ms
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wdgcfg.rlr = STM32_IWDG_RL((uint32_t)((32.768f / 64.0f) * timeoutMs));
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#if 0
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efiPrintf("[wdgStart]");
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#endif
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wdgStart(&WDGD1, &wdgcfg);
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#endif // HAL_USE_WDG
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}
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static efitimems_t watchdogResetPeriodMs = 0;
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void setWatchdogResetPeriod(int resetMs) {
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#if 0
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efiPrintf("[dev] wd %d", resetMs);
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#endif
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watchdogResetPeriodMs = (efitimems_t)resetMs;
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}
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void tryResetWatchdog() {
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#if HAL_USE_WDG
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static Timer lastTimeWasReset;
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// check if it's time to reset the watchdog
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if (lastTimeWasReset.hasElapsedMs(watchdogResetPeriodMs)) {
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// we assume tryResetWatchdog() is called from a timer callback
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wdgResetI(&WDGD1);
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lastTimeWasReset.reset();
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}
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#endif // HAL_USE_WDG
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}
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void baseMCUInit(void) {
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// looks like this holds a random value on start? Let's set a nice clean zero
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DWT->CYCCNT = 0;
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BOR_Set(BOR_Level_1); // one step above default value
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setWatchdogResetPeriod(WATCHDOG_RESET_MS);
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startWatchdog();
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}
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extern uint32_t __main_stack_base__;
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typedef struct port_intctx intctx_t;
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EXTERNC int getRemainingStack(thread_t *otp) {
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#if CH_DBG_ENABLE_STACK_CHECK
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// this would dismiss coverity warning - see http://rusefi.com/forum/viewtopic.php?f=5&t=655
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// coverity[uninit_use]
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register intctx_t *r13 asm ("r13");
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otp->activeStack = r13;
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int remainingStack;
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if (ch.dbg.isr_cnt > 0) {
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// ISR context
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remainingStack = (int)(r13 - 1) - (int)&__main_stack_base__;
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} else {
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remainingStack = (int)(r13 - 1) - (int)otp->wabase;
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}
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otp->remainingStack = remainingStack;
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return remainingStack;
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#else
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UNUSED(otp);
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return 99999;
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#endif /* CH_DBG_ENABLE_STACK_CHECK */
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}
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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#define HWREG(x) \
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(*((volatile unsigned long *)(x)))
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#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status
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#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid
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#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and
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// Fault
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#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control
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/**
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* @brief Probe an address to see if can be read without generating a bus fault
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* @details This function must be called with the processor in privileged mode.
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* It:
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* - Clear any previous indication of a bus fault in the BFARV bit
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* - Temporarily sets the processor to Ignore Bus Faults with all interrupts and fault handlers disabled
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* - Attempt to read from read_address, ignoring the result
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* - Checks to see if the read caused a bus fault, by checking the BFARV bit is set
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* - Re-enables Bus Faults and all interrupts and fault handlers
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* @param[in] read_address The address to try reading a byte from
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* @return Returns true if no bus fault occurred reading from read_address, or false if a bus fault occurred.
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*/
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bool ramReadProbe(volatile const char *read_address) {
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bool address_readable = true;
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/* Clear any existing indication of a bus fault - BFARV is write one to clear */
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HWREG (NVIC_FAULT_STAT) |= NVIC_FAULT_STAT_BFARV;
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HWREG (NVIC_CFG_CTRL) |= NVIC_CFG_CTRL_BFHFNMIGN;
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asm volatile (" CPSID f;");
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*read_address;
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if ((HWREG (NVIC_FAULT_STAT) & NVIC_FAULT_STAT_BFARV) != 0)
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{
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address_readable = false;
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}
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asm volatile (" CPSIE f;");
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HWREG (NVIC_CFG_CTRL) &= ~NVIC_CFG_CTRL_BFHFNMIGN;
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return address_readable;
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}
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#endif
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#if defined(STM32F4)
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bool isStm32F42x() {
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// really it's enough to just check 0x20020010
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return ramReadProbe((const char *)0x20000010) && ramReadProbe((const char *)0x20020010) && !ramReadProbe((const char *)0x20070010);
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}
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#endif
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// Stubs for per-board low power helpers
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PUBLIC_API_WEAK void boardPrepareForStop() {
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// Default implementation - wake up on PA0 - boards should override this
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palEnableLineEvent(PAL_LINE(GPIOA, 0), PAL_EVENT_MODE_RISING_EDGE);
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}
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/**
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Standby uses special low power hardware - it always wakes on rising edge
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*/
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void boardPreparePA0ForStandby() {
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#ifdef STM32F4XX
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//Enable Wakeup Pin for PA0
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PWR->CSR |= PWR_CSR_EWUP;
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// Clear wakeup flag - it may be set if PA0 is already
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// high when we enable it as a wake source
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PWR->CR |= PWR_CR_CWUF; //Clear Wakeup Pin flag for PA0
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#endif
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#ifdef STM32F7XX
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PWR->CSR2 |= PWR_CSR2_EWUP1; //EWUP1: Enable Wakeup pin for PA0
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PWR->CR2 |= PWR_CR2_CWUPF1; //Clear Wakeup Pin flag for PA0
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#endif
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#ifdef STM32H7XX
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// Wake on wakeup pin 0 - PA0
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PWR->WKUPEPR = PWR_WKUPEPR_WKUPEN1;
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// clear all possible wakeup bits
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PWR->WKUPCR = 0xFFFFFFFF;
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#endif
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}
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PUBLIC_API_WEAK void boardPrepareForStandby() {
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boardPreparePA0ForStandby();
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}
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#endif // EFI_PROD_CODE
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