mirror of https://github.com/rusefi/rusefi.git
606 lines
20 KiB
XML
606 lines
20 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
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<Device>
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<DeviceID>0x452</DeviceID>
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<Vendor>STMicroelectronics</Vendor>
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<Type>MCU</Type>
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<CPU>Cortex-M7</CPU>
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<Name>STM32F72x/STM32F73x</Name>
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<Series>STM32F7</Series>
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<Description>ARM 32-bit Cortex-M7 based device</Description>
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<Configurations>
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<!-- JTAG_SWD Interface -->
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<Interface name="JTAG_SWD">
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<Configuration number="0x0"> <!-- ROM Die -->
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<RomLess>
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<ReadRegister address="0x1FF07A22" mask="0x40" value="0x00"/>
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</RomLess>
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</Configuration>
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<Configuration number="0x1"> <!-- RomLess Die -->
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<RomLess>
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<ReadRegister address="0x1FF07A22" mask="0x40" value="0x40"/>
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</RomLess>
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</Configuration>
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</Interface>
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<!-- Bootloader Interface -->
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<Interface name="Bootloader">
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<Configuration number="0x0"> <!-- ROM Die -->
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<RomLess>
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<ReadRegister address="0x0x08000000" mask="0x00" value="0x00"/>
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</RomLess>
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</Configuration>
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</Interface>
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</Configurations>
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<!-- Peripherals -->
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<Peripherals>
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<!-- Embedded SRAM -->
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<Peripheral>
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<Name>Embedded SRAM</Name>
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<Type>Storage</Type>
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<Description/>
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<ErasedValue>0x00</ErasedValue>
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<Access>RWE</Access>
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<!-- 512 KB -->
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<Configuration>
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<Parameters address="0x20000000" name="SRAM" size="0x40000"/>
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<Description/>
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<Organization>Single</Organization>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x20000000" name="SRAM" occurrence="0x1" size="0x40000"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Embedded Flash -->
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<Peripheral>
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<Name>Embedded Flash</Name>
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<Type>Storage</Type>
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<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RWE</Access>
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<FlashSize address="0x1FF07A22" default="0x80000"/>
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<BootloaderVersion address="0x1FF0EDBE"/>
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<!-- 512KB single Bank -->
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<Configuration config="0">
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<Parameters address="0x08000000" name=" 512 Kbytes Embedded Flash" size="0x80000"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x10</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x4" size="0x4000"/>
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</Field>
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<Field>
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<Parameters address="0x08010000" name="sector4" occurrence="0x1" size="0x10000"/>
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</Field>
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<Field>
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<Parameters address="0x08020000" name="sector5" occurrence="0x3" size="0x20000"/>
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</Field>
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</Bank>
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</Configuration>
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<!-- 64KB RomLess -->
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<Configuration config="1">
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<Parameters address="0x08000000" name=" 64 Kbytes Embedded Flash" size="0x10000"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x10</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x4" size="0x4000"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- ITCM Bytes -->
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<Peripheral>
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<Name>ITCM Flash</Name>
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<Type>Storage</Type>
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<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RWE</Access>
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<!-- 512KB single Bank -->
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<Configuration config="0">
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<Parameters address="0x00200000" name=" 512 Kbytes ITCM Flash" size="0x80000"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x10</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x00200000" name="sector0" occurrence="0x4" size="0x4000"/>
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</Field>
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<Field>
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<Parameters address="0x00210000" name="sector4" occurrence="0x1" size="0x10000"/>
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</Field>
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<Field>
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<Parameters address="0x00220000" name="sector5" occurrence="0x3" size="0x20000"/>
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</Field>
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</Bank>
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</Configuration>
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<!-- 64KB RomLess -->
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<Configuration config="1">
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<Parameters address="0x00200000" name=" 64 Kbytes ITCM Flash" size="0x10000"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x10</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x00200000" name="sector0" occurrence="0x4" size="0x4000"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- OTP -->
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<Peripheral>
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<Name>OTP</Name>
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<Type>Storage</Type>
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<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RW</Access>
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<!-- 512 Bytes single bank -->
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<Configuration>
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<Parameters address="0x1FF07800" name=" 512 Bytes Data OTP" size="0x200"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x4</Alignment>
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<Bank name="OTP">
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<Field>
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<Parameters address="0x1FF07800" name="OTP" occurrence="0x1" size="0x200"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Mirror Option Bytes -->
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<Peripheral>
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<Name>MirrorOptionBytes</Name>
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<Type>Storage</Type>
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<Description>Mirror Option Bytes contains the extra area.</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RW</Access>
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<!-- 44 Bytes single bank -->
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<Configuration>
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<Parameters address="0x1FFF0000" name=" 44 Bytes Data MirrorOptionBytes" size="0x2C"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x4</Alignment>
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<Bank name="MirrorOptionBytes">
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<Field>
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<Parameters address="0x1FFF0000" name="MirrorOptionBytes" occurrence="0x1" size="0x2C"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Option Bytes -->
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<Peripheral>
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<Name>Option Bytes</Name>
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<Type>Configuration</Type>
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<Description/>
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<Access>RW</Access>
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<Bank interface="JTAG_SWD">
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<Parameters address="0x40023C14" name="Bank 1" size="0xC"/>
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<Category>
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<Name>Read Out Protection</Name>
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<Field>
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<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>RDP</Name>
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<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
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<BitOffset>0x8</BitOffset>
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<BitWidth>0x8</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0xAA">Level 0, no protection</Val>
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<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
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<Val value="0xCC">Level 2, chip protection</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>BOR Level</Name>
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<Field>
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<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>BOR_LEV</Name>
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<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
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<BitOffset>0x2</BitOffset>
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<BitWidth>0x2</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
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<Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
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<Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
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<Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>User Configuration</Name>
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<Field>
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<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>IWDG_STOP</Name>
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<Description/>
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<BitOffset>0x1F</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Freeze IWDG counter in stop mode</Val>
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<Val value="0x1">IWDG counter active in stop mode</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>IWDG_STDBY</Name>
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<Description/>
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<BitOffset>0x1E</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Freeze IWDG counter in standby mode</Val>
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<Val value="0x1">IWDG counter active in standby mode</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>WWDG_SW</Name>
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<Description/>
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<BitOffset>0x4</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Hardware window watchdog</Val>
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<Val value="0x1">Software window watchdog</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>IWDG_SW</Name>
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<Description/>
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<BitOffset>0x5</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Hardware independent watchdog</Val>
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<Val value="0x1">Software independent watchdog</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nRST_STOP</Name>
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<Description/>
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<BitOffset>0x6</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Reset generated when entering Stop mode</Val>
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<Val value="0x1">No reset generated</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nRST_STDBY</Name>
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<Description/>
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<BitOffset>0x7</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Reset generated when entering Standby mode</Val>
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<Val value="0x1">No reset generated</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40023C1C" name="FLASH_OPTCR2" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>PCROP_RDP</Name>
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<Description/>
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<BitOffset>0x1F</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
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<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>Boot address Option Bytes</Name>
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<Field>
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<Parameters address="0x40023C18" name="FLASH_OPTCR1" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>BOOT_ADD0</Name>
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<Description>Define the boot address when BOOT0=0</Description>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0x10</BitWidth>
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<Access>RW</Access>
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<Equation multiplier="0x4000" offset="0x0"/>
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</Bit>
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<Bit>
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<Name>BOOT_ADD1</Name>
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<Description>Define the boot address when BOOT0=1</Description>
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<BitOffset>0x10</BitOffset>
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<BitWidth>0x10</BitWidth>
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<Access>RW</Access>
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<Equation multiplier="0x4000" offset="0x0"/>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>Write Protection</Name>
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<Field>
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<Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
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<AssignedBits>
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<Bit config="0">
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<Name>nWRP0</Name>
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<Description/>
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<BitOffset>0x10</BitOffset>
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<BitWidth>0x8</BitWidth>
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<Access>RW</Access>
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<Values ByBit="true">
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<Val value="0x0">Write protection active on this sector</Val>
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<Val value="0x1">Write protection not active on this sector</Val>
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</Values>
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</Bit>
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<Bit config="1">
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<Name>nWRP0</Name>
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<Description/>
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<BitOffset>0x10</BitOffset>
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<BitWidth>0x4</BitWidth>
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<Access>RW</Access>
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<Values ByBit="true">
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<Val value="0x0">Write protection active on this sector</Val>
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<Val value="0x1">Write protection not active on this sector</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>Read/Write Protection</Name>
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<Field>
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<Parameters address="0x40023C1C" name="FLASH_OPTCR2" size="0x4"/>
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<AssignedBits>
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<Bit config="0">
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<Name>PCROP0</Name>
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<Description/>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0x8</BitWidth>
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<Access>RW</Access>
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<Values ByBit="true">
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<Val value="0x0">PCROP protection not active on this sector</Val>
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<Val value="0x1">PCROP protection active on this sector</Val>
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</Values>
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</Bit>
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<Bit config="1">
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<Name>PCROP0</Name>
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<Description/>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0x4</BitWidth>
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<Access>RW</Access>
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<Values ByBit="true">
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<Val value="0x0">PCROP protection not active on this sector</Val>
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<Val value="0x1">PCROP protection active on this sector</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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</Bank>
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<Bank interface="Bootloader">
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<Parameters address="0x1FFF0000" name="Bank 1" size="0x2C"/>
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<Category>
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<Name>Read Out Protection</Name>
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<Field>
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<Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>RDP</Name>
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<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
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<BitOffset>0x8</BitOffset>
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<BitWidth>0x8</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0xAA">Level 0, no protection</Val>
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<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
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<Val value="0xCC">Level 2, chip protection</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>BOR Level</Name>
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<Field>
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<Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>BOR_LEV</Name>
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<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
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<BitOffset>0x2</BitOffset>
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<BitWidth>0x2</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
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<Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
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<Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
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<Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>User Configuration</Name>
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<Field>
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<Parameters address="0x1FFF0008" name="FLASH_OPTCR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>IWDG_STOP</Name>
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<Description/>
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<BitOffset>0xF</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Freeze IWDG counter in stop mode</Val>
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<Val value="0x1">IWDG counter active in stop mode</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>IWDG_STDBY</Name>
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<Description/>
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<BitOffset>0xE</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Freeze IWDG counter in standby mode</Val>
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<Val value="0x1">IWDG counter active in standby mode</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>WWDG_SW</Name>
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<Description/>
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<BitOffset>0x4</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Hardware window watchdog</Val>
|
|
<Val value="0x1">Software window watchdog</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>IWDG_SW</Name>
|
|
<Description/>
|
|
<BitOffset>0x5</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Hardware independent watchdog</Val>
|
|
<Val value="0x1">Software independent watchdog</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nRST_STOP</Name>
|
|
<Description/>
|
|
<BitOffset>0x6</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
|
<Val value="0x1">No reset generated</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nRST_STDBY</Name>
|
|
<Description/>
|
|
<BitOffset>0x7</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
|
<Val value="0x1">No reset generated</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x1FFF0028" name="FLASH_OPTCR2" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP_RDP</Name>
|
|
<Description/>
|
|
<BitOffset>0xF</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
|
|
<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Boot address Option Bytes</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF0010" name="FLASH_OPTCR1" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BOOT_ADD0</Name>
|
|
<Description>Define the boot address when BOOT0=0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x10</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x4000" offset="0x0"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x1FFF0018" name="FLASH_OPTCR1" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BOOT_ADD1</Name>
|
|
<Description>Define the boot address when BOOT0=1</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x10</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x4000" offset="0x0"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Write Protection</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF0008" name="FLASH_OPTCR1" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>nWRP0</Name>
|
|
<Description/>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values ByBit="true">
|
|
<Val value="0x0">Write protection active on this sector</Val>
|
|
<Val value="0x1">Write protection not active on this sector</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Read/Write Protection</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF0020" name="FLASH_OPTCR2" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP0</Name>
|
|
<Description/>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values ByBit="true">
|
|
<Val value="0x0">PCROP protection not active on this sector</Val>
|
|
<Val value="0x1">PCROP protection active on this sector</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
</Peripheral>
|
|
</Peripherals>
|
|
</Device>
|
|
</Root> |