mirror of https://github.com/zcash/halo2.git
MessageSchedule subregion2 assignments
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@ -13,7 +13,7 @@ use crate::{
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mod schedule_gates;
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mod schedule_util;
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mod subregion1;
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// mod subregion2;
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mod subregion2;
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// mod subregion3;
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use schedule_gates::ScheduleGate;
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@ -411,7 +411,16 @@ impl MessageSchedule {
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// Returns the output of sigma_0 on W_[1..14]
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let lower_sigma_0_output = self.assign_subregion1(&mut region, &input[1..14])?;
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// TODO: Assign subregion2 and subregion3
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// sigma_0_v2 and sigma_1_v2 on W_[14..49]
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// Returns the output of sigma_0_v2 on W_[36..49], to be used in subregion3
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let lower_sigma_0_v2_output = self.assign_subregion2(
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&mut region,
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lower_sigma_0_output,
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&mut w,
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&mut w_halves,
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)?;
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// TODO: Assign subregion3
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Ok(())
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},
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@ -0,0 +1,427 @@
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use super::super::{
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util::*, CellValue16, CellValue32, SpreadVar, SpreadWord, Table16Assignment, Table16Chip,
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};
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use super::{schedule_util::*, MessageSchedule, MessageWord};
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use crate::{arithmetic::FieldExt, circuit::Region, plonk::Error};
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// A word in subregion 2
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// (3, 4, 3, 7, 1, 1, 13)-bit chunks
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#[derive(Clone, Debug)]
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pub struct Subregion2Word {
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index: usize,
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a: CellValue32,
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b: CellValue32,
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c: CellValue32,
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d: CellValue32,
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e: CellValue32,
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f: CellValue32,
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g: CellValue32,
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spread_d: CellValue32,
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spread_g: CellValue32,
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}
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impl MessageSchedule {
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// W_[14..49]
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pub fn assign_subregion2<F: FieldExt>(
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&self,
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region: &mut Region<'_, Table16Chip<F>>,
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lower_sigma_0_output: Vec<(CellValue16, CellValue16)>,
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w: &mut Vec<MessageWord>,
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w_halves: &mut Vec<(CellValue16, CellValue16)>,
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) -> Result<Vec<(CellValue16, CellValue16)>, Error> {
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let a_5 = self.message_schedule;
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let a_6 = self.extras[2];
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let a_7 = self.extras[3];
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let a_8 = self.extras[4];
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let a_9 = self.extras[5];
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let mut lower_sigma_0_v2_results =
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Vec::<(CellValue16, CellValue16)>::with_capacity(SUBREGION_2_LEN);
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let mut lower_sigma_1_v2_results =
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Vec::<(CellValue16, CellValue16)>::with_capacity(SUBREGION_2_LEN);
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// Closure to compose new word
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// W_i = sigma_1(W_{i - 2}) + W_{i - 7} + sigma_0(W_{i - 15}) + W_{i - 16}
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// e.g. W_16 = sigma_1(W_14) + W_9 + sigma_0(W_1) + W_0
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// sigma_0(W_[1..14]) will be used to get the new W_[16..29]
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// sigma_0_v2(W_[14..36]) will be used to get the new W_[29..51]
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// sigma_1_v2(W_[14..49]) will be used to get the W_[16..51]
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// The lowest-index words involved will be W_[0..13]
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let mut new_word = |idx: usize,
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sigma_0_output: (CellValue16, CellValue16)|
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-> Result<Vec<(CellValue16, CellValue16)>, Error> {
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// Decompose word into (3, 4, 3, 7, 1, 1, 13)-bit chunks
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let subregion2_word =
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self.decompose_subregion2_word(region, w[idx].value.unwrap(), idx)?;
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// sigma_0 v2 and sigma_1 v2 on subregion2_word
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lower_sigma_0_v2_results.push(self.lower_sigma_0_v2(region, subregion2_word.clone())?);
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lower_sigma_1_v2_results.push(self.lower_sigma_1_v2(region, subregion2_word)?);
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let new_word_idx = idx + 2;
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// Copy sigma_0(W_{i - 15}) output from Subregion 1
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self.assign_and_constrain(
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region,
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|| format!("sigma_0(W_{})_lo", new_word_idx - 15),
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a_6,
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get_word_row(new_word_idx - 16),
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&sigma_0_output.0.into(),
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&self.perm,
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)?;
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self.assign_and_constrain(
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region,
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|| format!("sigma_0(W_{})_hi", new_word_idx - 15),
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a_6,
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get_word_row(new_word_idx - 16) + 1,
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&sigma_0_output.1.into(),
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&self.perm,
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)?;
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// Copy sigma_1(W_{i - 2})
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self.assign_and_constrain(
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region,
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|| format!("sigma_1(W_{})_lo", new_word_idx - 2),
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a_7,
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get_word_row(new_word_idx - 16),
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&lower_sigma_1_v2_results[new_word_idx - 16].0.into(),
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&self.perm,
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)?;
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self.assign_and_constrain(
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region,
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|| format!("sigma_1(W_{})_hi", new_word_idx - 2),
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a_7,
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get_word_row(new_word_idx - 16) + 1,
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&lower_sigma_1_v2_results[new_word_idx - 16].1.into(),
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&self.perm,
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)?;
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// Copy W_{i - 7}
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self.assign_and_constrain(
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region,
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|| format!("W_{}_lo", new_word_idx - 7),
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a_8,
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get_word_row(new_word_idx - 16),
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&w_halves[new_word_idx - 7].0.into(),
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&self.perm,
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)?;
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self.assign_and_constrain(
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region,
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|| format!("W_{}_hi", new_word_idx - 7),
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a_8,
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get_word_row(new_word_idx - 16) + 1,
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&w_halves[new_word_idx - 7].1.into(),
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&self.perm,
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)?;
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// Calculate W_i, carry_i
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let word_lo: u32 = lower_sigma_1_v2_results[new_word_idx - 16].0.value.unwrap() as u32
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+ w_halves[new_word_idx - 7].0.value.unwrap() as u32
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+ sigma_0_output.0.value.unwrap() as u32
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+ w_halves[new_word_idx - 16].0.value.unwrap() as u32;
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let word_hi: u32 = lower_sigma_1_v2_results[new_word_idx - 16].1.value.unwrap() as u32
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+ w_halves[new_word_idx - 7].1.value.unwrap() as u32
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+ sigma_0_output.1.value.unwrap() as u32
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+ w_halves[new_word_idx - 16].1.value.unwrap() as u32;
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let word: u64 = word_lo as u64 + (1 << 16) * (word_hi as u64);
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let carry = word >> 32;
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let word = word as u32;
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// Assign W_i, carry_i
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region.assign_advice(
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|| format!("W_{}", new_word_idx),
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a_5,
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get_word_row(new_word_idx - 16) + 1,
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|| Ok(F::from_u64(word as u64)),
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)?;
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region.assign_advice(
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|| format!("carry_{}", new_word_idx),
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a_9,
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get_word_row(new_word_idx - 16) + 1,
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|| Ok(F::from_u64(carry as u64)),
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)?;
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let (var, halves) = self.assign_word_and_halves(region, word, new_word_idx)?;
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w.push(MessageWord {
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var,
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value: Some(word),
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});
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w_halves.push(halves);
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Ok(lower_sigma_0_v2_results.clone())
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};
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let mut tmp_lower_sigma_0_v2_results: Vec<(CellValue16, CellValue16)> =
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Vec::with_capacity(SUBREGION_2_LEN);
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// Use up all the output from Subregion 1 lower_sigma_0
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for i in 14..27 {
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tmp_lower_sigma_0_v2_results = new_word(i, lower_sigma_0_output[i - 14])?;
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}
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for i in 27..49 {
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tmp_lower_sigma_0_v2_results =
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new_word(i, tmp_lower_sigma_0_v2_results[i + 2 - 15 - 14].clone())?;
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}
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// Return lower_sigma_0_v2 output for W_[36..49]
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Ok(lower_sigma_0_v2_results.split_off(36 - 14))
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}
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fn decompose_subregion2_word<F: FieldExt>(
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&self,
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region: &mut Region<'_, Table16Chip<F>>,
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word: u32,
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index: usize,
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) -> Result<Subregion2Word, Error> {
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let row = get_word_row(index);
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// Rename these here for ease of matching the gates to the specification.
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let a_3 = self.extras[0];
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let a_4 = self.extras[1];
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let pieces = chop_u32(word, &[3, 4, 3, 7, 1, 1, 13]);
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// Assign `a` (3-bit piece)
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let a = region.assign_advice(|| "a", a_3, row - 1, || Ok(F::from_u64(pieces[0] as u64)))?;
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// Assign `b` (4-bit piece) lookup
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let spread_b = SpreadWord::new(pieces[1] as u16);
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let spread_b = SpreadVar::with_lookup(region, &self.lookup, row + 1, spread_b)?;
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// Assign `c` (3-bit piece)
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let c = region.assign_advice(|| "c", a_4, row - 1, || Ok(F::from_u64(pieces[2] as u64)))?;
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// Assign `d` (7-bit piece) lookup
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let spread_d = SpreadWord::new(pieces[3] as u16);
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let spread_d = SpreadVar::with_lookup(region, &self.lookup, row, spread_d)?;
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// Assign `e` (1-bit piece)
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let e = region.assign_advice(|| "e", a_3, row + 1, || Ok(F::from_u64(pieces[4] as u64)))?;
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// Assign `f` (1-bit piece)
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let f = region.assign_advice(|| "f", a_4, row + 1, || Ok(F::from_u64(pieces[5] as u64)))?;
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// Assign `g` (13-bit piece) lookup
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let spread_g = SpreadWord::new(pieces[6] as u16);
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let spread_g = SpreadVar::with_lookup(region, &self.lookup, row - 1, spread_g)?;
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Ok(Subregion2Word {
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index,
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a: CellValue32::new(a, pieces[0].into()),
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b: CellValue32::new(spread_b.dense.var, spread_b.dense.value.unwrap().into()),
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c: CellValue32::new(c, pieces[2].into()),
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d: CellValue32::new(spread_d.dense.var, spread_d.dense.value.unwrap().into()),
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e: CellValue32::new(e, pieces[4].into()),
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f: CellValue32::new(f, pieces[5].into()),
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g: CellValue32::new(spread_g.dense.var, spread_g.dense.value.unwrap().into()),
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spread_d: CellValue32::new(spread_d.spread.var, spread_d.spread.value.unwrap().into()),
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spread_g: CellValue32::new(spread_g.spread.var, spread_g.spread.value.unwrap().into()),
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})
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}
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fn assign_lower_sigma_v2_pieces<F: FieldExt>(
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&self,
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region: &mut Region<'_, Table16Chip<F>>,
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row: usize,
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subregion2_word: Subregion2Word,
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) -> Result<(u64, u64, u64, u64, u64, u64, u64, u64), Error> {
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let a_3 = self.extras[0];
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let a_4 = self.extras[1];
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let a_5 = self.message_schedule;
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let a_6 = self.extras[2];
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let a_7 = self.extras[3];
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// Assign `a` and copy constraint
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self.assign_and_constrain(region, || "a", a_3, row + 1, &subregion2_word.a, &self.perm)?;
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// Witness `spread_a`
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let spread_a = interleave_u16_with_zeros(subregion2_word.a.value.unwrap() as u16);
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region.assign_advice(
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|| "spread_a",
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a_4,
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row + 1,
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|| Ok(F::from_u64(spread_a as u64)),
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)?;
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// Split `b` (2-bit chunk) into `b_hi` and `b_lo`
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let b = subregion2_word.b.value.unwrap();
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let (b_lo, b_hi) = bisect_four_bit(b);
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let spread_b_lo = interleave_u16_with_zeros(b_lo as u16);
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let spread_b_hi = interleave_u16_with_zeros(b_hi as u16);
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// Assign `b_hi`, `spread_b_hi`, `b_lo`, `spread_b_lo`
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region.assign_advice(|| "b_lo", a_3, row - 1, || Ok(F::from_u64(b_lo as u64)))?;
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region.assign_advice(
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|| "spread_b_lo",
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a_4,
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row - 1,
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|| Ok(F::from_u64(spread_b_lo as u64)),
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)?;
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region.assign_advice(|| "b_hi", a_5, row - 1, || Ok(F::from_u64(b_hi as u64)))?;
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region.assign_advice(
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|| "spread_b_hi",
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a_6,
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row - 1,
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|| Ok(F::from_u64(spread_b_hi as u64)),
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)?;
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// Assign `b` and copy constraint
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self.assign_and_constrain(region, || "b", a_6, row, &subregion2_word.b, &self.perm)?;
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// Assign `c` and copy constraint
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self.assign_and_constrain(region, || "c", a_5, row + 1, &subregion2_word.c, &self.perm)?;
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// Witness `spread_c`
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let spread_c = interleave_u16_with_zeros(subregion2_word.c.value.unwrap() as u16);
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region.assign_advice(
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|| "spread_c",
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a_6,
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row + 1,
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|| Ok(F::from_u64(spread_c as u64)),
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)?;
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// Assign `spread_d` and copy constraint
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self.assign_and_constrain(
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region,
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|| "spread_d",
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a_4,
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row,
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&subregion2_word.spread_d,
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&self.perm,
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)?;
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// Assign `e` and copy constraint
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self.assign_and_constrain(region, || "e", a_7, row, &subregion2_word.e, &self.perm)?;
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// Assign `f` and copy constraint
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self.assign_and_constrain(region, || "f", a_7, row + 1, &subregion2_word.f, &self.perm)?;
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// Assign `spread_g` and copy constraint
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self.assign_and_constrain(
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region,
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|| "spread_g",
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a_5,
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row,
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&subregion2_word.spread_g,
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&self.perm,
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)?;
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Ok((
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spread_a as u64,
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spread_b_lo as u64,
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spread_b_hi as u64,
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spread_c as u64,
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subregion2_word.spread_d.value.unwrap() as u64,
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subregion2_word.e.value.unwrap() as u64,
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subregion2_word.f.value.unwrap() as u64,
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subregion2_word.spread_g.value.unwrap() as u64,
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))
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}
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fn lower_sigma_0_v2<F: FieldExt>(
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&self,
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region: &mut Region<'_, Table16Chip<F>>,
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subregion2_word: Subregion2Word,
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) -> Result<(CellValue16, CellValue16), Error> {
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let a_3 = self.extras[0];
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let row = get_word_row(subregion2_word.index) + 3;
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// Get spread pieces
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let (spread_a, spread_b_lo, spread_b_hi, spread_c, spread_d, e, f, spread_g) =
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self.assign_lower_sigma_v2_pieces(region, row, subregion2_word)?;
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// Calculate R_0^{even}, R_0^{odd}, R_1^{even}, R_1^{odd}
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let xor_0 = spread_b_lo
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+ (1 << 4) * spread_b_hi
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+ (1 << 8) * spread_c
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+ (1 << 14) * spread_d
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+ (1 << 28) * e
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+ (1 << 30) * f
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+ (1 << 32) * spread_g;
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let xor_1 = spread_c
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+ (1 << 6) * spread_d
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+ (1 << 20) * e
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+ (1 << 22) * f
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+ (1 << 24) * spread_g
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+ (1 << 50) * spread_a
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+ (1 << 56) * spread_b_lo
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+ (1 << 60) * spread_b_hi;
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let xor_2 = f
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+ (1 << 2) * spread_g
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+ (1 << 28) * spread_a
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+ (1 << 34) * spread_b_lo
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+ (1 << 38) * spread_b_hi
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+ (1 << 42) * spread_c
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+ (1 << 48) * spread_d
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+ (1 << 62) * e;
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let r = xor_0 + xor_1 + xor_2;
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let r_pieces = chop_u64(r, &[32, 32]); // r_0, r_1
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let (r_0_even, r_0_odd) = get_even_and_odd_bits_u32(r_pieces[0] as u32);
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let (r_1_even, r_1_odd) = get_even_and_odd_bits_u32(r_pieces[1] as u32);
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self.assign_sigma_outputs(
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region,
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&self.lookup,
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a_3,
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&self.perm,
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row,
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r_0_even,
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r_0_odd,
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r_1_even,
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r_1_odd,
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)
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}
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fn lower_sigma_1_v2<F: FieldExt>(
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&self,
|
||||
region: &mut Region<'_, Table16Chip<F>>,
|
||||
subregion2_word: Subregion2Word,
|
||||
) -> Result<(CellValue16, CellValue16), Error> {
|
||||
let a_3 = self.extras[0];
|
||||
let row = get_word_row(subregion2_word.index) + SIGMA_0_V2_ROWS + 3;
|
||||
|
||||
let (spread_a, spread_b_lo, spread_b_hi, spread_c, spread_d, e, f, spread_g) =
|
||||
self.assign_lower_sigma_v2_pieces(region, row, subregion2_word.clone())?;
|
||||
|
||||
// (3, 4, 3, 7, 1, 1, 13)
|
||||
|
||||
// Calculate R_0^{even}, R_0^{odd}, R_1^{even}, R_1^{odd}
|
||||
let xor_0 = spread_d + (1 << 14) * e + (1 << 16) * f + (1 << 18) * spread_g;
|
||||
let xor_1 = e
|
||||
+ (1 << 2) * f
|
||||
+ (1 << 4) * spread_g
|
||||
+ (1 << 30) * spread_a
|
||||
+ (1 << 36) * spread_b_lo
|
||||
+ (1 << 40) * spread_b_hi
|
||||
+ (1 << 44) * spread_c
|
||||
+ (1 << 50) * spread_d;
|
||||
let xor_2 = spread_g
|
||||
+ (1 << 26) * spread_a
|
||||
+ (1 << 32) * spread_b_lo
|
||||
+ (1 << 36) * spread_b_hi
|
||||
+ (1 << 40) * spread_c
|
||||
+ (1 << 46) * spread_d
|
||||
+ (1 << 60) * e
|
||||
+ (1 << 62) * f;
|
||||
|
||||
let r = xor_0 + xor_1 + xor_2;
|
||||
let r_pieces = chop_u64(r, &[32, 32]); // r_0, r_1
|
||||
let (r_0_even, r_0_odd) = get_even_and_odd_bits_u32(r_pieces[0] as u32);
|
||||
let (r_1_even, r_1_odd) = get_even_and_odd_bits_u32(r_pieces[1] as u32);
|
||||
|
||||
self.assign_sigma_outputs(
|
||||
region,
|
||||
&self.lookup,
|
||||
a_3,
|
||||
&self.perm,
|
||||
row,
|
||||
r_0_even,
|
||||
r_0_odd,
|
||||
r_1_even,
|
||||
r_1_odd,
|
||||
)
|
||||
}
|
||||
}
|
Loading…
Reference in New Issue