sha256: Update Error::SynthesisError -> Error::Synthesis

This commit is contained in:
therealyingtong 2021-11-23 13:13:11 -05:00
parent be1c0c080f
commit b805f85f9f
5 changed files with 15 additions and 18 deletions

View File

@ -783,7 +783,7 @@ impl CompressionConfig {
|| {
h_prime_carry
.map(|value| pallas::Base::from_u64(value as u64))
.ok_or(Error::SynthesisError)
.ok_or(Error::Synthesis)
},
)?;
@ -834,7 +834,7 @@ impl CompressionConfig {
|| {
e_new_carry
.map(pallas::Base::from_u64)
.ok_or(Error::SynthesisError)
.ok_or(Error::Synthesis)
},
)?;
@ -892,7 +892,7 @@ impl CompressionConfig {
|| {
a_new_carry
.map(pallas::Base::from_u64)
.ok_or(Error::SynthesisError)
.ok_or(Error::Synthesis)
},
)?;

View File

@ -42,7 +42,7 @@ impl CompressionConfig {
abcd_row,
|| {
a.map(|a| pallas::Base::from_u64(a as u64))
.ok_or(Error::SynthesisError)
.ok_or(Error::Synthesis)
},
)?;
@ -64,7 +64,7 @@ impl CompressionConfig {
efgh_row,
|| {
e.map(|e| pallas::Base::from_u64(e as u64))
.ok_or(Error::SynthesisError)
.ok_or(Error::Synthesis)
},
)?;
@ -103,7 +103,7 @@ impl CompressionConfig {
row,
|| {
val.map(|val| pallas::Base::from_u64(val as u64))
.ok_or(Error::SynthesisError)
.ok_or(Error::Synthesis)
},
)?;

View File

@ -253,7 +253,7 @@ impl MessageScheduleConfig {
get_word_row(new_word_idx - 16) + 1,
|| {
word.map(|word| pallas::Base::from_u64(word as u64))
.ok_or(Error::SynthesisError)
.ok_or(Error::Synthesis)
},
)?;
region.assign_advice(
@ -263,7 +263,7 @@ impl MessageScheduleConfig {
|| {
carry
.map(|carry| pallas::Base::from_u64(carry as u64))
.ok_or(Error::SynthesisError)
.ok_or(Error::Synthesis)
},
)?;
let (word, halves) = self.assign_word_and_halves(region, word, new_word_idx)?;

View File

@ -169,7 +169,7 @@ impl MessageScheduleConfig {
get_word_row(new_word_idx - 16) + 1,
|| {
word.map(|word| pallas::Base::from_u64(word as u64))
.ok_or(Error::SynthesisError)
.ok_or(Error::Synthesis)
},
)?;
region.assign_advice(
@ -179,7 +179,7 @@ impl MessageScheduleConfig {
|| {
carry
.map(|carry| pallas::Base::from_u64(carry as u64))
.ok_or(Error::SynthesisError)
.ok_or(Error::Synthesis)
},
)?;
let (word, halves) = self.assign_word_and_halves(region, word, new_word_idx)?;

View File

@ -90,7 +90,7 @@ impl<const DENSE: usize, const SPREAD: usize> SpreadVar<DENSE, SPREAD> {
row,
|| {
tag.map(|tag| pallas::Base::from_u64(tag as u64))
.ok_or(Error::SynthesisError)
.ok_or(Error::Synthesis)
},
)?;
@ -229,23 +229,20 @@ impl<F: FieldExt> SpreadTableChip<F> {
index,
|| {
row = rows.next();
row.map(|(tag, _, _)| tag).ok_or(Error::SynthesisError)
row.map(|(tag, _, _)| tag).ok_or(Error::Synthesis)
},
)?;
table.assign_cell(
|| "dense",
config.table.dense,
index,
|| row.map(|(_, dense, _)| dense).ok_or(Error::SynthesisError),
|| row.map(|(_, dense, _)| dense).ok_or(Error::Synthesis),
)?;
table.assign_cell(
|| "spread",
config.table.spread,
index,
|| {
row.map(|(_, _, spread)| spread)
.ok_or(Error::SynthesisError)
},
|| row.map(|(_, _, spread)| spread).ok_or(Error::Synthesis),
)?;
}
@ -336,7 +333,7 @@ mod tests {
|| "spread_test",
|mut gate| {
let mut row = 0;
let mut add_row = |tag, dense, spread| {
let mut add_row = |tag, dense, spread| -> Result<(), Error> {
gate.assign_advice(|| "tag", config.input.tag, row, || Ok(tag))?;
gate.assign_advice(|| "dense", config.input.dense, row, || Ok(dense))?;
gate.assign_advice(