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<ol class="chapter"><li class="chapter-item expanded affix "><a href="../index.html">halo2</a></li><li class="chapter-item expanded "><a href="../concepts.html"><strong aria-hidden="true">1.</strong> Concepts</a></li><li><ol class="section"><li class="chapter-item expanded "><a href="../concepts/proofs.html"><strong aria-hidden="true">1.1.</strong> Proof systems</a></li><li class="chapter-item expanded "><a href="../concepts/arithmetization.html"><strong aria-hidden="true">1.2.</strong> UltraPLONK Arithmetization</a></li><li class="chapter-item expanded "><a href="../concepts/cores.html" class="active"><strong aria-hidden="true">1.3.</strong> Cores</a></li><li class="chapter-item expanded "><a href="../concepts/chips.html"><strong aria-hidden="true">1.4.</strong> Chips</a></li><li class="chapter-item expanded "><a href="../concepts/gadgets.html"><strong aria-hidden="true">1.5.</strong> Gadgets</a></li></ol></li><li class="chapter-item expanded "><a href="../user.html"><strong aria-hidden="true">2.</strong> User Documentation</a></li><li><ol class="section"><li class="chapter-item expanded "><a href="../user/simple-example.html"><strong aria-hidden="true">2.1.</strong> A simple example</a></li><li class="chapter-item expanded "><a href="../user/lookup-tables.html"><strong aria-hidden="true">2.2.</strong> Lookup tables</a></li><li class="chapter-item expanded "><a href="../user/gadgets.html"><strong aria-hidden="true">2.3.</strong> Gadgets</a></li><li class="chapter-item expanded "><a href="../user/tips-and-tricks.html"><strong aria-hidden="true">2.4.</strong> Tips and tricks</a></li></ol></li><li class="chapter-item expanded "><a href="../design.html"><strong aria-hidden="true">3.</strong> Design</a></li><li><ol class="section"><li class="chapter-item expanded "><a href="../design/proving-system.html"><strong aria-hidden="true">3.1.</strong> Proving system</a></li><li><ol class="section"><li class="chapter-item expanded "><a href="../design/proving-system/lookup.html"><strong aria-hidden="true">3.1.1.</strong> Lookup argument</a></li><li class="chapter-item expanded "><a href="../design/proving-system/permutation.html"><strong aria-hidden="true">3.1.2.</strong> Permutation argument</a></li><li class="chapter-item expanded "><a href="../design/proving-system/circuit-commitments.html"><strong aria-hidden="true">3.1.3.</strong> Circuit commitments</a></li><li class="chapter-item expanded "><a href="../design/proving-system/vanishing.html"><strong aria-hidden="true">3.1.4.</strong> Vanishing argument</a></li><li class="chapter-item expanded "><a href="../design/proving-system/multipoint-opening.html"><strong aria-hidden="true">3.1.5.</strong> Multipoint opening argument</a></li><li class="chapter-item expanded "><a href="../design/proving-system/inner-product.html"><strong aria-hidden="true">3.1.6.</strong> Inner product argument</a></li><li class="chapter-item expanded "><a href="../design/proving-system/comparison.html"><strong aria-hidden="true">3.1.7.</strong> Comparison to other work</a></li></ol></li><li class="chapter-item expanded "><a href="../design/implementation.html"><strong aria-hidden="true">3.2.</strong> Implementation</a></li><li class="chapter-item expanded "><a href="../design/gadgets.html"><strong aria-hidden="true">3.3.</strong> Gadgets</a></li><li><ol class="section"><li class="chapter-item expanded "><a href="../design/gadgets/sha256.html"><strong aria-hidden="true">3.3.1.</strong> SHA-256</a></li><li><ol class="section"><li class="chapter-item expanded "><a href="../design/gadgets/sha256/table16.html"><strong aria-hidden="true">3.3.1.1.</strong> 16-bit table chip</a></li></ol></li></ol></li></ol></li><li class="chapter-item expanded "><a href="../background.html"><strong aria-hidden="true">4.</strong> Background Material</a></li><li><ol class="section"><li class="chapter-item expanded "><a href="../background/fields.html"><strong aria-hidden="true">4.1.</strong> Fields</a></li><li class="chapter-item expanded "><a href="../background/polynomials.html"><strong aria-hidden="true">4.2.</strong> Polynomials</a></li><li class="chapter-item expanded "><a href="../background/groups.html"><strong aria-hidden="true">4.3.</strong> Cryptographic groups</a></li><li class="chapter-item expanded "><a href="../background/curves.html"><strong aria-hidden="true">4.4.</strong> Elliptic curves</a></li><li class="chapter-item expanded "><a href="../background/upa.html"><strong aria-hidden="true">4.5.</strong> UltraPLONK arithmetisation</a></li><li class="chapter-item expanded "><a href="../background/pc-ipa.html"><strong aria-hidden="true">4.6.</strong> Polynomial commitment using inner product argument</a></li><li class="chapter-item expanded "><a href="../background/recursion.html"><strong aria-hidden="true">4.7.</strong> Recursion</a></li></ol></li></ol>
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<h1 class="menu-title">The halo2 Book</h1>
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<h1><a class="header" href="#cores" id="cores">Cores</a></h1>
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<p>The previous section gives a fairly low-level description of a circuit. When implementing circuits we will
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typically use a higher-level API which aims for the desirable characteristics of auditability,
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efficiency, modularity, and expressiveness.</p>
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<p>Some of the terminology and concepts used in this API are taken from an analogy with
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integrated circuit design and layout. <a href="https://opencores.org/">As for integrated circuits</a>,
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the above desirable characteristics are easier to obtain by composing <em><strong>cores</strong></em> that provide
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efficient pre-built implementations of particular functionality.</p>
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<p>For example, we might have cores that implement particular cryptographic primitives such as a
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hash function or cipher, or algorithms like scalar multiplication or pairings.</p>
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<p>In UPA, it is possible to build up arbitrary logic just from standard gates that do field
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multiplication and addition. However, very significant efficiency gains can be obtained by
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using custom gates.</p>
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<p>Using our API, we define cores that "know" how to use particular sets of custom gates. This
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creates an abstraction layer that isolates the implementation of a high-level circuit from the
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complexity of using custom gates directly.</p>
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<blockquote>
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<p>Even if we sometimes need to "wear two hats", by implementing both a high-level circuit and
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the cores that it uses, the intention is that this separation will result in code that is
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easier to understand, audit, and maintain/reuse. This is partly because some potential
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implementation errors are ruled out by construction.</p>
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</blockquote>
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<p>Gates in UPA refer to cells by <em><strong>relative references</strong></em>, i.e. to the cell in a given column,
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and the row at a given offset relative to the one in which the gate's selector is set. We call
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this an <em><strong>offset reference</strong></em> when the offset is nonzero (i.e. offset references are a subset
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of relative references).</p>
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<p>Relative references contrast with <em><strong>absolute references</strong></em> used in equality constraints,
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which can point to any cell.</p>
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<p>The motivation for offset references is to reduce the number of columns needed in the
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configuration, which reduces proof size. If we did not have offset references then we would
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need a column to hold each value referred to by a custom gate, and we would need to use
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equality constraints to copy values from other cells of the circuit into that column. With
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offset references, we not only need fewer columns; we also do not need equality constraints to
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be supported for all of those columns, which improves efficiency.</p>
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<p>In R1CS (which may be more familiar to some readers, but don't worry if it isn't), a circuit
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consists of a "sea of gates" with no semantically significant ordering. Because of offset
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references, the order of rows in a UPA circuit, on the other hand, <em>is</em> significant. We're
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going to make some simplifying assumptions and define some abstractions to tame the resulting
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complexity: the aim will be that, <a href="gadgets.html">at the gadget level</a> where we do most of our
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circuit construction, we will not have to deal with relative references or with gate layout
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explicitly.</p>
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<p>We will partition a circuit into <em><strong>regions</strong></em>, where each region contains a disjoint subset
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of cells, and relative references only ever point <em>within</em> a region. Part of the responsibility
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of a core implementation is to ensure that gates that make offset references are laid out in
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the correct positions in a region.</p>
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<p>Given the set of regions and their <em><strong>shapes</strong></em>, we will use a separate <em><strong>floor planner</strong></em>
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to decide where (i.e. at what starting row) each region is placed. There is a default floor
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planner that implements a very general algorithm, but you can write your own floor planner if
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you need to.</p>
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<p>Floor planning will in general leave gaps in the matrix, because the gates in a given row did
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not use all available columns. These are filled in ---as far as possible--- by gates that do
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not require offset references, which allows them to be placed on any row.</p>
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<p>Cores can also define lookup tables. If more than one table is defined for the same lookup
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argument, we can use a <em><strong>tag column</strong></em> to specify which table is used on each row. It is also
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possible to perform a lookup in the union of several tables (limited by the polynomial degree
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bound).</p>
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