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circuit: Add region layout diagrams for y_switch constraint 

Helps to see why we can't optimise it to remove the `prev` query.
This commit is contained in:
Jack Grigg 2021-07-29 20:57:09 +01:00
parent 6aa85fcdfe
commit 9af22a8cbc
1 changed files with 11 additions and 0 deletions
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11
src/circuit/gadget/ecc/chip/mul/complete.rs
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@ -42,6 +42,11 @@ impl Config {
/// addition gate (controlled by `q_mul`) already checks scalar decomposition for
/// the other bits.
pub(super) fn create_gate(&self, meta: &mut ConstraintSystem<pallas::Base>) {
// | y_p | z_complete |
// --------------------
// | y_p | z_{i + 1} |
// | | base_y |
// | | z_i |
meta.create_gate(
"Decompose scalar for complete bits of variable-base mul",
|meta| {
@ -122,6 +127,12 @@ impl Config {
// Each iteration uses 2 rows (two complete additions)
let row = 2 * iter;
// | x_p | y_p | x_qr | y_qr | z_complete |
// ------------------------------------------
// | U_x | U_y | acc_x | acc_y | z_{i + 1} | row + offset
// |acc_x|acc_y|acc+U_x|acc+U_y| base_y |
// | | | res_x | res_y | z_i |
// Update `z`.
z = {
// z_next = z_cur * 2 + k_next